1/*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_illegal(DisasContext *ctx, arg_empty *a)
22{
23    gen_exception_illegal(ctx);
24    return true;
25}
26
27static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
28{
29     REQUIRE_64BIT(ctx);
30     return trans_illegal(ctx, a);
31}
32
33static bool trans_lui(DisasContext *ctx, arg_lui *a)
34{
35    if (a->rd != 0) {
36        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
37    }
38    return true;
39}
40
41static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
42{
43    if (a->rd != 0) {
44        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
45    }
46    return true;
47}
48
49static bool trans_jal(DisasContext *ctx, arg_jal *a)
50{
51    gen_jal(ctx, a->rd, a->imm);
52    return true;
53}
54
55static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
56{
57    TCGLabel *misaligned = NULL;
58
59    tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
60    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
61
62    if (!has_ext(ctx, RVC)) {
63        TCGv t0 = tcg_temp_new();
64
65        misaligned = gen_new_label();
66        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
67        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
68        tcg_temp_free(t0);
69    }
70
71    if (a->rd != 0) {
72        tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
73    }
74    tcg_gen_lookup_and_goto_ptr();
75
76    if (misaligned) {
77        gen_set_label(misaligned);
78        gen_exception_inst_addr_mis(ctx);
79    }
80    ctx->base.is_jmp = DISAS_NORETURN;
81
82    return true;
83}
84
85static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
86{
87    TCGLabel *l = gen_new_label();
88    TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
89    TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
90
91    tcg_gen_brcond_tl(cond, src1, src2, l);
92    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
93
94    gen_set_label(l); /* branch taken */
95
96    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
97        /* misaligned */
98        gen_exception_inst_addr_mis(ctx);
99    } else {
100        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
101    }
102    ctx->base.is_jmp = DISAS_NORETURN;
103
104    return true;
105}
106
107static bool trans_beq(DisasContext *ctx, arg_beq *a)
108{
109    return gen_branch(ctx, a, TCG_COND_EQ);
110}
111
112static bool trans_bne(DisasContext *ctx, arg_bne *a)
113{
114    return gen_branch(ctx, a, TCG_COND_NE);
115}
116
117static bool trans_blt(DisasContext *ctx, arg_blt *a)
118{
119    return gen_branch(ctx, a, TCG_COND_LT);
120}
121
122static bool trans_bge(DisasContext *ctx, arg_bge *a)
123{
124    return gen_branch(ctx, a, TCG_COND_GE);
125}
126
127static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
128{
129    return gen_branch(ctx, a, TCG_COND_LTU);
130}
131
132static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
133{
134    return gen_branch(ctx, a, TCG_COND_GEU);
135}
136
137static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
138{
139    TCGv dest = dest_gpr(ctx, a->rd);
140    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
141
142    if (a->imm) {
143        TCGv temp = temp_new(ctx);
144        tcg_gen_addi_tl(temp, addr, a->imm);
145        addr = temp;
146    }
147
148    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
149    gen_set_gpr(ctx, a->rd, dest);
150    return true;
151}
152
153static bool trans_lb(DisasContext *ctx, arg_lb *a)
154{
155    return gen_load(ctx, a, MO_SB);
156}
157
158static bool trans_lh(DisasContext *ctx, arg_lh *a)
159{
160    return gen_load(ctx, a, MO_TESW);
161}
162
163static bool trans_lw(DisasContext *ctx, arg_lw *a)
164{
165    return gen_load(ctx, a, MO_TESL);
166}
167
168static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
169{
170    return gen_load(ctx, a, MO_UB);
171}
172
173static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
174{
175    return gen_load(ctx, a, MO_TEUW);
176}
177
178static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
179{
180    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
181    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
182
183    if (a->imm) {
184        TCGv temp = temp_new(ctx);
185        tcg_gen_addi_tl(temp, addr, a->imm);
186        addr = temp;
187    }
188
189    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
190    return true;
191}
192
193static bool trans_sb(DisasContext *ctx, arg_sb *a)
194{
195    return gen_store(ctx, a, MO_SB);
196}
197
198static bool trans_sh(DisasContext *ctx, arg_sh *a)
199{
200    return gen_store(ctx, a, MO_TESW);
201}
202
203static bool trans_sw(DisasContext *ctx, arg_sw *a)
204{
205    return gen_store(ctx, a, MO_TESL);
206}
207
208static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
209{
210    REQUIRE_64BIT(ctx);
211    return gen_load(ctx, a, MO_TEUL);
212}
213
214static bool trans_ld(DisasContext *ctx, arg_ld *a)
215{
216    REQUIRE_64BIT(ctx);
217    return gen_load(ctx, a, MO_TEQ);
218}
219
220static bool trans_sd(DisasContext *ctx, arg_sd *a)
221{
222    REQUIRE_64BIT(ctx);
223    return gen_store(ctx, a, MO_TEQ);
224}
225
226static bool trans_addi(DisasContext *ctx, arg_addi *a)
227{
228    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
229}
230
231static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
232{
233    tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
234}
235
236static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
237{
238    tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
239}
240
241static bool trans_slti(DisasContext *ctx, arg_slti *a)
242{
243    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
244}
245
246static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
247{
248    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
249}
250
251static bool trans_xori(DisasContext *ctx, arg_xori *a)
252{
253    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
254}
255
256static bool trans_ori(DisasContext *ctx, arg_ori *a)
257{
258    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
259}
260
261static bool trans_andi(DisasContext *ctx, arg_andi *a)
262{
263    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
264}
265
266static bool trans_slli(DisasContext *ctx, arg_slli *a)
267{
268    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
269}
270
271static bool trans_srli(DisasContext *ctx, arg_srli *a)
272{
273    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
274}
275
276static bool trans_srai(DisasContext *ctx, arg_srai *a)
277{
278    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
279}
280
281static bool trans_add(DisasContext *ctx, arg_add *a)
282{
283    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
284}
285
286static bool trans_sub(DisasContext *ctx, arg_sub *a)
287{
288    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
289}
290
291static bool trans_sll(DisasContext *ctx, arg_sll *a)
292{
293    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
294}
295
296static bool trans_slt(DisasContext *ctx, arg_slt *a)
297{
298    return gen_arith(ctx, a, EXT_SIGN, gen_slt);
299}
300
301static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
302{
303    return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
304}
305
306static bool trans_xor(DisasContext *ctx, arg_xor *a)
307{
308    return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
309}
310
311static bool trans_srl(DisasContext *ctx, arg_srl *a)
312{
313    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
314}
315
316static bool trans_sra(DisasContext *ctx, arg_sra *a)
317{
318    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
319}
320
321static bool trans_or(DisasContext *ctx, arg_or *a)
322{
323    return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
324}
325
326static bool trans_and(DisasContext *ctx, arg_and *a)
327{
328    return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
329}
330
331static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
332{
333    REQUIRE_64BIT(ctx);
334    ctx->w = true;
335    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
336}
337
338static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
339{
340    REQUIRE_64BIT(ctx);
341    ctx->w = true;
342    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
343}
344
345static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
346{
347    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
348}
349
350static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
351{
352    REQUIRE_64BIT(ctx);
353    ctx->w = true;
354    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
355}
356
357static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
358{
359    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
360}
361
362static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
363{
364    REQUIRE_64BIT(ctx);
365    ctx->w = true;
366    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
367}
368
369static bool trans_addw(DisasContext *ctx, arg_addw *a)
370{
371    REQUIRE_64BIT(ctx);
372    ctx->w = true;
373    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
374}
375
376static bool trans_subw(DisasContext *ctx, arg_subw *a)
377{
378    REQUIRE_64BIT(ctx);
379    ctx->w = true;
380    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
381}
382
383static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
384{
385    REQUIRE_64BIT(ctx);
386    ctx->w = true;
387    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
388}
389
390static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
391{
392    REQUIRE_64BIT(ctx);
393    ctx->w = true;
394    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
395}
396
397static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
398{
399    REQUIRE_64BIT(ctx);
400    ctx->w = true;
401    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
402}
403
404static bool trans_fence(DisasContext *ctx, arg_fence *a)
405{
406    /* FENCE is a full memory barrier. */
407    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
408    return true;
409}
410
411static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
412{
413    if (!ctx->ext_ifencei) {
414        return false;
415    }
416
417    /*
418     * FENCE_I is a no-op in QEMU,
419     * however we need to end the translation block
420     */
421    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
422    tcg_gen_exit_tb(NULL, 0);
423    ctx->base.is_jmp = DISAS_NORETURN;
424    return true;
425}
426
427static bool do_csr_post(DisasContext *ctx)
428{
429    /* We may have changed important cpu state -- exit to main loop. */
430    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
431    tcg_gen_exit_tb(NULL, 0);
432    ctx->base.is_jmp = DISAS_NORETURN;
433    return true;
434}
435
436static bool do_csrr(DisasContext *ctx, int rd, int rc)
437{
438    TCGv dest = dest_gpr(ctx, rd);
439    TCGv_i32 csr = tcg_constant_i32(rc);
440
441    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
442        gen_io_start();
443    }
444    gen_helper_csrr(dest, cpu_env, csr);
445    gen_set_gpr(ctx, rd, dest);
446    return do_csr_post(ctx);
447}
448
449static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
450{
451    TCGv_i32 csr = tcg_constant_i32(rc);
452
453    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
454        gen_io_start();
455    }
456    gen_helper_csrw(cpu_env, csr, src);
457    return do_csr_post(ctx);
458}
459
460static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
461{
462    TCGv dest = dest_gpr(ctx, rd);
463    TCGv_i32 csr = tcg_constant_i32(rc);
464
465    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
466        gen_io_start();
467    }
468    gen_helper_csrrw(dest, cpu_env, csr, src, mask);
469    gen_set_gpr(ctx, rd, dest);
470    return do_csr_post(ctx);
471}
472
473static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
474{
475    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
476
477    /*
478     * If rd == 0, the insn shall not read the csr, nor cause any of the
479     * side effects that might occur on a csr read.
480     */
481    if (a->rd == 0) {
482        return do_csrw(ctx, a->csr, src);
483    }
484
485    TCGv mask = tcg_constant_tl(-1);
486    return do_csrrw(ctx, a->rd, a->csr, src, mask);
487}
488
489static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
490{
491    /*
492     * If rs1 == 0, the insn shall not write to the csr at all, nor
493     * cause any of the side effects that might occur on a csr write.
494     * Note that if rs1 specifies a register other than x0, holding
495     * a zero value, the instruction will still attempt to write the
496     * unmodified value back to the csr and will cause side effects.
497     */
498    if (a->rs1 == 0) {
499        return do_csrr(ctx, a->rd, a->csr);
500    }
501
502    TCGv ones = tcg_constant_tl(-1);
503    TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
504    return do_csrrw(ctx, a->rd, a->csr, ones, mask);
505}
506
507static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
508{
509    /*
510     * If rs1 == 0, the insn shall not write to the csr at all, nor
511     * cause any of the side effects that might occur on a csr write.
512     * Note that if rs1 specifies a register other than x0, holding
513     * a zero value, the instruction will still attempt to write the
514     * unmodified value back to the csr and will cause side effects.
515     */
516    if (a->rs1 == 0) {
517        return do_csrr(ctx, a->rd, a->csr);
518    }
519
520    TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
521    return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
522}
523
524static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
525{
526    TCGv src = tcg_constant_tl(a->rs1);
527
528    /*
529     * If rd == 0, the insn shall not read the csr, nor cause any of the
530     * side effects that might occur on a csr read.
531     */
532    if (a->rd == 0) {
533        return do_csrw(ctx, a->csr, src);
534    }
535
536    TCGv mask = tcg_constant_tl(-1);
537    return do_csrrw(ctx, a->rd, a->csr, src, mask);
538}
539
540static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
541{
542    /*
543     * If rs1 == 0, the insn shall not write to the csr at all, nor
544     * cause any of the side effects that might occur on a csr write.
545     * Note that if rs1 specifies a register other than x0, holding
546     * a zero value, the instruction will still attempt to write the
547     * unmodified value back to the csr and will cause side effects.
548     */
549    if (a->rs1 == 0) {
550        return do_csrr(ctx, a->rd, a->csr);
551    }
552
553    TCGv ones = tcg_constant_tl(-1);
554    TCGv mask = tcg_constant_tl(a->rs1);
555    return do_csrrw(ctx, a->rd, a->csr, ones, mask);
556}
557
558static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
559{
560    /*
561     * If rs1 == 0, the insn shall not write to the csr at all, nor
562     * cause any of the side effects that might occur on a csr write.
563     * Note that if rs1 specifies a register other than x0, holding
564     * a zero value, the instruction will still attempt to write the
565     * unmodified value back to the csr and will cause side effects.
566     */
567    if (a->rs1 == 0) {
568        return do_csrr(ctx, a->rd, a->csr);
569    }
570
571    TCGv mask = tcg_constant_tl(a->rs1);
572    return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
573}
574