1/*
2 * RISC-V translation routines for the RVXI Base Integer Instruction Set.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_illegal(DisasContext *ctx, arg_empty *a)
22{
23    gen_exception_illegal(ctx);
24    return true;
25}
26
27static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
28{
29     REQUIRE_64BIT(ctx);
30     return trans_illegal(ctx, a);
31}
32
33static bool trans_lui(DisasContext *ctx, arg_lui *a)
34{
35    if (a->rd != 0) {
36        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
37    }
38    return true;
39}
40
41static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
42{
43    if (a->rd != 0) {
44        tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
45    }
46    return true;
47}
48
49static bool trans_jal(DisasContext *ctx, arg_jal *a)
50{
51    gen_jal(ctx, a->rd, a->imm);
52    return true;
53}
54
55static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
56{
57    /* no chaining with JALR */
58    TCGLabel *misaligned = NULL;
59    TCGv t0 = tcg_temp_new();
60
61
62    gen_get_gpr(ctx, cpu_pc, a->rs1);
63    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
64    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
65
66    if (!has_ext(ctx, RVC)) {
67        misaligned = gen_new_label();
68        tcg_gen_andi_tl(t0, cpu_pc, 0x2);
69        tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
70    }
71
72    if (a->rd != 0) {
73        tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
74    }
75    lookup_and_goto_ptr(ctx);
76
77    if (misaligned) {
78        gen_set_label(misaligned);
79        gen_exception_inst_addr_mis(ctx);
80    }
81    ctx->base.is_jmp = DISAS_NORETURN;
82
83    tcg_temp_free(t0);
84    return true;
85}
86
87static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
88{
89    TCGLabel *l = gen_new_label();
90    TCGv source1, source2;
91    source1 = tcg_temp_new();
92    source2 = tcg_temp_new();
93    gen_get_gpr(ctx, source1, a->rs1);
94    gen_get_gpr(ctx, source2, a->rs2);
95
96    tcg_gen_brcond_tl(cond, source1, source2, l);
97    gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
98    gen_set_label(l); /* branch taken */
99
100    if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
101        /* misaligned */
102        gen_exception_inst_addr_mis(ctx);
103    } else {
104        gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
105    }
106    ctx->base.is_jmp = DISAS_NORETURN;
107
108    tcg_temp_free(source1);
109    tcg_temp_free(source2);
110
111    return true;
112}
113
114static bool trans_beq(DisasContext *ctx, arg_beq *a)
115{
116    return gen_branch(ctx, a, TCG_COND_EQ);
117}
118
119static bool trans_bne(DisasContext *ctx, arg_bne *a)
120{
121    return gen_branch(ctx, a, TCG_COND_NE);
122}
123
124static bool trans_blt(DisasContext *ctx, arg_blt *a)
125{
126    return gen_branch(ctx, a, TCG_COND_LT);
127}
128
129static bool trans_bge(DisasContext *ctx, arg_bge *a)
130{
131    return gen_branch(ctx, a, TCG_COND_GE);
132}
133
134static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
135{
136    return gen_branch(ctx, a, TCG_COND_LTU);
137}
138
139static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
140{
141    return gen_branch(ctx, a, TCG_COND_GEU);
142}
143
144static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
145{
146    TCGv t0 = tcg_temp_new();
147    TCGv t1 = tcg_temp_new();
148    gen_get_gpr(ctx, t0, a->rs1);
149    tcg_gen_addi_tl(t0, t0, a->imm);
150
151    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
152    gen_set_gpr(ctx, a->rd, t1);
153    tcg_temp_free(t0);
154    tcg_temp_free(t1);
155    return true;
156}
157
158static bool trans_lb(DisasContext *ctx, arg_lb *a)
159{
160    return gen_load(ctx, a, MO_SB);
161}
162
163static bool trans_lh(DisasContext *ctx, arg_lh *a)
164{
165    return gen_load(ctx, a, MO_TESW);
166}
167
168static bool trans_lw(DisasContext *ctx, arg_lw *a)
169{
170    return gen_load(ctx, a, MO_TESL);
171}
172
173static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
174{
175    return gen_load(ctx, a, MO_UB);
176}
177
178static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
179{
180    return gen_load(ctx, a, MO_TEUW);
181}
182
183static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
184{
185    TCGv t0 = tcg_temp_new();
186    TCGv dat = tcg_temp_new();
187    gen_get_gpr(ctx, t0, a->rs1);
188    tcg_gen_addi_tl(t0, t0, a->imm);
189    gen_get_gpr(ctx, dat, a->rs2);
190
191    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
192    tcg_temp_free(t0);
193    tcg_temp_free(dat);
194    return true;
195}
196
197
198static bool trans_sb(DisasContext *ctx, arg_sb *a)
199{
200    return gen_store(ctx, a, MO_SB);
201}
202
203static bool trans_sh(DisasContext *ctx, arg_sh *a)
204{
205    return gen_store(ctx, a, MO_TESW);
206}
207
208static bool trans_sw(DisasContext *ctx, arg_sw *a)
209{
210    return gen_store(ctx, a, MO_TESL);
211}
212
213static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
214{
215    REQUIRE_64BIT(ctx);
216    return gen_load(ctx, a, MO_TEUL);
217}
218
219static bool trans_ld(DisasContext *ctx, arg_ld *a)
220{
221    REQUIRE_64BIT(ctx);
222    return gen_load(ctx, a, MO_TEQ);
223}
224
225static bool trans_sd(DisasContext *ctx, arg_sd *a)
226{
227    REQUIRE_64BIT(ctx);
228    return gen_store(ctx, a, MO_TEQ);
229}
230
231static bool trans_addi(DisasContext *ctx, arg_addi *a)
232{
233    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
234}
235
236static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
237{
238    tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
239}
240
241static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
242{
243    tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
244}
245
246static bool trans_slti(DisasContext *ctx, arg_slti *a)
247{
248    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
249}
250
251static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
252{
253    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
254}
255
256static bool trans_xori(DisasContext *ctx, arg_xori *a)
257{
258    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
259}
260
261static bool trans_ori(DisasContext *ctx, arg_ori *a)
262{
263    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
264}
265
266static bool trans_andi(DisasContext *ctx, arg_andi *a)
267{
268    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
269}
270
271static bool trans_slli(DisasContext *ctx, arg_slli *a)
272{
273    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
274}
275
276static bool trans_srli(DisasContext *ctx, arg_srli *a)
277{
278    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
279}
280
281static bool trans_srai(DisasContext *ctx, arg_srai *a)
282{
283    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
284}
285
286static bool trans_add(DisasContext *ctx, arg_add *a)
287{
288    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
289}
290
291static bool trans_sub(DisasContext *ctx, arg_sub *a)
292{
293    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
294}
295
296static bool trans_sll(DisasContext *ctx, arg_sll *a)
297{
298    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
299}
300
301static bool trans_slt(DisasContext *ctx, arg_slt *a)
302{
303    return gen_arith(ctx, a, EXT_SIGN, gen_slt);
304}
305
306static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
307{
308    return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
309}
310
311static bool trans_xor(DisasContext *ctx, arg_xor *a)
312{
313    return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
314}
315
316static bool trans_srl(DisasContext *ctx, arg_srl *a)
317{
318    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
319}
320
321static bool trans_sra(DisasContext *ctx, arg_sra *a)
322{
323    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
324}
325
326static bool trans_or(DisasContext *ctx, arg_or *a)
327{
328    return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
329}
330
331static bool trans_and(DisasContext *ctx, arg_and *a)
332{
333    return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
334}
335
336static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
337{
338    REQUIRE_64BIT(ctx);
339    ctx->w = true;
340    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
341}
342
343static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
344{
345    REQUIRE_64BIT(ctx);
346    ctx->w = true;
347    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
348}
349
350static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
351{
352    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
353}
354
355static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
356{
357    REQUIRE_64BIT(ctx);
358    ctx->w = true;
359    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
360}
361
362static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
363{
364    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
365}
366
367static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
368{
369    REQUIRE_64BIT(ctx);
370    ctx->w = true;
371    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
372}
373
374static bool trans_addw(DisasContext *ctx, arg_addw *a)
375{
376    REQUIRE_64BIT(ctx);
377    ctx->w = true;
378    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
379}
380
381static bool trans_subw(DisasContext *ctx, arg_subw *a)
382{
383    REQUIRE_64BIT(ctx);
384    ctx->w = true;
385    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
386}
387
388static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
389{
390    REQUIRE_64BIT(ctx);
391    ctx->w = true;
392    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
393}
394
395static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
396{
397    REQUIRE_64BIT(ctx);
398    ctx->w = true;
399    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
400}
401
402static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
403{
404    REQUIRE_64BIT(ctx);
405    ctx->w = true;
406    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
407}
408
409static bool trans_fence(DisasContext *ctx, arg_fence *a)
410{
411    /* FENCE is a full memory barrier. */
412    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
413    return true;
414}
415
416static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
417{
418    if (!ctx->ext_ifencei) {
419        return false;
420    }
421
422    /*
423     * FENCE_I is a no-op in QEMU,
424     * however we need to end the translation block
425     */
426    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
427    exit_tb(ctx);
428    ctx->base.is_jmp = DISAS_NORETURN;
429    return true;
430}
431
432#define RISCV_OP_CSR_PRE do {\
433    source1 = tcg_temp_new(); \
434    csr_store = tcg_temp_new(); \
435    dest = tcg_temp_new(); \
436    rs1_pass = tcg_temp_new(); \
437    gen_get_gpr(ctx, source1, a->rs1); \
438    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
439    tcg_gen_movi_tl(rs1_pass, a->rs1); \
440    tcg_gen_movi_tl(csr_store, a->csr); \
441    gen_io_start();\
442} while (0)
443
444#define RISCV_OP_CSR_POST do {\
445    gen_set_gpr(ctx, a->rd, dest); \
446    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
447    exit_tb(ctx); \
448    ctx->base.is_jmp = DISAS_NORETURN; \
449    tcg_temp_free(source1); \
450    tcg_temp_free(csr_store); \
451    tcg_temp_free(dest); \
452    tcg_temp_free(rs1_pass); \
453} while (0)
454
455
456static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
457{
458    TCGv source1, csr_store, dest, rs1_pass;
459    RISCV_OP_CSR_PRE;
460    gen_helper_csrrw(dest, cpu_env, source1, csr_store);
461    RISCV_OP_CSR_POST;
462    return true;
463}
464
465static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
466{
467    TCGv source1, csr_store, dest, rs1_pass;
468    RISCV_OP_CSR_PRE;
469    gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
470    RISCV_OP_CSR_POST;
471    return true;
472}
473
474static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
475{
476    TCGv source1, csr_store, dest, rs1_pass;
477    RISCV_OP_CSR_PRE;
478    gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
479    RISCV_OP_CSR_POST;
480    return true;
481}
482
483static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
484{
485    TCGv source1, csr_store, dest, rs1_pass;
486    RISCV_OP_CSR_PRE;
487    gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
488    RISCV_OP_CSR_POST;
489    return true;
490}
491
492static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
493{
494    TCGv source1, csr_store, dest, rs1_pass;
495    RISCV_OP_CSR_PRE;
496    gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
497    RISCV_OP_CSR_POST;
498    return true;
499}
500
501static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
502{
503    TCGv source1, csr_store, dest, rs1_pass;
504    RISCV_OP_CSR_PRE;
505    gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
506    RISCV_OP_CSR_POST;
507    return true;
508}
509