1/*
2 * RISC-V translation routines for the RV64F Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_FPU do {\
22    if (ctx->mstatus_fs == 0) \
23        return false;                       \
24} while (0)
25
26static bool trans_flw(DisasContext *ctx, arg_flw *a)
27{
28    TCGv t0 = tcg_temp_new();
29    gen_get_gpr(t0, a->rs1);
30    REQUIRE_FPU;
31    REQUIRE_EXT(ctx, RVF);
32    tcg_gen_addi_tl(t0, t0, a->imm);
33
34    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
35    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
36
37    tcg_temp_free(t0);
38    mark_fs_dirty(ctx);
39    return true;
40}
41
42static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
43{
44    TCGv t0 = tcg_temp_new();
45    gen_get_gpr(t0, a->rs1);
46
47    REQUIRE_FPU;
48    REQUIRE_EXT(ctx, RVF);
49    tcg_gen_addi_tl(t0, t0, a->imm);
50
51    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
52
53    tcg_temp_free(t0);
54    return true;
55}
56
57static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
58{
59    REQUIRE_FPU;
60    REQUIRE_EXT(ctx, RVF);
61    gen_set_rm(ctx, a->rm);
62    gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
63                       cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
64    mark_fs_dirty(ctx);
65    return true;
66}
67
68static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
69{
70    REQUIRE_FPU;
71    REQUIRE_EXT(ctx, RVF);
72    gen_set_rm(ctx, a->rm);
73    gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
74                       cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
75    mark_fs_dirty(ctx);
76    return true;
77}
78
79static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
80{
81    REQUIRE_FPU;
82    REQUIRE_EXT(ctx, RVF);
83    gen_set_rm(ctx, a->rm);
84    gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
85                        cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
86    mark_fs_dirty(ctx);
87    return true;
88}
89
90static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
91{
92    REQUIRE_FPU;
93    REQUIRE_EXT(ctx, RVF);
94    gen_set_rm(ctx, a->rm);
95    gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
96                        cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
97    mark_fs_dirty(ctx);
98    return true;
99}
100
101static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
102{
103    REQUIRE_FPU;
104    REQUIRE_EXT(ctx, RVF);
105
106    gen_set_rm(ctx, a->rm);
107    gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
108                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
109    mark_fs_dirty(ctx);
110    return true;
111}
112
113static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
114{
115    REQUIRE_FPU;
116    REQUIRE_EXT(ctx, RVF);
117
118    gen_set_rm(ctx, a->rm);
119    gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
120                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
121    mark_fs_dirty(ctx);
122    return true;
123}
124
125static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
126{
127    REQUIRE_FPU;
128    REQUIRE_EXT(ctx, RVF);
129
130    gen_set_rm(ctx, a->rm);
131    gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
132                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
133    mark_fs_dirty(ctx);
134    return true;
135}
136
137static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
138{
139    REQUIRE_FPU;
140    REQUIRE_EXT(ctx, RVF);
141
142    gen_set_rm(ctx, a->rm);
143    gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
144                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
145    mark_fs_dirty(ctx);
146    return true;
147}
148
149static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
150{
151    REQUIRE_FPU;
152    REQUIRE_EXT(ctx, RVF);
153
154    gen_set_rm(ctx, a->rm);
155    gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
156    mark_fs_dirty(ctx);
157    return true;
158}
159
160static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
161{
162    REQUIRE_FPU;
163    REQUIRE_EXT(ctx, RVF);
164
165    if (a->rs1 == a->rs2) { /* FMOV */
166        gen_check_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
167    } else { /* FSGNJ */
168        TCGv_i64 rs1 = tcg_temp_new_i64();
169        TCGv_i64 rs2 = tcg_temp_new_i64();
170
171        gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]);
172        gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
173
174        /* This formulation retains the nanboxing of rs2. */
175        tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 31);
176        tcg_temp_free_i64(rs1);
177        tcg_temp_free_i64(rs2);
178    }
179    mark_fs_dirty(ctx);
180    return true;
181}
182
183static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
184{
185    TCGv_i64 rs1, rs2, mask;
186
187    REQUIRE_FPU;
188    REQUIRE_EXT(ctx, RVF);
189
190    rs1 = tcg_temp_new_i64();
191    gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]);
192
193    if (a->rs1 == a->rs2) { /* FNEG */
194        tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(31, 1));
195    } else {
196        rs2 = tcg_temp_new_i64();
197        gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
198
199        /*
200         * Replace bit 31 in rs1 with inverse in rs2.
201         * This formulation retains the nanboxing of rs1.
202         */
203        mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1));
204        tcg_gen_nor_i64(rs2, rs2, mask);
205        tcg_gen_and_i64(rs1, mask, rs1);
206        tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2);
207
208        tcg_temp_free_i64(mask);
209        tcg_temp_free_i64(rs2);
210    }
211    tcg_temp_free_i64(rs1);
212
213    mark_fs_dirty(ctx);
214    return true;
215}
216
217static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
218{
219    TCGv_i64 rs1, rs2;
220
221    REQUIRE_FPU;
222    REQUIRE_EXT(ctx, RVF);
223
224    rs1 = tcg_temp_new_i64();
225    gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]);
226
227    if (a->rs1 == a->rs2) { /* FABS */
228        tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(31, 1));
229    } else {
230        rs2 = tcg_temp_new_i64();
231        gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
232
233        /*
234         * Xor bit 31 in rs1 with that in rs2.
235         * This formulation retains the nanboxing of rs1.
236         */
237        tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(31, 1));
238        tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2);
239
240        tcg_temp_free_i64(rs2);
241    }
242    tcg_temp_free_i64(rs1);
243
244    mark_fs_dirty(ctx);
245    return true;
246}
247
248static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
249{
250    REQUIRE_FPU;
251    REQUIRE_EXT(ctx, RVF);
252
253    gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
254                      cpu_fpr[a->rs2]);
255    mark_fs_dirty(ctx);
256    return true;
257}
258
259static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
260{
261    REQUIRE_FPU;
262    REQUIRE_EXT(ctx, RVF);
263
264    gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
265                      cpu_fpr[a->rs2]);
266    mark_fs_dirty(ctx);
267    return true;
268}
269
270static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
271{
272    REQUIRE_FPU;
273    REQUIRE_EXT(ctx, RVF);
274
275    TCGv t0 = tcg_temp_new();
276    gen_set_rm(ctx, a->rm);
277    gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
278    gen_set_gpr(a->rd, t0);
279    tcg_temp_free(t0);
280
281    return true;
282}
283
284static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
285{
286    REQUIRE_FPU;
287    REQUIRE_EXT(ctx, RVF);
288
289    TCGv t0 = tcg_temp_new();
290    gen_set_rm(ctx, a->rm);
291    gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
292    gen_set_gpr(a->rd, t0);
293    tcg_temp_free(t0);
294
295    return true;
296}
297
298static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
299{
300    /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
301    REQUIRE_FPU;
302    REQUIRE_EXT(ctx, RVF);
303
304    TCGv t0 = tcg_temp_new();
305
306#if defined(TARGET_RISCV64)
307    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
308#else
309    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
310#endif
311
312    gen_set_gpr(a->rd, t0);
313    tcg_temp_free(t0);
314
315    return true;
316}
317
318static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
319{
320    REQUIRE_FPU;
321    REQUIRE_EXT(ctx, RVF);
322    TCGv t0 = tcg_temp_new();
323    gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
324    gen_set_gpr(a->rd, t0);
325    tcg_temp_free(t0);
326    return true;
327}
328
329static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
330{
331    REQUIRE_FPU;
332    REQUIRE_EXT(ctx, RVF);
333    TCGv t0 = tcg_temp_new();
334    gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
335    gen_set_gpr(a->rd, t0);
336    tcg_temp_free(t0);
337    return true;
338}
339
340static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
341{
342    REQUIRE_FPU;
343    REQUIRE_EXT(ctx, RVF);
344    TCGv t0 = tcg_temp_new();
345    gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
346    gen_set_gpr(a->rd, t0);
347    tcg_temp_free(t0);
348    return true;
349}
350
351static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
352{
353    REQUIRE_FPU;
354    REQUIRE_EXT(ctx, RVF);
355
356    TCGv t0 = tcg_temp_new();
357
358    gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
359
360    gen_set_gpr(a->rd, t0);
361    tcg_temp_free(t0);
362
363    return true;
364}
365
366static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
367{
368    REQUIRE_FPU;
369    REQUIRE_EXT(ctx, RVF);
370
371    TCGv t0 = tcg_temp_new();
372    gen_get_gpr(t0, a->rs1);
373
374    gen_set_rm(ctx, a->rm);
375    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
376
377    mark_fs_dirty(ctx);
378    tcg_temp_free(t0);
379
380    return true;
381}
382
383static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
384{
385    REQUIRE_FPU;
386    REQUIRE_EXT(ctx, RVF);
387
388    TCGv t0 = tcg_temp_new();
389    gen_get_gpr(t0, a->rs1);
390
391    gen_set_rm(ctx, a->rm);
392    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
393
394    mark_fs_dirty(ctx);
395    tcg_temp_free(t0);
396
397    return true;
398}
399
400static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
401{
402    /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
403    REQUIRE_FPU;
404    REQUIRE_EXT(ctx, RVF);
405
406    TCGv t0 = tcg_temp_new();
407    gen_get_gpr(t0, a->rs1);
408
409#if defined(TARGET_RISCV64)
410    tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
411#else
412    tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
413#endif
414    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
415
416    mark_fs_dirty(ctx);
417    tcg_temp_free(t0);
418
419    return true;
420}
421
422#ifdef TARGET_RISCV64
423static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
424{
425    REQUIRE_FPU;
426    REQUIRE_EXT(ctx, RVF);
427
428    TCGv t0 = tcg_temp_new();
429    gen_set_rm(ctx, a->rm);
430    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
431    gen_set_gpr(a->rd, t0);
432    tcg_temp_free(t0);
433    return true;
434}
435
436static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
437{
438    REQUIRE_FPU;
439    REQUIRE_EXT(ctx, RVF);
440
441    TCGv t0 = tcg_temp_new();
442    gen_set_rm(ctx, a->rm);
443    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
444    gen_set_gpr(a->rd, t0);
445    tcg_temp_free(t0);
446    return true;
447}
448
449static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
450{
451    REQUIRE_FPU;
452    REQUIRE_EXT(ctx, RVF);
453
454    TCGv t0 = tcg_temp_new();
455    gen_get_gpr(t0, a->rs1);
456
457    gen_set_rm(ctx, a->rm);
458    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
459
460    mark_fs_dirty(ctx);
461    tcg_temp_free(t0);
462    return true;
463}
464
465static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
466{
467    REQUIRE_FPU;
468    REQUIRE_EXT(ctx, RVF);
469
470    TCGv t0 = tcg_temp_new();
471    gen_get_gpr(t0, a->rs1);
472
473    gen_set_rm(ctx, a->rm);
474    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
475
476    mark_fs_dirty(ctx);
477    tcg_temp_free(t0);
478    return true;
479}
480#endif
481