1/*
2 * RISC-V translation routines for the RV64F Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_FPU do {\
22    if (ctx->mstatus_fs == 0) \
23        return false;                       \
24} while (0)
25
26static bool trans_flw(DisasContext *ctx, arg_flw *a)
27{
28    TCGv t0 = tcg_temp_new();
29    gen_get_gpr(t0, a->rs1);
30    REQUIRE_FPU;
31    REQUIRE_EXT(ctx, RVF);
32    tcg_gen_addi_tl(t0, t0, a->imm);
33
34    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
35    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
36
37    tcg_temp_free(t0);
38    mark_fs_dirty(ctx);
39    return true;
40}
41
42static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
43{
44    TCGv t0 = tcg_temp_new();
45    gen_get_gpr(t0, a->rs1);
46
47    REQUIRE_FPU;
48    REQUIRE_EXT(ctx, RVF);
49    tcg_gen_addi_tl(t0, t0, a->imm);
50
51    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
52
53    tcg_temp_free(t0);
54    return true;
55}
56
57static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
58{
59    REQUIRE_FPU;
60    REQUIRE_EXT(ctx, RVF);
61    gen_set_rm(ctx, a->rm);
62    gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
63                       cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
64    mark_fs_dirty(ctx);
65    return true;
66}
67
68static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
69{
70    REQUIRE_FPU;
71    REQUIRE_EXT(ctx, RVF);
72    gen_set_rm(ctx, a->rm);
73    gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
74                       cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
75    mark_fs_dirty(ctx);
76    return true;
77}
78
79static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
80{
81    REQUIRE_FPU;
82    REQUIRE_EXT(ctx, RVF);
83    gen_set_rm(ctx, a->rm);
84    gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
85                        cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
86    mark_fs_dirty(ctx);
87    return true;
88}
89
90static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
91{
92    REQUIRE_FPU;
93    REQUIRE_EXT(ctx, RVF);
94    gen_set_rm(ctx, a->rm);
95    gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
96                        cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
97    mark_fs_dirty(ctx);
98    return true;
99}
100
101static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
102{
103    REQUIRE_FPU;
104    REQUIRE_EXT(ctx, RVF);
105
106    gen_set_rm(ctx, a->rm);
107    gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
108                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
109    mark_fs_dirty(ctx);
110    return true;
111}
112
113static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
114{
115    REQUIRE_FPU;
116    REQUIRE_EXT(ctx, RVF);
117
118    gen_set_rm(ctx, a->rm);
119    gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
120                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
121    mark_fs_dirty(ctx);
122    return true;
123}
124
125static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
126{
127    REQUIRE_FPU;
128    REQUIRE_EXT(ctx, RVF);
129
130    gen_set_rm(ctx, a->rm);
131    gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
132                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
133    mark_fs_dirty(ctx);
134    return true;
135}
136
137static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
138{
139    REQUIRE_FPU;
140    REQUIRE_EXT(ctx, RVF);
141
142    gen_set_rm(ctx, a->rm);
143    gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
144                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
145    mark_fs_dirty(ctx);
146    return true;
147}
148
149static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
150{
151    REQUIRE_FPU;
152    REQUIRE_EXT(ctx, RVF);
153
154    gen_set_rm(ctx, a->rm);
155    gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
156    mark_fs_dirty(ctx);
157    return true;
158}
159
160static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
161{
162    REQUIRE_FPU;
163    REQUIRE_EXT(ctx, RVF);
164    if (a->rs1 == a->rs2) { /* FMOV */
165        tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
166    } else { /* FSGNJ */
167        tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
168                            0, 31);
169    }
170    mark_fs_dirty(ctx);
171    return true;
172}
173
174static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
175{
176    REQUIRE_FPU;
177    REQUIRE_EXT(ctx, RVF);
178    if (a->rs1 == a->rs2) { /* FNEG */
179        tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
180    } else {
181        TCGv_i64 t0 = tcg_temp_new_i64();
182        tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
183        tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
184        tcg_temp_free_i64(t0);
185    }
186    mark_fs_dirty(ctx);
187    return true;
188}
189
190static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
191{
192    REQUIRE_FPU;
193    REQUIRE_EXT(ctx, RVF);
194    if (a->rs1 == a->rs2) { /* FABS */
195        tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
196    } else {
197        TCGv_i64 t0 = tcg_temp_new_i64();
198        tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
199        tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
200        tcg_temp_free_i64(t0);
201    }
202    mark_fs_dirty(ctx);
203    return true;
204}
205
206static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
207{
208    REQUIRE_FPU;
209    REQUIRE_EXT(ctx, RVF);
210
211    gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
212                      cpu_fpr[a->rs2]);
213    mark_fs_dirty(ctx);
214    return true;
215}
216
217static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
218{
219    REQUIRE_FPU;
220    REQUIRE_EXT(ctx, RVF);
221
222    gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
223                      cpu_fpr[a->rs2]);
224    mark_fs_dirty(ctx);
225    return true;
226}
227
228static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
229{
230    REQUIRE_FPU;
231    REQUIRE_EXT(ctx, RVF);
232
233    TCGv t0 = tcg_temp_new();
234    gen_set_rm(ctx, a->rm);
235    gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
236    gen_set_gpr(a->rd, t0);
237    tcg_temp_free(t0);
238
239    return true;
240}
241
242static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
243{
244    REQUIRE_FPU;
245    REQUIRE_EXT(ctx, RVF);
246
247    TCGv t0 = tcg_temp_new();
248    gen_set_rm(ctx, a->rm);
249    gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
250    gen_set_gpr(a->rd, t0);
251    tcg_temp_free(t0);
252
253    return true;
254}
255
256static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
257{
258    /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
259    REQUIRE_FPU;
260    REQUIRE_EXT(ctx, RVF);
261
262    TCGv t0 = tcg_temp_new();
263
264#if defined(TARGET_RISCV64)
265    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
266#else
267    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
268#endif
269
270    gen_set_gpr(a->rd, t0);
271    tcg_temp_free(t0);
272
273    return true;
274}
275
276static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
277{
278    REQUIRE_FPU;
279    REQUIRE_EXT(ctx, RVF);
280    TCGv t0 = tcg_temp_new();
281    gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
282    gen_set_gpr(a->rd, t0);
283    tcg_temp_free(t0);
284    return true;
285}
286
287static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
288{
289    REQUIRE_FPU;
290    REQUIRE_EXT(ctx, RVF);
291    TCGv t0 = tcg_temp_new();
292    gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
293    gen_set_gpr(a->rd, t0);
294    tcg_temp_free(t0);
295    return true;
296}
297
298static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
299{
300    REQUIRE_FPU;
301    REQUIRE_EXT(ctx, RVF);
302    TCGv t0 = tcg_temp_new();
303    gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
304    gen_set_gpr(a->rd, t0);
305    tcg_temp_free(t0);
306    return true;
307}
308
309static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
310{
311    REQUIRE_FPU;
312    REQUIRE_EXT(ctx, RVF);
313
314    TCGv t0 = tcg_temp_new();
315
316    gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
317
318    gen_set_gpr(a->rd, t0);
319    tcg_temp_free(t0);
320
321    return true;
322}
323
324static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
325{
326    REQUIRE_FPU;
327    REQUIRE_EXT(ctx, RVF);
328
329    TCGv t0 = tcg_temp_new();
330    gen_get_gpr(t0, a->rs1);
331
332    gen_set_rm(ctx, a->rm);
333    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
334
335    mark_fs_dirty(ctx);
336    tcg_temp_free(t0);
337
338    return true;
339}
340
341static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
342{
343    REQUIRE_FPU;
344    REQUIRE_EXT(ctx, RVF);
345
346    TCGv t0 = tcg_temp_new();
347    gen_get_gpr(t0, a->rs1);
348
349    gen_set_rm(ctx, a->rm);
350    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
351
352    mark_fs_dirty(ctx);
353    tcg_temp_free(t0);
354
355    return true;
356}
357
358static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
359{
360    /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
361    REQUIRE_FPU;
362    REQUIRE_EXT(ctx, RVF);
363
364    TCGv t0 = tcg_temp_new();
365    gen_get_gpr(t0, a->rs1);
366
367#if defined(TARGET_RISCV64)
368    tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
369#else
370    tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
371#endif
372
373    mark_fs_dirty(ctx);
374    tcg_temp_free(t0);
375
376    return true;
377}
378
379#ifdef TARGET_RISCV64
380static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
381{
382    REQUIRE_FPU;
383    REQUIRE_EXT(ctx, RVF);
384
385    TCGv t0 = tcg_temp_new();
386    gen_set_rm(ctx, a->rm);
387    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
388    gen_set_gpr(a->rd, t0);
389    tcg_temp_free(t0);
390    return true;
391}
392
393static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
394{
395    REQUIRE_FPU;
396    REQUIRE_EXT(ctx, RVF);
397
398    TCGv t0 = tcg_temp_new();
399    gen_set_rm(ctx, a->rm);
400    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
401    gen_set_gpr(a->rd, t0);
402    tcg_temp_free(t0);
403    return true;
404}
405
406static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
407{
408    REQUIRE_FPU;
409    REQUIRE_EXT(ctx, RVF);
410
411    TCGv t0 = tcg_temp_new();
412    gen_get_gpr(t0, a->rs1);
413
414    gen_set_rm(ctx, a->rm);
415    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
416
417    mark_fs_dirty(ctx);
418    tcg_temp_free(t0);
419    return true;
420}
421
422static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
423{
424    REQUIRE_FPU;
425    REQUIRE_EXT(ctx, RVF);
426
427    TCGv t0 = tcg_temp_new();
428    gen_get_gpr(t0, a->rs1);
429
430    gen_set_rm(ctx, a->rm);
431    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
432
433    mark_fs_dirty(ctx);
434    tcg_temp_free(t0);
435    return true;
436}
437#endif
438