1/*
2 * RISC-V translation routines for the RV64F Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_FPU do {\
22    if (ctx->mstatus_fs == 0) \
23        return false;                       \
24} while (0)
25
26static bool trans_flw(DisasContext *ctx, arg_flw *a)
27{
28    TCGv t0 = tcg_temp_new();
29    gen_get_gpr(t0, a->rs1);
30    REQUIRE_FPU;
31    REQUIRE_EXT(ctx, RVF);
32    tcg_gen_addi_tl(t0, t0, a->imm);
33
34    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
35    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
36
37    tcg_temp_free(t0);
38    mark_fs_dirty(ctx);
39    return true;
40}
41
42static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
43{
44    TCGv t0 = tcg_temp_new();
45    gen_get_gpr(t0, a->rs1);
46
47    REQUIRE_FPU;
48    REQUIRE_EXT(ctx, RVF);
49    tcg_gen_addi_tl(t0, t0, a->imm);
50
51    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
52
53    tcg_temp_free(t0);
54    return true;
55}
56
57static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
58{
59    REQUIRE_FPU;
60    REQUIRE_EXT(ctx, RVF);
61    gen_set_rm(ctx, a->rm);
62    gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
63                       cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
64    mark_fs_dirty(ctx);
65    return true;
66}
67
68static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a)
69{
70    REQUIRE_FPU;
71    REQUIRE_EXT(ctx, RVF);
72    gen_set_rm(ctx, a->rm);
73    gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
74                       cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
75    mark_fs_dirty(ctx);
76    return true;
77}
78
79static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a)
80{
81    REQUIRE_FPU;
82    REQUIRE_EXT(ctx, RVF);
83    gen_set_rm(ctx, a->rm);
84    gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
85                        cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
86    mark_fs_dirty(ctx);
87    return true;
88}
89
90static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a)
91{
92    REQUIRE_FPU;
93    REQUIRE_EXT(ctx, RVF);
94    gen_set_rm(ctx, a->rm);
95    gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
96                        cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
97    mark_fs_dirty(ctx);
98    return true;
99}
100
101static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a)
102{
103    REQUIRE_FPU;
104    REQUIRE_EXT(ctx, RVF);
105
106    gen_set_rm(ctx, a->rm);
107    gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env,
108                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
109    mark_fs_dirty(ctx);
110    return true;
111}
112
113static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a)
114{
115    REQUIRE_FPU;
116    REQUIRE_EXT(ctx, RVF);
117
118    gen_set_rm(ctx, a->rm);
119    gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env,
120                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
121    mark_fs_dirty(ctx);
122    return true;
123}
124
125static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a)
126{
127    REQUIRE_FPU;
128    REQUIRE_EXT(ctx, RVF);
129
130    gen_set_rm(ctx, a->rm);
131    gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env,
132                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
133    mark_fs_dirty(ctx);
134    return true;
135}
136
137static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a)
138{
139    REQUIRE_FPU;
140    REQUIRE_EXT(ctx, RVF);
141
142    gen_set_rm(ctx, a->rm);
143    gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env,
144                      cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
145    mark_fs_dirty(ctx);
146    return true;
147}
148
149static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a)
150{
151    REQUIRE_FPU;
152    REQUIRE_EXT(ctx, RVF);
153
154    gen_set_rm(ctx, a->rm);
155    gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
156    mark_fs_dirty(ctx);
157    return true;
158}
159
160static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)
161{
162    REQUIRE_FPU;
163    REQUIRE_EXT(ctx, RVF);
164    if (a->rs1 == a->rs2) { /* FMOV */
165        tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
166    } else { /* FSGNJ */
167        tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], cpu_fpr[a->rs1],
168                            0, 31);
169    }
170    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
171    mark_fs_dirty(ctx);
172    return true;
173}
174
175static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
176{
177    REQUIRE_FPU;
178    REQUIRE_EXT(ctx, RVF);
179    if (a->rs1 == a->rs2) { /* FNEG */
180        tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
181    } else {
182        TCGv_i64 t0 = tcg_temp_new_i64();
183        tcg_gen_not_i64(t0, cpu_fpr[a->rs2]);
184        tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 31);
185        tcg_temp_free_i64(t0);
186    }
187    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
188    mark_fs_dirty(ctx);
189    return true;
190}
191
192static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
193{
194    REQUIRE_FPU;
195    REQUIRE_EXT(ctx, RVF);
196    if (a->rs1 == a->rs2) { /* FABS */
197        tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT32_MIN);
198    } else {
199        TCGv_i64 t0 = tcg_temp_new_i64();
200        tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT32_MIN);
201        tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0);
202        tcg_temp_free_i64(t0);
203    }
204    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
205    mark_fs_dirty(ctx);
206    return true;
207}
208
209static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a)
210{
211    REQUIRE_FPU;
212    REQUIRE_EXT(ctx, RVF);
213
214    gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
215                      cpu_fpr[a->rs2]);
216    mark_fs_dirty(ctx);
217    return true;
218}
219
220static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a)
221{
222    REQUIRE_FPU;
223    REQUIRE_EXT(ctx, RVF);
224
225    gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
226                      cpu_fpr[a->rs2]);
227    mark_fs_dirty(ctx);
228    return true;
229}
230
231static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
232{
233    REQUIRE_FPU;
234    REQUIRE_EXT(ctx, RVF);
235
236    TCGv t0 = tcg_temp_new();
237    gen_set_rm(ctx, a->rm);
238    gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
239    gen_set_gpr(a->rd, t0);
240    tcg_temp_free(t0);
241
242    return true;
243}
244
245static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
246{
247    REQUIRE_FPU;
248    REQUIRE_EXT(ctx, RVF);
249
250    TCGv t0 = tcg_temp_new();
251    gen_set_rm(ctx, a->rm);
252    gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
253    gen_set_gpr(a->rd, t0);
254    tcg_temp_free(t0);
255
256    return true;
257}
258
259static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
260{
261    /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */
262    REQUIRE_FPU;
263    REQUIRE_EXT(ctx, RVF);
264
265    TCGv t0 = tcg_temp_new();
266
267#if defined(TARGET_RISCV64)
268    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
269#else
270    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
271#endif
272
273    gen_set_gpr(a->rd, t0);
274    tcg_temp_free(t0);
275
276    return true;
277}
278
279static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
280{
281    REQUIRE_FPU;
282    REQUIRE_EXT(ctx, RVF);
283    TCGv t0 = tcg_temp_new();
284    gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
285    gen_set_gpr(a->rd, t0);
286    tcg_temp_free(t0);
287    return true;
288}
289
290static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
291{
292    REQUIRE_FPU;
293    REQUIRE_EXT(ctx, RVF);
294    TCGv t0 = tcg_temp_new();
295    gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
296    gen_set_gpr(a->rd, t0);
297    tcg_temp_free(t0);
298    return true;
299}
300
301static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
302{
303    REQUIRE_FPU;
304    REQUIRE_EXT(ctx, RVF);
305    TCGv t0 = tcg_temp_new();
306    gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
307    gen_set_gpr(a->rd, t0);
308    tcg_temp_free(t0);
309    return true;
310}
311
312static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
313{
314    REQUIRE_FPU;
315    REQUIRE_EXT(ctx, RVF);
316
317    TCGv t0 = tcg_temp_new();
318
319    gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
320
321    gen_set_gpr(a->rd, t0);
322    tcg_temp_free(t0);
323
324    return true;
325}
326
327static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
328{
329    REQUIRE_FPU;
330    REQUIRE_EXT(ctx, RVF);
331
332    TCGv t0 = tcg_temp_new();
333    gen_get_gpr(t0, a->rs1);
334
335    gen_set_rm(ctx, a->rm);
336    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
337
338    mark_fs_dirty(ctx);
339    tcg_temp_free(t0);
340
341    return true;
342}
343
344static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
345{
346    REQUIRE_FPU;
347    REQUIRE_EXT(ctx, RVF);
348
349    TCGv t0 = tcg_temp_new();
350    gen_get_gpr(t0, a->rs1);
351
352    gen_set_rm(ctx, a->rm);
353    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
354
355    mark_fs_dirty(ctx);
356    tcg_temp_free(t0);
357
358    return true;
359}
360
361static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
362{
363    /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */
364    REQUIRE_FPU;
365    REQUIRE_EXT(ctx, RVF);
366
367    TCGv t0 = tcg_temp_new();
368    gen_get_gpr(t0, a->rs1);
369
370#if defined(TARGET_RISCV64)
371    tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
372#else
373    tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
374#endif
375    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
376
377    mark_fs_dirty(ctx);
378    tcg_temp_free(t0);
379
380    return true;
381}
382
383#ifdef TARGET_RISCV64
384static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
385{
386    REQUIRE_FPU;
387    REQUIRE_EXT(ctx, RVF);
388
389    TCGv t0 = tcg_temp_new();
390    gen_set_rm(ctx, a->rm);
391    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
392    gen_set_gpr(a->rd, t0);
393    tcg_temp_free(t0);
394    return true;
395}
396
397static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
398{
399    REQUIRE_FPU;
400    REQUIRE_EXT(ctx, RVF);
401
402    TCGv t0 = tcg_temp_new();
403    gen_set_rm(ctx, a->rm);
404    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
405    gen_set_gpr(a->rd, t0);
406    tcg_temp_free(t0);
407    return true;
408}
409
410static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
411{
412    REQUIRE_FPU;
413    REQUIRE_EXT(ctx, RVF);
414
415    TCGv t0 = tcg_temp_new();
416    gen_get_gpr(t0, a->rs1);
417
418    gen_set_rm(ctx, a->rm);
419    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
420
421    mark_fs_dirty(ctx);
422    tcg_temp_free(t0);
423    return true;
424}
425
426static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
427{
428    REQUIRE_FPU;
429    REQUIRE_EXT(ctx, RVF);
430
431    TCGv t0 = tcg_temp_new();
432    gen_get_gpr(t0, a->rs1);
433
434    gen_set_rm(ctx, a->rm);
435    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
436
437    mark_fs_dirty(ctx);
438    tcg_temp_free(t0);
439    return true;
440}
441#endif
442