1/*
2 * RISC-V translation routines for the Zb[abcs] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBB(ctx) do {                    \
28    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
29        return false;                            \
30    }                                            \
31} while (0)
32
33#define REQUIRE_ZBC(ctx) do {                    \
34    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
35        return false;                            \
36    }                                            \
37} while (0)
38
39#define REQUIRE_ZBS(ctx) do {                    \
40    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
41        return false;                            \
42    }                                            \
43} while (0)
44
45static void gen_clz(TCGv ret, TCGv arg1)
46{
47    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
48}
49
50static void gen_clzw(TCGv ret, TCGv arg1)
51{
52    TCGv t = tcg_temp_new();
53    tcg_gen_shli_tl(t, arg1, 32);
54    tcg_gen_clzi_tl(ret, t, 32);
55    tcg_temp_free(t);
56}
57
58static bool trans_clz(DisasContext *ctx, arg_clz *a)
59{
60    REQUIRE_ZBB(ctx);
61    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
62}
63
64static void gen_ctz(TCGv ret, TCGv arg1)
65{
66    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
67}
68
69static void gen_ctzw(TCGv ret, TCGv arg1)
70{
71    tcg_gen_ctzi_tl(ret, arg1, 32);
72}
73
74static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
75{
76    REQUIRE_ZBB(ctx);
77    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
78}
79
80static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
81{
82    REQUIRE_ZBB(ctx);
83    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
84}
85
86static bool trans_andn(DisasContext *ctx, arg_andn *a)
87{
88    REQUIRE_ZBB(ctx);
89    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
90}
91
92static bool trans_orn(DisasContext *ctx, arg_orn *a)
93{
94    REQUIRE_ZBB(ctx);
95    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
96}
97
98static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
99{
100    REQUIRE_ZBB(ctx);
101    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
102}
103
104static bool trans_min(DisasContext *ctx, arg_min *a)
105{
106    REQUIRE_ZBB(ctx);
107    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
108}
109
110static bool trans_max(DisasContext *ctx, arg_max *a)
111{
112    REQUIRE_ZBB(ctx);
113    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
114}
115
116static bool trans_minu(DisasContext *ctx, arg_minu *a)
117{
118    REQUIRE_ZBB(ctx);
119    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
120}
121
122static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
123{
124    REQUIRE_ZBB(ctx);
125    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
126}
127
128static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
129{
130    REQUIRE_ZBB(ctx);
131    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
132}
133
134static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
135{
136    REQUIRE_ZBB(ctx);
137    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
138}
139
140static void gen_sbop_mask(TCGv ret, TCGv shamt)
141{
142    tcg_gen_movi_tl(ret, 1);
143    tcg_gen_shl_tl(ret, ret, shamt);
144}
145
146static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
147{
148    TCGv t = tcg_temp_new();
149
150    gen_sbop_mask(t, shamt);
151    tcg_gen_or_tl(ret, arg1, t);
152
153    tcg_temp_free(t);
154}
155
156static bool trans_bset(DisasContext *ctx, arg_bset *a)
157{
158    REQUIRE_ZBS(ctx);
159    return gen_shift(ctx, a, EXT_NONE, gen_bset);
160}
161
162static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
163{
164    REQUIRE_ZBS(ctx);
165    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
166}
167
168static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
169{
170    TCGv t = tcg_temp_new();
171
172    gen_sbop_mask(t, shamt);
173    tcg_gen_andc_tl(ret, arg1, t);
174
175    tcg_temp_free(t);
176}
177
178static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
179{
180    REQUIRE_ZBS(ctx);
181    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
182}
183
184static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
185{
186    REQUIRE_ZBS(ctx);
187    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
188}
189
190static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
191{
192    TCGv t = tcg_temp_new();
193
194    gen_sbop_mask(t, shamt);
195    tcg_gen_xor_tl(ret, arg1, t);
196
197    tcg_temp_free(t);
198}
199
200static bool trans_binv(DisasContext *ctx, arg_binv *a)
201{
202    REQUIRE_ZBS(ctx);
203    return gen_shift(ctx, a, EXT_NONE, gen_binv);
204}
205
206static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
207{
208    REQUIRE_ZBS(ctx);
209    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
210}
211
212static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
213{
214    tcg_gen_shr_tl(ret, arg1, shamt);
215    tcg_gen_andi_tl(ret, ret, 1);
216}
217
218static bool trans_bext(DisasContext *ctx, arg_bext *a)
219{
220    REQUIRE_ZBS(ctx);
221    return gen_shift(ctx, a, EXT_NONE, gen_bext);
222}
223
224static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
225{
226    REQUIRE_ZBS(ctx);
227    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
228}
229
230static bool trans_ror(DisasContext *ctx, arg_ror *a)
231{
232    REQUIRE_ZBB(ctx);
233    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
234}
235
236static bool trans_rori(DisasContext *ctx, arg_rori *a)
237{
238    REQUIRE_ZBB(ctx);
239    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
240}
241
242static bool trans_rol(DisasContext *ctx, arg_rol *a)
243{
244    REQUIRE_ZBB(ctx);
245    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
246}
247
248static void gen_rev8_32(TCGv ret, TCGv src1)
249{
250    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
251}
252
253static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
254{
255    REQUIRE_32BIT(ctx);
256    REQUIRE_ZBB(ctx);
257    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
258}
259
260static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
261{
262    REQUIRE_64BIT(ctx);
263    REQUIRE_ZBB(ctx);
264    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
265}
266
267static void gen_orc_b(TCGv ret, TCGv source1)
268{
269    TCGv  tmp = tcg_temp_new();
270    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
271
272    /* Set msb in each byte if the byte was non-zero. */
273    tcg_gen_and_tl(tmp, source1, low7);
274    tcg_gen_add_tl(tmp, tmp, low7);
275    tcg_gen_or_tl(tmp, tmp, source1);
276
277    /* Extract the msb to the lsb in each byte */
278    tcg_gen_andc_tl(tmp, tmp, low7);
279    tcg_gen_shri_tl(tmp, tmp, 7);
280
281    /* Replicate the lsb of each byte across the byte. */
282    tcg_gen_muli_tl(ret, tmp, 0xff);
283
284    tcg_temp_free(tmp);
285}
286
287static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
288{
289    REQUIRE_ZBB(ctx);
290    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
291}
292
293#define GEN_SHADD(SHAMT)                                       \
294static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
295{                                                              \
296    TCGv t = tcg_temp_new();                                   \
297                                                               \
298    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
299    tcg_gen_add_tl(ret, t, arg2);                              \
300                                                               \
301    tcg_temp_free(t);                                          \
302}
303
304GEN_SHADD(1)
305GEN_SHADD(2)
306GEN_SHADD(3)
307
308#define GEN_TRANS_SHADD(SHAMT)                                             \
309static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
310{                                                                          \
311    REQUIRE_ZBA(ctx);                                                      \
312    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
313}
314
315GEN_TRANS_SHADD(1)
316GEN_TRANS_SHADD(2)
317GEN_TRANS_SHADD(3)
318
319static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
320{
321    REQUIRE_32BIT(ctx);
322    REQUIRE_ZBB(ctx);
323    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
324}
325
326static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
327{
328    REQUIRE_64BIT(ctx);
329    REQUIRE_ZBB(ctx);
330    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
331}
332
333static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
334{
335    REQUIRE_64BIT(ctx);
336    REQUIRE_ZBB(ctx);
337    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
338}
339
340static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
341{
342    REQUIRE_64BIT(ctx);
343    REQUIRE_ZBB(ctx);
344    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
345}
346
347static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
348{
349    REQUIRE_64BIT(ctx);
350    REQUIRE_ZBB(ctx);
351    ctx->ol = MXL_RV32;
352    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
353}
354
355static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
356{
357    TCGv_i32 t1 = tcg_temp_new_i32();
358    TCGv_i32 t2 = tcg_temp_new_i32();
359
360    /* truncate to 32-bits */
361    tcg_gen_trunc_tl_i32(t1, arg1);
362    tcg_gen_trunc_tl_i32(t2, arg2);
363
364    tcg_gen_rotr_i32(t1, t1, t2);
365
366    /* sign-extend 64-bits */
367    tcg_gen_ext_i32_tl(ret, t1);
368
369    tcg_temp_free_i32(t1);
370    tcg_temp_free_i32(t2);
371}
372
373static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
374{
375    REQUIRE_64BIT(ctx);
376    REQUIRE_ZBB(ctx);
377    ctx->ol = MXL_RV32;
378    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
379}
380
381static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
382{
383    REQUIRE_64BIT(ctx);
384    REQUIRE_ZBB(ctx);
385    ctx->ol = MXL_RV32;
386    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
387}
388
389static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
390{
391    TCGv_i32 t1 = tcg_temp_new_i32();
392    TCGv_i32 t2 = tcg_temp_new_i32();
393
394    /* truncate to 32-bits */
395    tcg_gen_trunc_tl_i32(t1, arg1);
396    tcg_gen_trunc_tl_i32(t2, arg2);
397
398    tcg_gen_rotl_i32(t1, t1, t2);
399
400    /* sign-extend 64-bits */
401    tcg_gen_ext_i32_tl(ret, t1);
402
403    tcg_temp_free_i32(t1);
404    tcg_temp_free_i32(t2);
405}
406
407static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
408{
409    REQUIRE_64BIT(ctx);
410    REQUIRE_ZBB(ctx);
411    ctx->ol = MXL_RV32;
412    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
413}
414
415#define GEN_SHADD_UW(SHAMT)                                       \
416static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
417{                                                                 \
418    TCGv t = tcg_temp_new();                                      \
419                                                                  \
420    tcg_gen_ext32u_tl(t, arg1);                                   \
421                                                                  \
422    tcg_gen_shli_tl(t, t, SHAMT);                                 \
423    tcg_gen_add_tl(ret, t, arg2);                                 \
424                                                                  \
425    tcg_temp_free(t);                                             \
426}
427
428GEN_SHADD_UW(1)
429GEN_SHADD_UW(2)
430GEN_SHADD_UW(3)
431
432#define GEN_TRANS_SHADD_UW(SHAMT)                             \
433static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
434                                    arg_sh##SHAMT##add_uw *a) \
435{                                                             \
436    REQUIRE_64BIT(ctx);                                       \
437    REQUIRE_ZBA(ctx);                                         \
438    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
439}
440
441GEN_TRANS_SHADD_UW(1)
442GEN_TRANS_SHADD_UW(2)
443GEN_TRANS_SHADD_UW(3)
444
445static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
446{
447    TCGv t = tcg_temp_new();
448    tcg_gen_ext32u_tl(t, arg1);
449    tcg_gen_add_tl(ret, t, arg2);
450    tcg_temp_free(t);
451}
452
453static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
454{
455    REQUIRE_64BIT(ctx);
456    REQUIRE_ZBA(ctx);
457    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
458}
459
460static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
461{
462    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
463}
464
465static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
466{
467    REQUIRE_64BIT(ctx);
468    REQUIRE_ZBA(ctx);
469    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
470}
471
472static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
473{
474    REQUIRE_ZBC(ctx);
475    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
476}
477
478static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
479{
480     gen_helper_clmulr(dst, src1, src2);
481     tcg_gen_shri_tl(dst, dst, 1);
482}
483
484static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
485{
486    REQUIRE_ZBC(ctx);
487    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
488}
489
490static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
491{
492    REQUIRE_ZBC(ctx);
493    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
494}
495