1/*
2 * RISC-V translation routines for the Zb[acs] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBC(ctx) do {                    \
28    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
29        return false;                            \
30    }                                            \
31} while (0)
32
33#define REQUIRE_ZBS(ctx) do {                    \
34    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
35        return false;                            \
36    }                                            \
37} while (0)
38
39static void gen_clz(TCGv ret, TCGv arg1)
40{
41    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
42}
43static bool trans_clz(DisasContext *ctx, arg_clz *a)
44{
45    REQUIRE_EXT(ctx, RVB);
46    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
47}
48
49static void gen_ctz(TCGv ret, TCGv arg1)
50{
51    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
52}
53
54static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
55{
56    REQUIRE_EXT(ctx, RVB);
57    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
58}
59
60static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
61{
62    REQUIRE_EXT(ctx, RVB);
63    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
64}
65
66static bool trans_andn(DisasContext *ctx, arg_andn *a)
67{
68    REQUIRE_EXT(ctx, RVB);
69    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
70}
71
72static bool trans_orn(DisasContext *ctx, arg_orn *a)
73{
74    REQUIRE_EXT(ctx, RVB);
75    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
76}
77
78static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
79{
80    REQUIRE_EXT(ctx, RVB);
81    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
82}
83
84static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
85{
86    tcg_gen_deposit_tl(ret, arg1, arg2,
87                       TARGET_LONG_BITS / 2,
88                       TARGET_LONG_BITS / 2);
89}
90
91static bool trans_pack(DisasContext *ctx, arg_pack *a)
92{
93    REQUIRE_EXT(ctx, RVB);
94    return gen_arith(ctx, a, EXT_NONE, gen_pack);
95}
96
97static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
98{
99    TCGv t = tcg_temp_new();
100    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
101    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
102    tcg_temp_free(t);
103}
104
105static bool trans_packu(DisasContext *ctx, arg_packu *a)
106{
107    REQUIRE_EXT(ctx, RVB);
108    return gen_arith(ctx, a, EXT_NONE, gen_packu);
109}
110
111static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
112{
113    TCGv t = tcg_temp_new();
114    tcg_gen_ext8u_tl(t, arg2);
115    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
116    tcg_temp_free(t);
117}
118
119static bool trans_packh(DisasContext *ctx, arg_packh *a)
120{
121    REQUIRE_EXT(ctx, RVB);
122    return gen_arith(ctx, a, EXT_NONE, gen_packh);
123}
124
125static bool trans_min(DisasContext *ctx, arg_min *a)
126{
127    REQUIRE_EXT(ctx, RVB);
128    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
129}
130
131static bool trans_max(DisasContext *ctx, arg_max *a)
132{
133    REQUIRE_EXT(ctx, RVB);
134    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
135}
136
137static bool trans_minu(DisasContext *ctx, arg_minu *a)
138{
139    REQUIRE_EXT(ctx, RVB);
140    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
141}
142
143static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
144{
145    REQUIRE_EXT(ctx, RVB);
146    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
147}
148
149static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
150{
151    REQUIRE_EXT(ctx, RVB);
152    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
153}
154
155static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
156{
157    REQUIRE_EXT(ctx, RVB);
158    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
159}
160
161static void gen_sbop_mask(TCGv ret, TCGv shamt)
162{
163    tcg_gen_movi_tl(ret, 1);
164    tcg_gen_shl_tl(ret, ret, shamt);
165}
166
167static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
168{
169    TCGv t = tcg_temp_new();
170
171    gen_sbop_mask(t, shamt);
172    tcg_gen_or_tl(ret, arg1, t);
173
174    tcg_temp_free(t);
175}
176
177static bool trans_bset(DisasContext *ctx, arg_bset *a)
178{
179    REQUIRE_ZBS(ctx);
180    return gen_shift(ctx, a, EXT_NONE, gen_bset);
181}
182
183static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
184{
185    REQUIRE_ZBS(ctx);
186    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
187}
188
189static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
190{
191    TCGv t = tcg_temp_new();
192
193    gen_sbop_mask(t, shamt);
194    tcg_gen_andc_tl(ret, arg1, t);
195
196    tcg_temp_free(t);
197}
198
199static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
200{
201    REQUIRE_ZBS(ctx);
202    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
203}
204
205static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
206{
207    REQUIRE_ZBS(ctx);
208    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
209}
210
211static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
212{
213    TCGv t = tcg_temp_new();
214
215    gen_sbop_mask(t, shamt);
216    tcg_gen_xor_tl(ret, arg1, t);
217
218    tcg_temp_free(t);
219}
220
221static bool trans_binv(DisasContext *ctx, arg_binv *a)
222{
223    REQUIRE_ZBS(ctx);
224    return gen_shift(ctx, a, EXT_NONE, gen_binv);
225}
226
227static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
228{
229    REQUIRE_ZBS(ctx);
230    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
231}
232
233static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
234{
235    tcg_gen_shr_tl(ret, arg1, shamt);
236    tcg_gen_andi_tl(ret, ret, 1);
237}
238
239static bool trans_bext(DisasContext *ctx, arg_bext *a)
240{
241    REQUIRE_ZBS(ctx);
242    return gen_shift(ctx, a, EXT_NONE, gen_bext);
243}
244
245static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
246{
247    REQUIRE_ZBS(ctx);
248    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
249}
250
251static bool trans_ror(DisasContext *ctx, arg_ror *a)
252{
253    REQUIRE_EXT(ctx, RVB);
254    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
255}
256
257static bool trans_rori(DisasContext *ctx, arg_rori *a)
258{
259    REQUIRE_EXT(ctx, RVB);
260    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
261}
262
263static bool trans_rol(DisasContext *ctx, arg_rol *a)
264{
265    REQUIRE_EXT(ctx, RVB);
266    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
267}
268
269static bool trans_grev(DisasContext *ctx, arg_grev *a)
270{
271    REQUIRE_EXT(ctx, RVB);
272    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
273}
274
275static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
276{
277    if (shamt == TARGET_LONG_BITS - 8) {
278        /* rev8, byte swaps */
279        tcg_gen_bswap_tl(dest, src);
280    } else {
281        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
282    }
283}
284
285static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
286{
287    REQUIRE_EXT(ctx, RVB);
288    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
289}
290
291static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
292{
293    REQUIRE_EXT(ctx, RVB);
294    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
295}
296
297static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
298{
299    REQUIRE_EXT(ctx, RVB);
300    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
301}
302
303#define GEN_SHADD(SHAMT)                                       \
304static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
305{                                                              \
306    TCGv t = tcg_temp_new();                                   \
307                                                               \
308    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
309    tcg_gen_add_tl(ret, t, arg2);                              \
310                                                               \
311    tcg_temp_free(t);                                          \
312}
313
314GEN_SHADD(1)
315GEN_SHADD(2)
316GEN_SHADD(3)
317
318#define GEN_TRANS_SHADD(SHAMT)                                             \
319static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
320{                                                                          \
321    REQUIRE_ZBA(ctx);                                                      \
322    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
323}
324
325GEN_TRANS_SHADD(1)
326GEN_TRANS_SHADD(2)
327GEN_TRANS_SHADD(3)
328
329static void gen_clzw(TCGv ret, TCGv arg1)
330{
331    TCGv t = tcg_temp_new();
332    tcg_gen_shli_tl(t, arg1, 32);
333    tcg_gen_clzi_tl(ret, t, 32);
334    tcg_temp_free(t);
335}
336
337static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
338{
339    REQUIRE_64BIT(ctx);
340    REQUIRE_EXT(ctx, RVB);
341    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
342}
343
344static void gen_ctzw(TCGv ret, TCGv arg1)
345{
346    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
347    tcg_gen_ctzi_tl(ret, ret, 64);
348}
349
350static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
351{
352    REQUIRE_64BIT(ctx);
353    REQUIRE_EXT(ctx, RVB);
354    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
355}
356
357static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
358{
359    REQUIRE_64BIT(ctx);
360    REQUIRE_EXT(ctx, RVB);
361    ctx->w = true;
362    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
363}
364
365static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
366{
367    TCGv t = tcg_temp_new();
368    tcg_gen_ext16s_tl(t, arg2);
369    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
370    tcg_temp_free(t);
371}
372
373static bool trans_packw(DisasContext *ctx, arg_packw *a)
374{
375    REQUIRE_64BIT(ctx);
376    REQUIRE_EXT(ctx, RVB);
377    return gen_arith(ctx, a, EXT_NONE, gen_packw);
378}
379
380static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
381{
382    TCGv t = tcg_temp_new();
383    tcg_gen_shri_tl(t, arg1, 16);
384    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
385    tcg_gen_ext32s_tl(ret, ret);
386    tcg_temp_free(t);
387}
388
389static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
390{
391    REQUIRE_64BIT(ctx);
392    REQUIRE_EXT(ctx, RVB);
393    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
394}
395
396static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
397{
398    TCGv_i32 t1 = tcg_temp_new_i32();
399    TCGv_i32 t2 = tcg_temp_new_i32();
400
401    /* truncate to 32-bits */
402    tcg_gen_trunc_tl_i32(t1, arg1);
403    tcg_gen_trunc_tl_i32(t2, arg2);
404
405    tcg_gen_rotr_i32(t1, t1, t2);
406
407    /* sign-extend 64-bits */
408    tcg_gen_ext_i32_tl(ret, t1);
409
410    tcg_temp_free_i32(t1);
411    tcg_temp_free_i32(t2);
412}
413
414static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
415{
416    REQUIRE_64BIT(ctx);
417    REQUIRE_EXT(ctx, RVB);
418    ctx->w = true;
419    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
420}
421
422static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
423{
424    REQUIRE_64BIT(ctx);
425    REQUIRE_EXT(ctx, RVB);
426    ctx->w = true;
427    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
428}
429
430static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
431{
432    TCGv_i32 t1 = tcg_temp_new_i32();
433    TCGv_i32 t2 = tcg_temp_new_i32();
434
435    /* truncate to 32-bits */
436    tcg_gen_trunc_tl_i32(t1, arg1);
437    tcg_gen_trunc_tl_i32(t2, arg2);
438
439    tcg_gen_rotl_i32(t1, t1, t2);
440
441    /* sign-extend 64-bits */
442    tcg_gen_ext_i32_tl(ret, t1);
443
444    tcg_temp_free_i32(t1);
445    tcg_temp_free_i32(t2);
446}
447
448static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
449{
450    REQUIRE_64BIT(ctx);
451    REQUIRE_EXT(ctx, RVB);
452    ctx->w = true;
453    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
454}
455
456static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
457{
458    REQUIRE_64BIT(ctx);
459    REQUIRE_EXT(ctx, RVB);
460    ctx->w = true;
461    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
462}
463
464static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
465{
466    REQUIRE_64BIT(ctx);
467    REQUIRE_EXT(ctx, RVB);
468    ctx->w = true;
469    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
470}
471
472static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
473{
474    REQUIRE_64BIT(ctx);
475    REQUIRE_EXT(ctx, RVB);
476    ctx->w = true;
477    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
478}
479
480static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
481{
482    REQUIRE_64BIT(ctx);
483    REQUIRE_EXT(ctx, RVB);
484    ctx->w = true;
485    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
486}
487
488#define GEN_SHADD_UW(SHAMT)                                       \
489static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
490{                                                                 \
491    TCGv t = tcg_temp_new();                                      \
492                                                                  \
493    tcg_gen_ext32u_tl(t, arg1);                                   \
494                                                                  \
495    tcg_gen_shli_tl(t, t, SHAMT);                                 \
496    tcg_gen_add_tl(ret, t, arg2);                                 \
497                                                                  \
498    tcg_temp_free(t);                                             \
499}
500
501GEN_SHADD_UW(1)
502GEN_SHADD_UW(2)
503GEN_SHADD_UW(3)
504
505#define GEN_TRANS_SHADD_UW(SHAMT)                             \
506static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
507                                    arg_sh##SHAMT##add_uw *a) \
508{                                                             \
509    REQUIRE_64BIT(ctx);                                       \
510    REQUIRE_ZBA(ctx);                                         \
511    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
512}
513
514GEN_TRANS_SHADD_UW(1)
515GEN_TRANS_SHADD_UW(2)
516GEN_TRANS_SHADD_UW(3)
517
518static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
519{
520    TCGv t = tcg_temp_new();
521    tcg_gen_ext32u_tl(t, arg1);
522    tcg_gen_add_tl(ret, t, arg2);
523    tcg_temp_free(t);
524}
525
526static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
527{
528    REQUIRE_64BIT(ctx);
529    REQUIRE_ZBA(ctx);
530    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
531}
532
533static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
534{
535    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
536}
537
538static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
539{
540    REQUIRE_64BIT(ctx);
541    REQUIRE_ZBA(ctx);
542    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
543}
544
545static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
546{
547    REQUIRE_ZBC(ctx);
548    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
549}
550
551static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
552{
553     gen_helper_clmulr(dst, src1, src2);
554     tcg_gen_shri_tl(dst, dst, 1);
555}
556
557static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
558{
559    REQUIRE_ZBC(ctx);
560    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
561}
562
563static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
564{
565    REQUIRE_ZBC(ctx);
566    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
567}
568