1/*
2 * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBS(ctx) do {                    \
28    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
29        return false;                            \
30    }                                            \
31} while (0)
32
33static void gen_clz(TCGv ret, TCGv arg1)
34{
35    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
36}
37static bool trans_clz(DisasContext *ctx, arg_clz *a)
38{
39    REQUIRE_EXT(ctx, RVB);
40    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
41}
42
43static void gen_ctz(TCGv ret, TCGv arg1)
44{
45    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
46}
47
48static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
49{
50    REQUIRE_EXT(ctx, RVB);
51    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
52}
53
54static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
55{
56    REQUIRE_EXT(ctx, RVB);
57    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
58}
59
60static bool trans_andn(DisasContext *ctx, arg_andn *a)
61{
62    REQUIRE_EXT(ctx, RVB);
63    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
64}
65
66static bool trans_orn(DisasContext *ctx, arg_orn *a)
67{
68    REQUIRE_EXT(ctx, RVB);
69    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
70}
71
72static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
73{
74    REQUIRE_EXT(ctx, RVB);
75    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
76}
77
78static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
79{
80    tcg_gen_deposit_tl(ret, arg1, arg2,
81                       TARGET_LONG_BITS / 2,
82                       TARGET_LONG_BITS / 2);
83}
84
85static bool trans_pack(DisasContext *ctx, arg_pack *a)
86{
87    REQUIRE_EXT(ctx, RVB);
88    return gen_arith(ctx, a, EXT_NONE, gen_pack);
89}
90
91static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
92{
93    TCGv t = tcg_temp_new();
94    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
95    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
96    tcg_temp_free(t);
97}
98
99static bool trans_packu(DisasContext *ctx, arg_packu *a)
100{
101    REQUIRE_EXT(ctx, RVB);
102    return gen_arith(ctx, a, EXT_NONE, gen_packu);
103}
104
105static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
106{
107    TCGv t = tcg_temp_new();
108    tcg_gen_ext8u_tl(t, arg2);
109    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
110    tcg_temp_free(t);
111}
112
113static bool trans_packh(DisasContext *ctx, arg_packh *a)
114{
115    REQUIRE_EXT(ctx, RVB);
116    return gen_arith(ctx, a, EXT_NONE, gen_packh);
117}
118
119static bool trans_min(DisasContext *ctx, arg_min *a)
120{
121    REQUIRE_EXT(ctx, RVB);
122    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
123}
124
125static bool trans_max(DisasContext *ctx, arg_max *a)
126{
127    REQUIRE_EXT(ctx, RVB);
128    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
129}
130
131static bool trans_minu(DisasContext *ctx, arg_minu *a)
132{
133    REQUIRE_EXT(ctx, RVB);
134    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
135}
136
137static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
138{
139    REQUIRE_EXT(ctx, RVB);
140    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
141}
142
143static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
144{
145    REQUIRE_EXT(ctx, RVB);
146    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
147}
148
149static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
150{
151    REQUIRE_EXT(ctx, RVB);
152    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
153}
154
155static void gen_sbop_mask(TCGv ret, TCGv shamt)
156{
157    tcg_gen_movi_tl(ret, 1);
158    tcg_gen_shl_tl(ret, ret, shamt);
159}
160
161static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
162{
163    TCGv t = tcg_temp_new();
164
165    gen_sbop_mask(t, shamt);
166    tcg_gen_or_tl(ret, arg1, t);
167
168    tcg_temp_free(t);
169}
170
171static bool trans_bset(DisasContext *ctx, arg_bset *a)
172{
173    REQUIRE_ZBS(ctx);
174    return gen_shift(ctx, a, EXT_NONE, gen_bset);
175}
176
177static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
178{
179    REQUIRE_ZBS(ctx);
180    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
181}
182
183static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
184{
185    TCGv t = tcg_temp_new();
186
187    gen_sbop_mask(t, shamt);
188    tcg_gen_andc_tl(ret, arg1, t);
189
190    tcg_temp_free(t);
191}
192
193static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
194{
195    REQUIRE_ZBS(ctx);
196    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
197}
198
199static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
200{
201    REQUIRE_ZBS(ctx);
202    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
203}
204
205static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
206{
207    TCGv t = tcg_temp_new();
208
209    gen_sbop_mask(t, shamt);
210    tcg_gen_xor_tl(ret, arg1, t);
211
212    tcg_temp_free(t);
213}
214
215static bool trans_binv(DisasContext *ctx, arg_binv *a)
216{
217    REQUIRE_ZBS(ctx);
218    return gen_shift(ctx, a, EXT_NONE, gen_binv);
219}
220
221static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
222{
223    REQUIRE_ZBS(ctx);
224    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
225}
226
227static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
228{
229    tcg_gen_shr_tl(ret, arg1, shamt);
230    tcg_gen_andi_tl(ret, ret, 1);
231}
232
233static bool trans_bext(DisasContext *ctx, arg_bext *a)
234{
235    REQUIRE_ZBS(ctx);
236    return gen_shift(ctx, a, EXT_NONE, gen_bext);
237}
238
239static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
240{
241    REQUIRE_ZBS(ctx);
242    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
243}
244
245static bool trans_ror(DisasContext *ctx, arg_ror *a)
246{
247    REQUIRE_EXT(ctx, RVB);
248    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
249}
250
251static bool trans_rori(DisasContext *ctx, arg_rori *a)
252{
253    REQUIRE_EXT(ctx, RVB);
254    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
255}
256
257static bool trans_rol(DisasContext *ctx, arg_rol *a)
258{
259    REQUIRE_EXT(ctx, RVB);
260    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
261}
262
263static bool trans_grev(DisasContext *ctx, arg_grev *a)
264{
265    REQUIRE_EXT(ctx, RVB);
266    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
267}
268
269static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
270{
271    if (shamt == TARGET_LONG_BITS - 8) {
272        /* rev8, byte swaps */
273        tcg_gen_bswap_tl(dest, src);
274    } else {
275        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
276    }
277}
278
279static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
280{
281    REQUIRE_EXT(ctx, RVB);
282    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
283}
284
285static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
286{
287    REQUIRE_EXT(ctx, RVB);
288    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
289}
290
291static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
292{
293    REQUIRE_EXT(ctx, RVB);
294    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
295}
296
297#define GEN_SHADD(SHAMT)                                       \
298static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
299{                                                              \
300    TCGv t = tcg_temp_new();                                   \
301                                                               \
302    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
303    tcg_gen_add_tl(ret, t, arg2);                              \
304                                                               \
305    tcg_temp_free(t);                                          \
306}
307
308GEN_SHADD(1)
309GEN_SHADD(2)
310GEN_SHADD(3)
311
312#define GEN_TRANS_SHADD(SHAMT)                                             \
313static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
314{                                                                          \
315    REQUIRE_ZBA(ctx);                                                      \
316    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
317}
318
319GEN_TRANS_SHADD(1)
320GEN_TRANS_SHADD(2)
321GEN_TRANS_SHADD(3)
322
323static void gen_clzw(TCGv ret, TCGv arg1)
324{
325    TCGv t = tcg_temp_new();
326    tcg_gen_shli_tl(t, arg1, 32);
327    tcg_gen_clzi_tl(ret, t, 32);
328    tcg_temp_free(t);
329}
330
331static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
332{
333    REQUIRE_64BIT(ctx);
334    REQUIRE_EXT(ctx, RVB);
335    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
336}
337
338static void gen_ctzw(TCGv ret, TCGv arg1)
339{
340    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
341    tcg_gen_ctzi_tl(ret, ret, 64);
342}
343
344static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
345{
346    REQUIRE_64BIT(ctx);
347    REQUIRE_EXT(ctx, RVB);
348    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
349}
350
351static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
352{
353    REQUIRE_64BIT(ctx);
354    REQUIRE_EXT(ctx, RVB);
355    ctx->w = true;
356    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
357}
358
359static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
360{
361    TCGv t = tcg_temp_new();
362    tcg_gen_ext16s_tl(t, arg2);
363    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
364    tcg_temp_free(t);
365}
366
367static bool trans_packw(DisasContext *ctx, arg_packw *a)
368{
369    REQUIRE_64BIT(ctx);
370    REQUIRE_EXT(ctx, RVB);
371    return gen_arith(ctx, a, EXT_NONE, gen_packw);
372}
373
374static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
375{
376    TCGv t = tcg_temp_new();
377    tcg_gen_shri_tl(t, arg1, 16);
378    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
379    tcg_gen_ext32s_tl(ret, ret);
380    tcg_temp_free(t);
381}
382
383static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
384{
385    REQUIRE_64BIT(ctx);
386    REQUIRE_EXT(ctx, RVB);
387    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
388}
389
390static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
391{
392    TCGv_i32 t1 = tcg_temp_new_i32();
393    TCGv_i32 t2 = tcg_temp_new_i32();
394
395    /* truncate to 32-bits */
396    tcg_gen_trunc_tl_i32(t1, arg1);
397    tcg_gen_trunc_tl_i32(t2, arg2);
398
399    tcg_gen_rotr_i32(t1, t1, t2);
400
401    /* sign-extend 64-bits */
402    tcg_gen_ext_i32_tl(ret, t1);
403
404    tcg_temp_free_i32(t1);
405    tcg_temp_free_i32(t2);
406}
407
408static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
409{
410    REQUIRE_64BIT(ctx);
411    REQUIRE_EXT(ctx, RVB);
412    ctx->w = true;
413    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
414}
415
416static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
417{
418    REQUIRE_64BIT(ctx);
419    REQUIRE_EXT(ctx, RVB);
420    ctx->w = true;
421    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
422}
423
424static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
425{
426    TCGv_i32 t1 = tcg_temp_new_i32();
427    TCGv_i32 t2 = tcg_temp_new_i32();
428
429    /* truncate to 32-bits */
430    tcg_gen_trunc_tl_i32(t1, arg1);
431    tcg_gen_trunc_tl_i32(t2, arg2);
432
433    tcg_gen_rotl_i32(t1, t1, t2);
434
435    /* sign-extend 64-bits */
436    tcg_gen_ext_i32_tl(ret, t1);
437
438    tcg_temp_free_i32(t1);
439    tcg_temp_free_i32(t2);
440}
441
442static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
443{
444    REQUIRE_64BIT(ctx);
445    REQUIRE_EXT(ctx, RVB);
446    ctx->w = true;
447    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
448}
449
450static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
451{
452    REQUIRE_64BIT(ctx);
453    REQUIRE_EXT(ctx, RVB);
454    ctx->w = true;
455    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
456}
457
458static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
459{
460    REQUIRE_64BIT(ctx);
461    REQUIRE_EXT(ctx, RVB);
462    ctx->w = true;
463    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
464}
465
466static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
467{
468    REQUIRE_64BIT(ctx);
469    REQUIRE_EXT(ctx, RVB);
470    ctx->w = true;
471    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
472}
473
474static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
475{
476    REQUIRE_64BIT(ctx);
477    REQUIRE_EXT(ctx, RVB);
478    ctx->w = true;
479    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
480}
481
482#define GEN_SHADD_UW(SHAMT)                                       \
483static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
484{                                                                 \
485    TCGv t = tcg_temp_new();                                      \
486                                                                  \
487    tcg_gen_ext32u_tl(t, arg1);                                   \
488                                                                  \
489    tcg_gen_shli_tl(t, t, SHAMT);                                 \
490    tcg_gen_add_tl(ret, t, arg2);                                 \
491                                                                  \
492    tcg_temp_free(t);                                             \
493}
494
495GEN_SHADD_UW(1)
496GEN_SHADD_UW(2)
497GEN_SHADD_UW(3)
498
499#define GEN_TRANS_SHADD_UW(SHAMT)                             \
500static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
501                                    arg_sh##SHAMT##add_uw *a) \
502{                                                             \
503    REQUIRE_64BIT(ctx);                                       \
504    REQUIRE_ZBA(ctx);                                         \
505    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
506}
507
508GEN_TRANS_SHADD_UW(1)
509GEN_TRANS_SHADD_UW(2)
510GEN_TRANS_SHADD_UW(3)
511
512static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
513{
514    TCGv t = tcg_temp_new();
515    tcg_gen_ext32u_tl(t, arg1);
516    tcg_gen_add_tl(ret, t, arg2);
517    tcg_temp_free(t);
518}
519
520static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
521{
522    REQUIRE_64BIT(ctx);
523    REQUIRE_ZBA(ctx);
524    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
525}
526
527static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
528{
529    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
530}
531
532static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
533{
534    REQUIRE_64BIT(ctx);
535    REQUIRE_ZBA(ctx);
536    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
537}
538