1/*
2 * RISC-V translation routines for the RVB draft and Zba Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27static void gen_clz(TCGv ret, TCGv arg1)
28{
29    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
30}
31
32static bool trans_clz(DisasContext *ctx, arg_clz *a)
33{
34    REQUIRE_EXT(ctx, RVB);
35    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
36}
37
38static void gen_ctz(TCGv ret, TCGv arg1)
39{
40    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
41}
42
43static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
44{
45    REQUIRE_EXT(ctx, RVB);
46    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
47}
48
49static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
50{
51    REQUIRE_EXT(ctx, RVB);
52    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
53}
54
55static bool trans_andn(DisasContext *ctx, arg_andn *a)
56{
57    REQUIRE_EXT(ctx, RVB);
58    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
59}
60
61static bool trans_orn(DisasContext *ctx, arg_orn *a)
62{
63    REQUIRE_EXT(ctx, RVB);
64    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
65}
66
67static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
68{
69    REQUIRE_EXT(ctx, RVB);
70    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
71}
72
73static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
74{
75    tcg_gen_deposit_tl(ret, arg1, arg2,
76                       TARGET_LONG_BITS / 2,
77                       TARGET_LONG_BITS / 2);
78}
79
80static bool trans_pack(DisasContext *ctx, arg_pack *a)
81{
82    REQUIRE_EXT(ctx, RVB);
83    return gen_arith(ctx, a, EXT_NONE, gen_pack);
84}
85
86static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
87{
88    TCGv t = tcg_temp_new();
89    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
90    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
91    tcg_temp_free(t);
92}
93
94static bool trans_packu(DisasContext *ctx, arg_packu *a)
95{
96    REQUIRE_EXT(ctx, RVB);
97    return gen_arith(ctx, a, EXT_NONE, gen_packu);
98}
99
100static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
101{
102    TCGv t = tcg_temp_new();
103    tcg_gen_ext8u_tl(t, arg2);
104    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
105    tcg_temp_free(t);
106}
107
108static bool trans_packh(DisasContext *ctx, arg_packh *a)
109{
110    REQUIRE_EXT(ctx, RVB);
111    return gen_arith(ctx, a, EXT_NONE, gen_packh);
112}
113
114static bool trans_min(DisasContext *ctx, arg_min *a)
115{
116    REQUIRE_EXT(ctx, RVB);
117    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
118}
119
120static bool trans_max(DisasContext *ctx, arg_max *a)
121{
122    REQUIRE_EXT(ctx, RVB);
123    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
124}
125
126static bool trans_minu(DisasContext *ctx, arg_minu *a)
127{
128    REQUIRE_EXT(ctx, RVB);
129    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
130}
131
132static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
133{
134    REQUIRE_EXT(ctx, RVB);
135    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
136}
137
138static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
139{
140    REQUIRE_EXT(ctx, RVB);
141    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
142}
143
144static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
145{
146    REQUIRE_EXT(ctx, RVB);
147    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
148}
149
150static void gen_sbop_mask(TCGv ret, TCGv shamt)
151{
152    tcg_gen_movi_tl(ret, 1);
153    tcg_gen_shl_tl(ret, ret, shamt);
154}
155
156static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
157{
158    TCGv t = tcg_temp_new();
159
160    gen_sbop_mask(t, shamt);
161    tcg_gen_or_tl(ret, arg1, t);
162
163    tcg_temp_free(t);
164}
165
166static bool trans_bset(DisasContext *ctx, arg_bset *a)
167{
168    REQUIRE_EXT(ctx, RVB);
169    return gen_shift(ctx, a, EXT_NONE, gen_bset);
170}
171
172static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
173{
174    REQUIRE_EXT(ctx, RVB);
175    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
176}
177
178static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
179{
180    TCGv t = tcg_temp_new();
181
182    gen_sbop_mask(t, shamt);
183    tcg_gen_andc_tl(ret, arg1, t);
184
185    tcg_temp_free(t);
186}
187
188static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
189{
190    REQUIRE_EXT(ctx, RVB);
191    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
192}
193
194static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
195{
196    REQUIRE_EXT(ctx, RVB);
197    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
198}
199
200static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
201{
202    TCGv t = tcg_temp_new();
203
204    gen_sbop_mask(t, shamt);
205    tcg_gen_xor_tl(ret, arg1, t);
206
207    tcg_temp_free(t);
208}
209
210static bool trans_binv(DisasContext *ctx, arg_binv *a)
211{
212    REQUIRE_EXT(ctx, RVB);
213    return gen_shift(ctx, a, EXT_NONE, gen_binv);
214}
215
216static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
217{
218    REQUIRE_EXT(ctx, RVB);
219    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
220}
221
222static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
223{
224    tcg_gen_shr_tl(ret, arg1, shamt);
225    tcg_gen_andi_tl(ret, ret, 1);
226}
227
228static bool trans_bext(DisasContext *ctx, arg_bext *a)
229{
230    REQUIRE_EXT(ctx, RVB);
231    return gen_shift(ctx, a, EXT_NONE, gen_bext);
232}
233
234static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
235{
236    REQUIRE_EXT(ctx, RVB);
237    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
238}
239
240static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
241{
242    tcg_gen_not_tl(ret, arg1);
243    tcg_gen_shl_tl(ret, ret, arg2);
244    tcg_gen_not_tl(ret, ret);
245}
246
247static bool trans_slo(DisasContext *ctx, arg_slo *a)
248{
249    REQUIRE_EXT(ctx, RVB);
250    return gen_shift(ctx, a, EXT_NONE, gen_slo);
251}
252
253static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
254{
255    REQUIRE_EXT(ctx, RVB);
256    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
257}
258
259static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
260{
261    tcg_gen_not_tl(ret, arg1);
262    tcg_gen_shr_tl(ret, ret, arg2);
263    tcg_gen_not_tl(ret, ret);
264}
265
266static bool trans_sro(DisasContext *ctx, arg_sro *a)
267{
268    REQUIRE_EXT(ctx, RVB);
269    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
270}
271
272static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
273{
274    REQUIRE_EXT(ctx, RVB);
275    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
276}
277
278static bool trans_ror(DisasContext *ctx, arg_ror *a)
279{
280    REQUIRE_EXT(ctx, RVB);
281    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
282}
283
284static bool trans_rori(DisasContext *ctx, arg_rori *a)
285{
286    REQUIRE_EXT(ctx, RVB);
287    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
288}
289
290static bool trans_rol(DisasContext *ctx, arg_rol *a)
291{
292    REQUIRE_EXT(ctx, RVB);
293    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
294}
295
296static bool trans_grev(DisasContext *ctx, arg_grev *a)
297{
298    REQUIRE_EXT(ctx, RVB);
299    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
300}
301
302static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
303{
304    if (shamt == TARGET_LONG_BITS - 8) {
305        /* rev8, byte swaps */
306        tcg_gen_bswap_tl(dest, src);
307    } else {
308        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
309    }
310}
311
312static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
313{
314    REQUIRE_EXT(ctx, RVB);
315    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
316}
317
318static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
319{
320    REQUIRE_EXT(ctx, RVB);
321    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
322}
323
324static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
325{
326    REQUIRE_EXT(ctx, RVB);
327    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
328}
329
330#define GEN_SHADD(SHAMT)                                       \
331static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
332{                                                              \
333    TCGv t = tcg_temp_new();                                   \
334                                                               \
335    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
336    tcg_gen_add_tl(ret, t, arg2);                              \
337                                                               \
338    tcg_temp_free(t);                                          \
339}
340
341GEN_SHADD(1)
342GEN_SHADD(2)
343GEN_SHADD(3)
344
345#define GEN_TRANS_SHADD(SHAMT)                                             \
346static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
347{                                                                          \
348    REQUIRE_ZBA(ctx);                                                      \
349    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
350}
351
352GEN_TRANS_SHADD(1)
353GEN_TRANS_SHADD(2)
354GEN_TRANS_SHADD(3)
355
356static void gen_clzw(TCGv ret, TCGv arg1)
357{
358    TCGv t = tcg_temp_new();
359    tcg_gen_shli_tl(t, arg1, 32);
360    tcg_gen_clzi_tl(ret, t, 32);
361    tcg_temp_free(t);
362}
363
364static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
365{
366    REQUIRE_64BIT(ctx);
367    REQUIRE_EXT(ctx, RVB);
368    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
369}
370
371static void gen_ctzw(TCGv ret, TCGv arg1)
372{
373    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
374    tcg_gen_ctzi_tl(ret, ret, 64);
375}
376
377static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
378{
379    REQUIRE_64BIT(ctx);
380    REQUIRE_EXT(ctx, RVB);
381    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
382}
383
384static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
385{
386    REQUIRE_64BIT(ctx);
387    REQUIRE_EXT(ctx, RVB);
388    ctx->w = true;
389    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
390}
391
392static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
393{
394    TCGv t = tcg_temp_new();
395    tcg_gen_ext16s_tl(t, arg2);
396    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
397    tcg_temp_free(t);
398}
399
400static bool trans_packw(DisasContext *ctx, arg_packw *a)
401{
402    REQUIRE_64BIT(ctx);
403    REQUIRE_EXT(ctx, RVB);
404    return gen_arith(ctx, a, EXT_NONE, gen_packw);
405}
406
407static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
408{
409    TCGv t = tcg_temp_new();
410    tcg_gen_shri_tl(t, arg1, 16);
411    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
412    tcg_gen_ext32s_tl(ret, ret);
413    tcg_temp_free(t);
414}
415
416static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
417{
418    REQUIRE_64BIT(ctx);
419    REQUIRE_EXT(ctx, RVB);
420    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
421}
422
423static bool trans_slow(DisasContext *ctx, arg_slow *a)
424{
425    REQUIRE_64BIT(ctx);
426    REQUIRE_EXT(ctx, RVB);
427    ctx->w = true;
428    return gen_shift(ctx, a, EXT_NONE, gen_slo);
429}
430
431static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
432{
433    REQUIRE_64BIT(ctx);
434    REQUIRE_EXT(ctx, RVB);
435    ctx->w = true;
436    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
437}
438
439static bool trans_srow(DisasContext *ctx, arg_srow *a)
440{
441    REQUIRE_64BIT(ctx);
442    REQUIRE_EXT(ctx, RVB);
443    ctx->w = true;
444    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
445}
446
447static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
448{
449    REQUIRE_64BIT(ctx);
450    REQUIRE_EXT(ctx, RVB);
451    ctx->w = true;
452    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
453}
454
455static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
456{
457    TCGv_i32 t1 = tcg_temp_new_i32();
458    TCGv_i32 t2 = tcg_temp_new_i32();
459
460    /* truncate to 32-bits */
461    tcg_gen_trunc_tl_i32(t1, arg1);
462    tcg_gen_trunc_tl_i32(t2, arg2);
463
464    tcg_gen_rotr_i32(t1, t1, t2);
465
466    /* sign-extend 64-bits */
467    tcg_gen_ext_i32_tl(ret, t1);
468
469    tcg_temp_free_i32(t1);
470    tcg_temp_free_i32(t2);
471}
472
473static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
474{
475    REQUIRE_64BIT(ctx);
476    REQUIRE_EXT(ctx, RVB);
477    ctx->w = true;
478    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
479}
480
481static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
482{
483    REQUIRE_64BIT(ctx);
484    REQUIRE_EXT(ctx, RVB);
485    ctx->w = true;
486    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
487}
488
489static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
490{
491    TCGv_i32 t1 = tcg_temp_new_i32();
492    TCGv_i32 t2 = tcg_temp_new_i32();
493
494    /* truncate to 32-bits */
495    tcg_gen_trunc_tl_i32(t1, arg1);
496    tcg_gen_trunc_tl_i32(t2, arg2);
497
498    tcg_gen_rotl_i32(t1, t1, t2);
499
500    /* sign-extend 64-bits */
501    tcg_gen_ext_i32_tl(ret, t1);
502
503    tcg_temp_free_i32(t1);
504    tcg_temp_free_i32(t2);
505}
506
507static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
508{
509    REQUIRE_64BIT(ctx);
510    REQUIRE_EXT(ctx, RVB);
511    ctx->w = true;
512    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
513}
514
515static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
516{
517    REQUIRE_64BIT(ctx);
518    REQUIRE_EXT(ctx, RVB);
519    ctx->w = true;
520    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
521}
522
523static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
524{
525    REQUIRE_64BIT(ctx);
526    REQUIRE_EXT(ctx, RVB);
527    ctx->w = true;
528    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
529}
530
531static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
532{
533    REQUIRE_64BIT(ctx);
534    REQUIRE_EXT(ctx, RVB);
535    ctx->w = true;
536    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
537}
538
539static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
540{
541    REQUIRE_64BIT(ctx);
542    REQUIRE_EXT(ctx, RVB);
543    ctx->w = true;
544    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
545}
546
547#define GEN_SHADD_UW(SHAMT)                                       \
548static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
549{                                                                 \
550    TCGv t = tcg_temp_new();                                      \
551                                                                  \
552    tcg_gen_ext32u_tl(t, arg1);                                   \
553                                                                  \
554    tcg_gen_shli_tl(t, t, SHAMT);                                 \
555    tcg_gen_add_tl(ret, t, arg2);                                 \
556                                                                  \
557    tcg_temp_free(t);                                             \
558}
559
560GEN_SHADD_UW(1)
561GEN_SHADD_UW(2)
562GEN_SHADD_UW(3)
563
564#define GEN_TRANS_SHADD_UW(SHAMT)                             \
565static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
566                                    arg_sh##SHAMT##add_uw *a) \
567{                                                             \
568    REQUIRE_64BIT(ctx);                                       \
569    REQUIRE_ZBA(ctx);                                         \
570    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
571}
572
573GEN_TRANS_SHADD_UW(1)
574GEN_TRANS_SHADD_UW(2)
575GEN_TRANS_SHADD_UW(3)
576
577static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
578{
579    TCGv t = tcg_temp_new();
580    tcg_gen_ext32u_tl(t, arg1);
581    tcg_gen_add_tl(ret, t, arg2);
582    tcg_temp_free(t);
583}
584
585static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
586{
587    REQUIRE_64BIT(ctx);
588    REQUIRE_ZBA(ctx);
589    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
590}
591
592static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
593{
594    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
595}
596
597static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
598{
599    REQUIRE_64BIT(ctx);
600    REQUIRE_ZBA(ctx);
601    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
602}
603