1/*
2 * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!ctx->cfg_ptr->ext_zba) {                \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBB(ctx) do {                    \
28    if (!ctx->cfg_ptr->ext_zbb) {                \
29        return false;                            \
30    }                                            \
31} while (0)
32
33#define REQUIRE_ZBC(ctx) do {                    \
34    if (!ctx->cfg_ptr->ext_zbc) {                \
35        return false;                            \
36    }                                            \
37} while (0)
38
39#define REQUIRE_ZBS(ctx) do {                    \
40    if (!ctx->cfg_ptr->ext_zbs) {                \
41        return false;                            \
42    }                                            \
43} while (0)
44
45#define REQUIRE_ZBKB(ctx) do {                   \
46    if (!ctx->cfg_ptr->ext_zbkb) {               \
47        return false;                            \
48    }                                            \
49} while (0)
50
51static void gen_clz(TCGv ret, TCGv arg1)
52{
53    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
54}
55
56static void gen_clzw(TCGv ret, TCGv arg1)
57{
58    TCGv t = tcg_temp_new();
59    tcg_gen_shli_tl(t, arg1, 32);
60    tcg_gen_clzi_tl(ret, t, 32);
61    tcg_temp_free(t);
62}
63
64static bool trans_clz(DisasContext *ctx, arg_clz *a)
65{
66    REQUIRE_ZBB(ctx);
67    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
68}
69
70static void gen_ctz(TCGv ret, TCGv arg1)
71{
72    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
73}
74
75static void gen_ctzw(TCGv ret, TCGv arg1)
76{
77    tcg_gen_ctzi_tl(ret, arg1, 32);
78}
79
80static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
81{
82    REQUIRE_ZBB(ctx);
83    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
84}
85
86static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
87{
88    REQUIRE_ZBB(ctx);
89    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
90}
91
92static bool trans_andn(DisasContext *ctx, arg_andn *a)
93{
94    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
95    return gen_logic(ctx, a, tcg_gen_andc_tl);
96}
97
98static bool trans_orn(DisasContext *ctx, arg_orn *a)
99{
100    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
101    return gen_logic(ctx, a, tcg_gen_orc_tl);
102}
103
104static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
105{
106    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
107    return gen_logic(ctx, a, tcg_gen_eqv_tl);
108}
109
110static bool trans_min(DisasContext *ctx, arg_min *a)
111{
112    REQUIRE_ZBB(ctx);
113    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl, NULL);
114}
115
116static bool trans_max(DisasContext *ctx, arg_max *a)
117{
118    REQUIRE_ZBB(ctx);
119    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl, NULL);
120}
121
122static bool trans_minu(DisasContext *ctx, arg_minu *a)
123{
124    REQUIRE_ZBB(ctx);
125    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl, NULL);
126}
127
128static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
129{
130    REQUIRE_ZBB(ctx);
131    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl, NULL);
132}
133
134static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
135{
136    REQUIRE_ZBB(ctx);
137    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
138}
139
140static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
141{
142    REQUIRE_ZBB(ctx);
143    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
144}
145
146static void gen_sbop_mask(TCGv ret, TCGv shamt)
147{
148    tcg_gen_movi_tl(ret, 1);
149    tcg_gen_shl_tl(ret, ret, shamt);
150}
151
152static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
153{
154    TCGv t = tcg_temp_new();
155
156    gen_sbop_mask(t, shamt);
157    tcg_gen_or_tl(ret, arg1, t);
158
159    tcg_temp_free(t);
160}
161
162static bool trans_bset(DisasContext *ctx, arg_bset *a)
163{
164    REQUIRE_ZBS(ctx);
165    return gen_shift(ctx, a, EXT_NONE, gen_bset, NULL);
166}
167
168static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
169{
170    REQUIRE_ZBS(ctx);
171    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
172}
173
174static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
175{
176    TCGv t = tcg_temp_new();
177
178    gen_sbop_mask(t, shamt);
179    tcg_gen_andc_tl(ret, arg1, t);
180
181    tcg_temp_free(t);
182}
183
184static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
185{
186    REQUIRE_ZBS(ctx);
187    return gen_shift(ctx, a, EXT_NONE, gen_bclr, NULL);
188}
189
190static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
191{
192    REQUIRE_ZBS(ctx);
193    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
194}
195
196static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
197{
198    TCGv t = tcg_temp_new();
199
200    gen_sbop_mask(t, shamt);
201    tcg_gen_xor_tl(ret, arg1, t);
202
203    tcg_temp_free(t);
204}
205
206static bool trans_binv(DisasContext *ctx, arg_binv *a)
207{
208    REQUIRE_ZBS(ctx);
209    return gen_shift(ctx, a, EXT_NONE, gen_binv, NULL);
210}
211
212static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
213{
214    REQUIRE_ZBS(ctx);
215    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
216}
217
218static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
219{
220    tcg_gen_shr_tl(ret, arg1, shamt);
221    tcg_gen_andi_tl(ret, ret, 1);
222}
223
224static bool trans_bext(DisasContext *ctx, arg_bext *a)
225{
226    REQUIRE_ZBS(ctx);
227    return gen_shift(ctx, a, EXT_NONE, gen_bext, NULL);
228}
229
230static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
231{
232    REQUIRE_ZBS(ctx);
233    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
234}
235
236static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
237{
238    TCGv_i32 t1 = tcg_temp_new_i32();
239    TCGv_i32 t2 = tcg_temp_new_i32();
240
241    /* truncate to 32-bits */
242    tcg_gen_trunc_tl_i32(t1, arg1);
243    tcg_gen_trunc_tl_i32(t2, arg2);
244
245    tcg_gen_rotr_i32(t1, t1, t2);
246
247    /* sign-extend 64-bits */
248    tcg_gen_ext_i32_tl(ret, t1);
249
250    tcg_temp_free_i32(t1);
251    tcg_temp_free_i32(t2);
252}
253
254static bool trans_ror(DisasContext *ctx, arg_ror *a)
255{
256    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
257    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
258}
259
260static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
261{
262    TCGv_i32 t1 = tcg_temp_new_i32();
263
264    tcg_gen_trunc_tl_i32(t1, arg1);
265    tcg_gen_rotri_i32(t1, t1, shamt);
266    tcg_gen_ext_i32_tl(ret, t1);
267
268    tcg_temp_free_i32(t1);
269}
270
271static bool trans_rori(DisasContext *ctx, arg_rori *a)
272{
273    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
274    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
275                                   tcg_gen_rotri_tl, gen_roriw, NULL);
276}
277
278static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
279{
280    TCGv_i32 t1 = tcg_temp_new_i32();
281    TCGv_i32 t2 = tcg_temp_new_i32();
282
283    /* truncate to 32-bits */
284    tcg_gen_trunc_tl_i32(t1, arg1);
285    tcg_gen_trunc_tl_i32(t2, arg2);
286
287    tcg_gen_rotl_i32(t1, t1, t2);
288
289    /* sign-extend 64-bits */
290    tcg_gen_ext_i32_tl(ret, t1);
291
292    tcg_temp_free_i32(t1);
293    tcg_temp_free_i32(t2);
294}
295
296static bool trans_rol(DisasContext *ctx, arg_rol *a)
297{
298    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
299    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
300}
301
302static void gen_rev8_32(TCGv ret, TCGv src1)
303{
304    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
305}
306
307static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
308{
309    REQUIRE_32BIT(ctx);
310    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
311    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
312}
313
314static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
315{
316    REQUIRE_64BIT(ctx);
317    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
318    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
319}
320
321static void gen_orc_b(TCGv ret, TCGv source1)
322{
323    TCGv  tmp = tcg_temp_new();
324    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
325
326    /* Set msb in each byte if the byte was non-zero. */
327    tcg_gen_and_tl(tmp, source1, low7);
328    tcg_gen_add_tl(tmp, tmp, low7);
329    tcg_gen_or_tl(tmp, tmp, source1);
330
331    /* Extract the msb to the lsb in each byte */
332    tcg_gen_andc_tl(tmp, tmp, low7);
333    tcg_gen_shri_tl(tmp, tmp, 7);
334
335    /* Replicate the lsb of each byte across the byte. */
336    tcg_gen_muli_tl(ret, tmp, 0xff);
337
338    tcg_temp_free(tmp);
339}
340
341static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
342{
343    REQUIRE_ZBB(ctx);
344    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
345}
346
347#define GEN_SHADD(SHAMT)                                       \
348static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
349{                                                              \
350    TCGv t = tcg_temp_new();                                   \
351                                                               \
352    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
353    tcg_gen_add_tl(ret, t, arg2);                              \
354                                                               \
355    tcg_temp_free(t);                                          \
356}
357
358GEN_SHADD(1)
359GEN_SHADD(2)
360GEN_SHADD(3)
361
362#define GEN_TRANS_SHADD(SHAMT)                                             \
363static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
364{                                                                          \
365    REQUIRE_ZBA(ctx);                                                      \
366    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add, NULL);          \
367}
368
369GEN_TRANS_SHADD(1)
370GEN_TRANS_SHADD(2)
371GEN_TRANS_SHADD(3)
372
373static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
374{
375    REQUIRE_32BIT(ctx);
376    REQUIRE_ZBB(ctx);
377    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
378}
379
380static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
381{
382    REQUIRE_64BIT(ctx);
383    REQUIRE_ZBB(ctx);
384    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
385}
386
387static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
388{
389    REQUIRE_64BIT(ctx);
390    REQUIRE_ZBB(ctx);
391    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
392}
393
394static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
395{
396    REQUIRE_64BIT(ctx);
397    REQUIRE_ZBB(ctx);
398    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
399}
400
401static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
402{
403    REQUIRE_64BIT(ctx);
404    REQUIRE_ZBB(ctx);
405    ctx->ol = MXL_RV32;
406    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
407}
408
409static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
410{
411    REQUIRE_64BIT(ctx);
412    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
413    ctx->ol = MXL_RV32;
414    return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
415}
416
417static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
418{
419    REQUIRE_64BIT(ctx);
420    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
421    ctx->ol = MXL_RV32;
422    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
423}
424
425static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
426{
427    REQUIRE_64BIT(ctx);
428    REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
429    ctx->ol = MXL_RV32;
430    return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
431}
432
433#define GEN_SHADD_UW(SHAMT)                                       \
434static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
435{                                                                 \
436    TCGv t = tcg_temp_new();                                      \
437                                                                  \
438    tcg_gen_ext32u_tl(t, arg1);                                   \
439                                                                  \
440    tcg_gen_shli_tl(t, t, SHAMT);                                 \
441    tcg_gen_add_tl(ret, t, arg2);                                 \
442                                                                  \
443    tcg_temp_free(t);                                             \
444}
445
446GEN_SHADD_UW(1)
447GEN_SHADD_UW(2)
448GEN_SHADD_UW(3)
449
450#define GEN_TRANS_SHADD_UW(SHAMT)                             \
451static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
452                                    arg_sh##SHAMT##add_uw *a) \
453{                                                             \
454    REQUIRE_64BIT(ctx);                                       \
455    REQUIRE_ZBA(ctx);                                         \
456    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw, NULL); \
457}
458
459GEN_TRANS_SHADD_UW(1)
460GEN_TRANS_SHADD_UW(2)
461GEN_TRANS_SHADD_UW(3)
462
463static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
464{
465    TCGv t = tcg_temp_new();
466    tcg_gen_ext32u_tl(t, arg1);
467    tcg_gen_add_tl(ret, t, arg2);
468    tcg_temp_free(t);
469}
470
471static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
472{
473    REQUIRE_64BIT(ctx);
474    REQUIRE_ZBA(ctx);
475    return gen_arith(ctx, a, EXT_NONE, gen_add_uw, NULL);
476}
477
478static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
479{
480    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
481}
482
483static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
484{
485    REQUIRE_64BIT(ctx);
486    REQUIRE_ZBA(ctx);
487    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw, NULL);
488}
489
490static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
491{
492    REQUIRE_ZBC(ctx);
493    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
494}
495
496static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
497{
498     gen_helper_clmulr(dst, src1, src2);
499     tcg_gen_shri_tl(dst, dst, 1);
500}
501
502static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
503{
504    REQUIRE_ZBC(ctx);
505    return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
506}
507
508static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
509{
510    REQUIRE_ZBC(ctx);
511    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
512}
513
514static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
515{
516    tcg_gen_deposit_tl(ret, src1, src2,
517                       TARGET_LONG_BITS / 2,
518                       TARGET_LONG_BITS / 2);
519}
520
521static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
522{
523    TCGv t = tcg_temp_new();
524
525    tcg_gen_ext8u_tl(t, src2);
526    tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
527    tcg_temp_free(t);
528}
529
530static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
531{
532    TCGv t = tcg_temp_new();
533
534    tcg_gen_ext16s_tl(t, src2);
535    tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
536    tcg_temp_free(t);
537}
538
539static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
540{
541    REQUIRE_ZBKB(ctx);
542    return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
543}
544
545static bool trans_pack(DisasContext *ctx, arg_pack *a)
546{
547    REQUIRE_ZBKB(ctx);
548    return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
549}
550
551static bool trans_packh(DisasContext *ctx, arg_packh *a)
552{
553    REQUIRE_ZBKB(ctx);
554    return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
555}
556
557static bool trans_packw(DisasContext *ctx, arg_packw *a)
558{
559    REQUIRE_64BIT(ctx);
560    REQUIRE_ZBKB(ctx);
561    return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
562}
563
564static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
565{
566    REQUIRE_32BIT(ctx);
567    REQUIRE_ZBKB(ctx);
568    return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
569}
570
571static bool trans_zip(DisasContext *ctx, arg_zip *a)
572{
573    REQUIRE_32BIT(ctx);
574    REQUIRE_ZBKB(ctx);
575    return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
576}
577