1/*
2 * RISC-V translation routines for the Zb[abcs] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBB(ctx) do {                    \
28    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
29        return false;                            \
30    }                                            \
31} while (0)
32
33#define REQUIRE_ZBC(ctx) do {                    \
34    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
35        return false;                            \
36    }                                            \
37} while (0)
38
39#define REQUIRE_ZBS(ctx) do {                    \
40    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
41        return false;                            \
42    }                                            \
43} while (0)
44
45static void gen_clz(TCGv ret, TCGv arg1)
46{
47    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
48}
49
50static void gen_clzw(TCGv ret, TCGv arg1)
51{
52    TCGv t = tcg_temp_new();
53    tcg_gen_shli_tl(t, arg1, 32);
54    tcg_gen_clzi_tl(ret, t, 32);
55    tcg_temp_free(t);
56}
57
58static bool trans_clz(DisasContext *ctx, arg_clz *a)
59{
60    REQUIRE_ZBB(ctx);
61    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
62}
63
64static void gen_ctz(TCGv ret, TCGv arg1)
65{
66    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
67}
68
69static void gen_ctzw(TCGv ret, TCGv arg1)
70{
71    tcg_gen_ctzi_tl(ret, arg1, 32);
72}
73
74static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
75{
76    REQUIRE_ZBB(ctx);
77    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
78}
79
80static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
81{
82    REQUIRE_ZBB(ctx);
83    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
84}
85
86static bool trans_andn(DisasContext *ctx, arg_andn *a)
87{
88    REQUIRE_ZBB(ctx);
89    return gen_logic(ctx, a, tcg_gen_andc_tl);
90}
91
92static bool trans_orn(DisasContext *ctx, arg_orn *a)
93{
94    REQUIRE_ZBB(ctx);
95    return gen_logic(ctx, a, tcg_gen_orc_tl);
96}
97
98static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
99{
100    REQUIRE_ZBB(ctx);
101    return gen_logic(ctx, a, tcg_gen_eqv_tl);
102}
103
104static bool trans_min(DisasContext *ctx, arg_min *a)
105{
106    REQUIRE_ZBB(ctx);
107    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
108}
109
110static bool trans_max(DisasContext *ctx, arg_max *a)
111{
112    REQUIRE_ZBB(ctx);
113    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
114}
115
116static bool trans_minu(DisasContext *ctx, arg_minu *a)
117{
118    REQUIRE_ZBB(ctx);
119    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
120}
121
122static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
123{
124    REQUIRE_ZBB(ctx);
125    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
126}
127
128static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
129{
130    REQUIRE_ZBB(ctx);
131    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
132}
133
134static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
135{
136    REQUIRE_ZBB(ctx);
137    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
138}
139
140static void gen_sbop_mask(TCGv ret, TCGv shamt)
141{
142    tcg_gen_movi_tl(ret, 1);
143    tcg_gen_shl_tl(ret, ret, shamt);
144}
145
146static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
147{
148    TCGv t = tcg_temp_new();
149
150    gen_sbop_mask(t, shamt);
151    tcg_gen_or_tl(ret, arg1, t);
152
153    tcg_temp_free(t);
154}
155
156static bool trans_bset(DisasContext *ctx, arg_bset *a)
157{
158    REQUIRE_ZBS(ctx);
159    return gen_shift(ctx, a, EXT_NONE, gen_bset);
160}
161
162static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
163{
164    REQUIRE_ZBS(ctx);
165    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
166}
167
168static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
169{
170    TCGv t = tcg_temp_new();
171
172    gen_sbop_mask(t, shamt);
173    tcg_gen_andc_tl(ret, arg1, t);
174
175    tcg_temp_free(t);
176}
177
178static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
179{
180    REQUIRE_ZBS(ctx);
181    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
182}
183
184static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
185{
186    REQUIRE_ZBS(ctx);
187    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
188}
189
190static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
191{
192    TCGv t = tcg_temp_new();
193
194    gen_sbop_mask(t, shamt);
195    tcg_gen_xor_tl(ret, arg1, t);
196
197    tcg_temp_free(t);
198}
199
200static bool trans_binv(DisasContext *ctx, arg_binv *a)
201{
202    REQUIRE_ZBS(ctx);
203    return gen_shift(ctx, a, EXT_NONE, gen_binv);
204}
205
206static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
207{
208    REQUIRE_ZBS(ctx);
209    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
210}
211
212static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
213{
214    tcg_gen_shr_tl(ret, arg1, shamt);
215    tcg_gen_andi_tl(ret, ret, 1);
216}
217
218static bool trans_bext(DisasContext *ctx, arg_bext *a)
219{
220    REQUIRE_ZBS(ctx);
221    return gen_shift(ctx, a, EXT_NONE, gen_bext);
222}
223
224static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
225{
226    REQUIRE_ZBS(ctx);
227    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
228}
229
230static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
231{
232    TCGv_i32 t1 = tcg_temp_new_i32();
233    TCGv_i32 t2 = tcg_temp_new_i32();
234
235    /* truncate to 32-bits */
236    tcg_gen_trunc_tl_i32(t1, arg1);
237    tcg_gen_trunc_tl_i32(t2, arg2);
238
239    tcg_gen_rotr_i32(t1, t1, t2);
240
241    /* sign-extend 64-bits */
242    tcg_gen_ext_i32_tl(ret, t1);
243
244    tcg_temp_free_i32(t1);
245    tcg_temp_free_i32(t2);
246}
247
248static bool trans_ror(DisasContext *ctx, arg_ror *a)
249{
250    REQUIRE_ZBB(ctx);
251    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw);
252}
253
254static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
255{
256    TCGv_i32 t1 = tcg_temp_new_i32();
257
258    tcg_gen_trunc_tl_i32(t1, arg1);
259    tcg_gen_rotri_i32(t1, t1, shamt);
260    tcg_gen_ext_i32_tl(ret, t1);
261
262    tcg_temp_free_i32(t1);
263}
264
265static bool trans_rori(DisasContext *ctx, arg_rori *a)
266{
267    REQUIRE_ZBB(ctx);
268    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
269                                   tcg_gen_rotri_tl, gen_roriw);
270}
271
272static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
273{
274    TCGv_i32 t1 = tcg_temp_new_i32();
275    TCGv_i32 t2 = tcg_temp_new_i32();
276
277    /* truncate to 32-bits */
278    tcg_gen_trunc_tl_i32(t1, arg1);
279    tcg_gen_trunc_tl_i32(t2, arg2);
280
281    tcg_gen_rotl_i32(t1, t1, t2);
282
283    /* sign-extend 64-bits */
284    tcg_gen_ext_i32_tl(ret, t1);
285
286    tcg_temp_free_i32(t1);
287    tcg_temp_free_i32(t2);
288}
289
290static bool trans_rol(DisasContext *ctx, arg_rol *a)
291{
292    REQUIRE_ZBB(ctx);
293    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw);
294}
295
296static void gen_rev8_32(TCGv ret, TCGv src1)
297{
298    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
299}
300
301static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
302{
303    REQUIRE_32BIT(ctx);
304    REQUIRE_ZBB(ctx);
305    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
306}
307
308static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
309{
310    REQUIRE_64BIT(ctx);
311    REQUIRE_ZBB(ctx);
312    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
313}
314
315static void gen_orc_b(TCGv ret, TCGv source1)
316{
317    TCGv  tmp = tcg_temp_new();
318    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
319
320    /* Set msb in each byte if the byte was non-zero. */
321    tcg_gen_and_tl(tmp, source1, low7);
322    tcg_gen_add_tl(tmp, tmp, low7);
323    tcg_gen_or_tl(tmp, tmp, source1);
324
325    /* Extract the msb to the lsb in each byte */
326    tcg_gen_andc_tl(tmp, tmp, low7);
327    tcg_gen_shri_tl(tmp, tmp, 7);
328
329    /* Replicate the lsb of each byte across the byte. */
330    tcg_gen_muli_tl(ret, tmp, 0xff);
331
332    tcg_temp_free(tmp);
333}
334
335static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
336{
337    REQUIRE_ZBB(ctx);
338    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
339}
340
341#define GEN_SHADD(SHAMT)                                       \
342static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
343{                                                              \
344    TCGv t = tcg_temp_new();                                   \
345                                                               \
346    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
347    tcg_gen_add_tl(ret, t, arg2);                              \
348                                                               \
349    tcg_temp_free(t);                                          \
350}
351
352GEN_SHADD(1)
353GEN_SHADD(2)
354GEN_SHADD(3)
355
356#define GEN_TRANS_SHADD(SHAMT)                                             \
357static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
358{                                                                          \
359    REQUIRE_ZBA(ctx);                                                      \
360    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
361}
362
363GEN_TRANS_SHADD(1)
364GEN_TRANS_SHADD(2)
365GEN_TRANS_SHADD(3)
366
367static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
368{
369    REQUIRE_32BIT(ctx);
370    REQUIRE_ZBB(ctx);
371    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
372}
373
374static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
375{
376    REQUIRE_64BIT(ctx);
377    REQUIRE_ZBB(ctx);
378    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
379}
380
381static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
382{
383    REQUIRE_64BIT(ctx);
384    REQUIRE_ZBB(ctx);
385    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
386}
387
388static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
389{
390    REQUIRE_64BIT(ctx);
391    REQUIRE_ZBB(ctx);
392    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
393}
394
395static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
396{
397    REQUIRE_64BIT(ctx);
398    REQUIRE_ZBB(ctx);
399    ctx->ol = MXL_RV32;
400    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
401}
402
403static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
404{
405    REQUIRE_64BIT(ctx);
406    REQUIRE_ZBB(ctx);
407    ctx->ol = MXL_RV32;
408    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
409}
410
411static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
412{
413    REQUIRE_64BIT(ctx);
414    REQUIRE_ZBB(ctx);
415    ctx->ol = MXL_RV32;
416    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw);
417}
418
419static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
420{
421    REQUIRE_64BIT(ctx);
422    REQUIRE_ZBB(ctx);
423    ctx->ol = MXL_RV32;
424    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
425}
426
427#define GEN_SHADD_UW(SHAMT)                                       \
428static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
429{                                                                 \
430    TCGv t = tcg_temp_new();                                      \
431                                                                  \
432    tcg_gen_ext32u_tl(t, arg1);                                   \
433                                                                  \
434    tcg_gen_shli_tl(t, t, SHAMT);                                 \
435    tcg_gen_add_tl(ret, t, arg2);                                 \
436                                                                  \
437    tcg_temp_free(t);                                             \
438}
439
440GEN_SHADD_UW(1)
441GEN_SHADD_UW(2)
442GEN_SHADD_UW(3)
443
444#define GEN_TRANS_SHADD_UW(SHAMT)                             \
445static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
446                                    arg_sh##SHAMT##add_uw *a) \
447{                                                             \
448    REQUIRE_64BIT(ctx);                                       \
449    REQUIRE_ZBA(ctx);                                         \
450    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
451}
452
453GEN_TRANS_SHADD_UW(1)
454GEN_TRANS_SHADD_UW(2)
455GEN_TRANS_SHADD_UW(3)
456
457static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
458{
459    TCGv t = tcg_temp_new();
460    tcg_gen_ext32u_tl(t, arg1);
461    tcg_gen_add_tl(ret, t, arg2);
462    tcg_temp_free(t);
463}
464
465static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
466{
467    REQUIRE_64BIT(ctx);
468    REQUIRE_ZBA(ctx);
469    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
470}
471
472static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
473{
474    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
475}
476
477static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
478{
479    REQUIRE_64BIT(ctx);
480    REQUIRE_ZBA(ctx);
481    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
482}
483
484static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
485{
486    REQUIRE_ZBC(ctx);
487    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
488}
489
490static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
491{
492     gen_helper_clmulr(dst, src1, src2);
493     tcg_gen_shri_tl(dst, dst, 1);
494}
495
496static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
497{
498    REQUIRE_ZBC(ctx);
499    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
500}
501
502static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
503{
504    REQUIRE_ZBC(ctx);
505    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
506}
507