1/*
2 * RISC-V translation routines for the Zb[abcs] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBB(ctx) do {                    \
28    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
29        return false;                            \
30    }                                            \
31} while (0)
32
33#define REQUIRE_ZBC(ctx) do {                    \
34    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
35        return false;                            \
36    }                                            \
37} while (0)
38
39#define REQUIRE_ZBS(ctx) do {                    \
40    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
41        return false;                            \
42    }                                            \
43} while (0)
44
45static void gen_clz(TCGv ret, TCGv arg1)
46{
47    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
48}
49
50static bool trans_clz(DisasContext *ctx, arg_clz *a)
51{
52    REQUIRE_ZBB(ctx);
53    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
54}
55
56static void gen_ctz(TCGv ret, TCGv arg1)
57{
58    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
59}
60
61static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
62{
63    REQUIRE_ZBB(ctx);
64    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
65}
66
67static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
68{
69    REQUIRE_ZBB(ctx);
70    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
71}
72
73static bool trans_andn(DisasContext *ctx, arg_andn *a)
74{
75    REQUIRE_ZBB(ctx);
76    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
77}
78
79static bool trans_orn(DisasContext *ctx, arg_orn *a)
80{
81    REQUIRE_ZBB(ctx);
82    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
83}
84
85static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
86{
87    REQUIRE_ZBB(ctx);
88    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
89}
90
91static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
92{
93    tcg_gen_deposit_tl(ret, arg1, arg2,
94                       TARGET_LONG_BITS / 2,
95                       TARGET_LONG_BITS / 2);
96}
97
98static bool trans_pack(DisasContext *ctx, arg_pack *a)
99{
100    REQUIRE_EXT(ctx, RVB);
101    return gen_arith(ctx, a, EXT_NONE, gen_pack);
102}
103
104static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
105{
106    TCGv t = tcg_temp_new();
107    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
108    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
109    tcg_temp_free(t);
110}
111
112static bool trans_packu(DisasContext *ctx, arg_packu *a)
113{
114    REQUIRE_EXT(ctx, RVB);
115    return gen_arith(ctx, a, EXT_NONE, gen_packu);
116}
117
118static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
119{
120    TCGv t = tcg_temp_new();
121    tcg_gen_ext8u_tl(t, arg2);
122    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
123    tcg_temp_free(t);
124}
125
126static bool trans_packh(DisasContext *ctx, arg_packh *a)
127{
128    REQUIRE_EXT(ctx, RVB);
129    return gen_arith(ctx, a, EXT_NONE, gen_packh);
130}
131
132static bool trans_min(DisasContext *ctx, arg_min *a)
133{
134    REQUIRE_ZBB(ctx);
135    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
136}
137
138static bool trans_max(DisasContext *ctx, arg_max *a)
139{
140    REQUIRE_ZBB(ctx);
141    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
142}
143
144static bool trans_minu(DisasContext *ctx, arg_minu *a)
145{
146    REQUIRE_ZBB(ctx);
147    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
148}
149
150static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
151{
152    REQUIRE_ZBB(ctx);
153    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
154}
155
156static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
157{
158    REQUIRE_ZBB(ctx);
159    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
160}
161
162static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
163{
164    REQUIRE_ZBB(ctx);
165    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
166}
167
168static void gen_sbop_mask(TCGv ret, TCGv shamt)
169{
170    tcg_gen_movi_tl(ret, 1);
171    tcg_gen_shl_tl(ret, ret, shamt);
172}
173
174static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
175{
176    TCGv t = tcg_temp_new();
177
178    gen_sbop_mask(t, shamt);
179    tcg_gen_or_tl(ret, arg1, t);
180
181    tcg_temp_free(t);
182}
183
184static bool trans_bset(DisasContext *ctx, arg_bset *a)
185{
186    REQUIRE_ZBS(ctx);
187    return gen_shift(ctx, a, EXT_NONE, gen_bset);
188}
189
190static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
191{
192    REQUIRE_ZBS(ctx);
193    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
194}
195
196static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
197{
198    TCGv t = tcg_temp_new();
199
200    gen_sbop_mask(t, shamt);
201    tcg_gen_andc_tl(ret, arg1, t);
202
203    tcg_temp_free(t);
204}
205
206static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
207{
208    REQUIRE_ZBS(ctx);
209    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
210}
211
212static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
213{
214    REQUIRE_ZBS(ctx);
215    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
216}
217
218static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
219{
220    TCGv t = tcg_temp_new();
221
222    gen_sbop_mask(t, shamt);
223    tcg_gen_xor_tl(ret, arg1, t);
224
225    tcg_temp_free(t);
226}
227
228static bool trans_binv(DisasContext *ctx, arg_binv *a)
229{
230    REQUIRE_ZBS(ctx);
231    return gen_shift(ctx, a, EXT_NONE, gen_binv);
232}
233
234static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
235{
236    REQUIRE_ZBS(ctx);
237    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
238}
239
240static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
241{
242    tcg_gen_shr_tl(ret, arg1, shamt);
243    tcg_gen_andi_tl(ret, ret, 1);
244}
245
246static bool trans_bext(DisasContext *ctx, arg_bext *a)
247{
248    REQUIRE_ZBS(ctx);
249    return gen_shift(ctx, a, EXT_NONE, gen_bext);
250}
251
252static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
253{
254    REQUIRE_ZBS(ctx);
255    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
256}
257
258static bool trans_ror(DisasContext *ctx, arg_ror *a)
259{
260    REQUIRE_ZBB(ctx);
261    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
262}
263
264static bool trans_rori(DisasContext *ctx, arg_rori *a)
265{
266    REQUIRE_ZBB(ctx);
267    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
268}
269
270static bool trans_rol(DisasContext *ctx, arg_rol *a)
271{
272    REQUIRE_ZBB(ctx);
273    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
274}
275
276static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
277{
278    REQUIRE_32BIT(ctx);
279    REQUIRE_ZBB(ctx);
280    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
281}
282
283static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
284{
285    REQUIRE_64BIT(ctx);
286    REQUIRE_ZBB(ctx);
287    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
288}
289
290static void gen_orc_b(TCGv ret, TCGv source1)
291{
292    TCGv  tmp = tcg_temp_new();
293    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
294
295    /* Set lsb in each byte if the byte was zero. */
296    tcg_gen_sub_tl(tmp, source1, ones);
297    tcg_gen_andc_tl(tmp, tmp, source1);
298    tcg_gen_shri_tl(tmp, tmp, 7);
299    tcg_gen_andc_tl(tmp, ones, tmp);
300
301    /* Replicate the lsb of each byte across the byte. */
302    tcg_gen_muli_tl(ret, tmp, 0xff);
303
304    tcg_temp_free(tmp);
305}
306
307static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
308{
309    REQUIRE_ZBB(ctx);
310    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
311}
312
313#define GEN_SHADD(SHAMT)                                       \
314static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
315{                                                              \
316    TCGv t = tcg_temp_new();                                   \
317                                                               \
318    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
319    tcg_gen_add_tl(ret, t, arg2);                              \
320                                                               \
321    tcg_temp_free(t);                                          \
322}
323
324GEN_SHADD(1)
325GEN_SHADD(2)
326GEN_SHADD(3)
327
328#define GEN_TRANS_SHADD(SHAMT)                                             \
329static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
330{                                                                          \
331    REQUIRE_ZBA(ctx);                                                      \
332    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
333}
334
335GEN_TRANS_SHADD(1)
336GEN_TRANS_SHADD(2)
337GEN_TRANS_SHADD(3)
338
339static void gen_clzw(TCGv ret, TCGv arg1)
340{
341    TCGv t = tcg_temp_new();
342    tcg_gen_shli_tl(t, arg1, 32);
343    tcg_gen_clzi_tl(ret, t, 32);
344    tcg_temp_free(t);
345}
346
347static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
348{
349    REQUIRE_64BIT(ctx);
350    REQUIRE_ZBB(ctx);
351    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
352}
353
354static void gen_ctzw(TCGv ret, TCGv arg1)
355{
356    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
357    tcg_gen_ctzi_tl(ret, ret, 64);
358}
359
360static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
361{
362    REQUIRE_64BIT(ctx);
363    REQUIRE_ZBB(ctx);
364    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
365}
366
367static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
368{
369    REQUIRE_64BIT(ctx);
370    REQUIRE_ZBB(ctx);
371    ctx->w = true;
372    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
373}
374
375static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
376{
377    TCGv t = tcg_temp_new();
378    tcg_gen_ext16s_tl(t, arg2);
379    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
380    tcg_temp_free(t);
381}
382
383static bool trans_packw(DisasContext *ctx, arg_packw *a)
384{
385    REQUIRE_64BIT(ctx);
386    REQUIRE_EXT(ctx, RVB);
387    return gen_arith(ctx, a, EXT_NONE, gen_packw);
388}
389
390static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
391{
392    TCGv t = tcg_temp_new();
393    tcg_gen_shri_tl(t, arg1, 16);
394    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
395    tcg_gen_ext32s_tl(ret, ret);
396    tcg_temp_free(t);
397}
398
399static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
400{
401    REQUIRE_64BIT(ctx);
402    REQUIRE_EXT(ctx, RVB);
403    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
404}
405
406static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
407{
408    TCGv_i32 t1 = tcg_temp_new_i32();
409    TCGv_i32 t2 = tcg_temp_new_i32();
410
411    /* truncate to 32-bits */
412    tcg_gen_trunc_tl_i32(t1, arg1);
413    tcg_gen_trunc_tl_i32(t2, arg2);
414
415    tcg_gen_rotr_i32(t1, t1, t2);
416
417    /* sign-extend 64-bits */
418    tcg_gen_ext_i32_tl(ret, t1);
419
420    tcg_temp_free_i32(t1);
421    tcg_temp_free_i32(t2);
422}
423
424static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
425{
426    REQUIRE_64BIT(ctx);
427    REQUIRE_ZBB(ctx);
428    ctx->w = true;
429    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
430}
431
432static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
433{
434    REQUIRE_64BIT(ctx);
435    REQUIRE_ZBB(ctx);
436    ctx->w = true;
437    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
438}
439
440static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
441{
442    TCGv_i32 t1 = tcg_temp_new_i32();
443    TCGv_i32 t2 = tcg_temp_new_i32();
444
445    /* truncate to 32-bits */
446    tcg_gen_trunc_tl_i32(t1, arg1);
447    tcg_gen_trunc_tl_i32(t2, arg2);
448
449    tcg_gen_rotl_i32(t1, t1, t2);
450
451    /* sign-extend 64-bits */
452    tcg_gen_ext_i32_tl(ret, t1);
453
454    tcg_temp_free_i32(t1);
455    tcg_temp_free_i32(t2);
456}
457
458static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
459{
460    REQUIRE_64BIT(ctx);
461    REQUIRE_ZBB(ctx);
462    ctx->w = true;
463    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
464}
465
466#define GEN_SHADD_UW(SHAMT)                                       \
467static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
468{                                                                 \
469    TCGv t = tcg_temp_new();                                      \
470                                                                  \
471    tcg_gen_ext32u_tl(t, arg1);                                   \
472                                                                  \
473    tcg_gen_shli_tl(t, t, SHAMT);                                 \
474    tcg_gen_add_tl(ret, t, arg2);                                 \
475                                                                  \
476    tcg_temp_free(t);                                             \
477}
478
479GEN_SHADD_UW(1)
480GEN_SHADD_UW(2)
481GEN_SHADD_UW(3)
482
483#define GEN_TRANS_SHADD_UW(SHAMT)                             \
484static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
485                                    arg_sh##SHAMT##add_uw *a) \
486{                                                             \
487    REQUIRE_64BIT(ctx);                                       \
488    REQUIRE_ZBA(ctx);                                         \
489    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
490}
491
492GEN_TRANS_SHADD_UW(1)
493GEN_TRANS_SHADD_UW(2)
494GEN_TRANS_SHADD_UW(3)
495
496static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
497{
498    TCGv t = tcg_temp_new();
499    tcg_gen_ext32u_tl(t, arg1);
500    tcg_gen_add_tl(ret, t, arg2);
501    tcg_temp_free(t);
502}
503
504static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
505{
506    REQUIRE_64BIT(ctx);
507    REQUIRE_ZBA(ctx);
508    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
509}
510
511static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
512{
513    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
514}
515
516static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
517{
518    REQUIRE_64BIT(ctx);
519    REQUIRE_ZBA(ctx);
520    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
521}
522
523static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
524{
525    REQUIRE_ZBC(ctx);
526    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
527}
528
529static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
530{
531     gen_helper_clmulr(dst, src1, src2);
532     tcg_gen_shri_tl(dst, dst, 1);
533}
534
535static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
536{
537    REQUIRE_ZBC(ctx);
538    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
539}
540
541static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
542{
543    REQUIRE_ZBC(ctx);
544    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
545}
546