1/*
2 * RISC-V translation routines for the RVB Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21static void gen_clz(TCGv ret, TCGv arg1)
22{
23    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
24}
25
26static bool trans_clz(DisasContext *ctx, arg_clz *a)
27{
28    REQUIRE_EXT(ctx, RVB);
29    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
30}
31
32static void gen_ctz(TCGv ret, TCGv arg1)
33{
34    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
35}
36
37static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
38{
39    REQUIRE_EXT(ctx, RVB);
40    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
41}
42
43static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
44{
45    REQUIRE_EXT(ctx, RVB);
46    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
47}
48
49static bool trans_andn(DisasContext *ctx, arg_andn *a)
50{
51    REQUIRE_EXT(ctx, RVB);
52    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
53}
54
55static bool trans_orn(DisasContext *ctx, arg_orn *a)
56{
57    REQUIRE_EXT(ctx, RVB);
58    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
59}
60
61static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
62{
63    REQUIRE_EXT(ctx, RVB);
64    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
65}
66
67static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
68{
69    tcg_gen_deposit_tl(ret, arg1, arg2,
70                       TARGET_LONG_BITS / 2,
71                       TARGET_LONG_BITS / 2);
72}
73
74static bool trans_pack(DisasContext *ctx, arg_pack *a)
75{
76    REQUIRE_EXT(ctx, RVB);
77    return gen_arith(ctx, a, EXT_NONE, gen_pack);
78}
79
80static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
81{
82    TCGv t = tcg_temp_new();
83    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
84    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
85    tcg_temp_free(t);
86}
87
88static bool trans_packu(DisasContext *ctx, arg_packu *a)
89{
90    REQUIRE_EXT(ctx, RVB);
91    return gen_arith(ctx, a, EXT_NONE, gen_packu);
92}
93
94static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
95{
96    TCGv t = tcg_temp_new();
97    tcg_gen_ext8u_tl(t, arg2);
98    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
99    tcg_temp_free(t);
100}
101
102static bool trans_packh(DisasContext *ctx, arg_packh *a)
103{
104    REQUIRE_EXT(ctx, RVB);
105    return gen_arith(ctx, a, EXT_NONE, gen_packh);
106}
107
108static bool trans_min(DisasContext *ctx, arg_min *a)
109{
110    REQUIRE_EXT(ctx, RVB);
111    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
112}
113
114static bool trans_max(DisasContext *ctx, arg_max *a)
115{
116    REQUIRE_EXT(ctx, RVB);
117    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
118}
119
120static bool trans_minu(DisasContext *ctx, arg_minu *a)
121{
122    REQUIRE_EXT(ctx, RVB);
123    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
124}
125
126static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
127{
128    REQUIRE_EXT(ctx, RVB);
129    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
130}
131
132static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
133{
134    REQUIRE_EXT(ctx, RVB);
135    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
136}
137
138static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
139{
140    REQUIRE_EXT(ctx, RVB);
141    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
142}
143
144static void gen_sbop_mask(TCGv ret, TCGv shamt)
145{
146    tcg_gen_movi_tl(ret, 1);
147    tcg_gen_shl_tl(ret, ret, shamt);
148}
149
150static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
151{
152    TCGv t = tcg_temp_new();
153
154    gen_sbop_mask(t, shamt);
155    tcg_gen_or_tl(ret, arg1, t);
156
157    tcg_temp_free(t);
158}
159
160static bool trans_bset(DisasContext *ctx, arg_bset *a)
161{
162    REQUIRE_EXT(ctx, RVB);
163    return gen_shift(ctx, a, EXT_NONE, gen_bset);
164}
165
166static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
167{
168    REQUIRE_EXT(ctx, RVB);
169    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
170}
171
172static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
173{
174    TCGv t = tcg_temp_new();
175
176    gen_sbop_mask(t, shamt);
177    tcg_gen_andc_tl(ret, arg1, t);
178
179    tcg_temp_free(t);
180}
181
182static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
183{
184    REQUIRE_EXT(ctx, RVB);
185    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
186}
187
188static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
189{
190    REQUIRE_EXT(ctx, RVB);
191    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
192}
193
194static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
195{
196    TCGv t = tcg_temp_new();
197
198    gen_sbop_mask(t, shamt);
199    tcg_gen_xor_tl(ret, arg1, t);
200
201    tcg_temp_free(t);
202}
203
204static bool trans_binv(DisasContext *ctx, arg_binv *a)
205{
206    REQUIRE_EXT(ctx, RVB);
207    return gen_shift(ctx, a, EXT_NONE, gen_binv);
208}
209
210static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
211{
212    REQUIRE_EXT(ctx, RVB);
213    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
214}
215
216static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
217{
218    tcg_gen_shr_tl(ret, arg1, shamt);
219    tcg_gen_andi_tl(ret, ret, 1);
220}
221
222static bool trans_bext(DisasContext *ctx, arg_bext *a)
223{
224    REQUIRE_EXT(ctx, RVB);
225    return gen_shift(ctx, a, EXT_NONE, gen_bext);
226}
227
228static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
229{
230    REQUIRE_EXT(ctx, RVB);
231    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
232}
233
234static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
235{
236    tcg_gen_not_tl(ret, arg1);
237    tcg_gen_shl_tl(ret, ret, arg2);
238    tcg_gen_not_tl(ret, ret);
239}
240
241static bool trans_slo(DisasContext *ctx, arg_slo *a)
242{
243    REQUIRE_EXT(ctx, RVB);
244    return gen_shift(ctx, a, EXT_NONE, gen_slo);
245}
246
247static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
248{
249    REQUIRE_EXT(ctx, RVB);
250    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
251}
252
253static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
254{
255    tcg_gen_not_tl(ret, arg1);
256    tcg_gen_shr_tl(ret, ret, arg2);
257    tcg_gen_not_tl(ret, ret);
258}
259
260static bool trans_sro(DisasContext *ctx, arg_sro *a)
261{
262    REQUIRE_EXT(ctx, RVB);
263    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
264}
265
266static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
267{
268    REQUIRE_EXT(ctx, RVB);
269    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
270}
271
272static bool trans_ror(DisasContext *ctx, arg_ror *a)
273{
274    REQUIRE_EXT(ctx, RVB);
275    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
276}
277
278static bool trans_rori(DisasContext *ctx, arg_rori *a)
279{
280    REQUIRE_EXT(ctx, RVB);
281    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
282}
283
284static bool trans_rol(DisasContext *ctx, arg_rol *a)
285{
286    REQUIRE_EXT(ctx, RVB);
287    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
288}
289
290static bool trans_grev(DisasContext *ctx, arg_grev *a)
291{
292    REQUIRE_EXT(ctx, RVB);
293    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
294}
295
296static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
297{
298    if (shamt == TARGET_LONG_BITS - 8) {
299        /* rev8, byte swaps */
300        tcg_gen_bswap_tl(dest, src);
301    } else {
302        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
303    }
304}
305
306static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
307{
308    REQUIRE_EXT(ctx, RVB);
309    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
310}
311
312static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
313{
314    REQUIRE_EXT(ctx, RVB);
315    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
316}
317
318static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
319{
320    REQUIRE_EXT(ctx, RVB);
321    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
322}
323
324#define GEN_SHADD(SHAMT)                                       \
325static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
326{                                                              \
327    TCGv t = tcg_temp_new();                                   \
328                                                               \
329    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
330    tcg_gen_add_tl(ret, t, arg2);                              \
331                                                               \
332    tcg_temp_free(t);                                          \
333}
334
335GEN_SHADD(1)
336GEN_SHADD(2)
337GEN_SHADD(3)
338
339#define GEN_TRANS_SHADD(SHAMT)                                             \
340static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
341{                                                                          \
342    REQUIRE_EXT(ctx, RVB);                                                 \
343    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
344}
345
346GEN_TRANS_SHADD(1)
347GEN_TRANS_SHADD(2)
348GEN_TRANS_SHADD(3)
349
350static void gen_clzw(TCGv ret, TCGv arg1)
351{
352    tcg_gen_clzi_tl(ret, ret, 64);
353    tcg_gen_subi_tl(ret, ret, 32);
354}
355
356static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
357{
358    REQUIRE_64BIT(ctx);
359    REQUIRE_EXT(ctx, RVB);
360    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
361}
362
363static void gen_ctzw(TCGv ret, TCGv arg1)
364{
365    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
366    tcg_gen_ctzi_tl(ret, ret, 64);
367}
368
369static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
370{
371    REQUIRE_64BIT(ctx);
372    REQUIRE_EXT(ctx, RVB);
373    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
374}
375
376static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
377{
378    REQUIRE_64BIT(ctx);
379    REQUIRE_EXT(ctx, RVB);
380    ctx->w = true;
381    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
382}
383
384static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
385{
386    TCGv t = tcg_temp_new();
387    tcg_gen_ext16s_tl(t, arg2);
388    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
389    tcg_temp_free(t);
390}
391
392static bool trans_packw(DisasContext *ctx, arg_packw *a)
393{
394    REQUIRE_64BIT(ctx);
395    REQUIRE_EXT(ctx, RVB);
396    return gen_arith(ctx, a, EXT_NONE, gen_packw);
397}
398
399static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
400{
401    TCGv t = tcg_temp_new();
402    tcg_gen_shri_tl(t, arg1, 16);
403    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
404    tcg_gen_ext32s_tl(ret, ret);
405    tcg_temp_free(t);
406}
407
408static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
409{
410    REQUIRE_64BIT(ctx);
411    REQUIRE_EXT(ctx, RVB);
412    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
413}
414
415static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
416{
417    REQUIRE_64BIT(ctx);
418    REQUIRE_EXT(ctx, RVB);
419    ctx->w = true;
420    return gen_shift(ctx, a, EXT_NONE, gen_bset);
421}
422
423static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
424{
425    REQUIRE_64BIT(ctx);
426    REQUIRE_EXT(ctx, RVB);
427    ctx->w = true;
428    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
429}
430
431static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
432{
433    REQUIRE_64BIT(ctx);
434    REQUIRE_EXT(ctx, RVB);
435    ctx->w = true;
436    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
437}
438
439static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
440{
441    REQUIRE_64BIT(ctx);
442    REQUIRE_EXT(ctx, RVB);
443    ctx->w = true;
444    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
445}
446
447static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
448{
449    REQUIRE_64BIT(ctx);
450    REQUIRE_EXT(ctx, RVB);
451    ctx->w = true;
452    return gen_shift(ctx, a, EXT_NONE, gen_binv);
453}
454
455static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
456{
457    REQUIRE_64BIT(ctx);
458    REQUIRE_EXT(ctx, RVB);
459    ctx->w = true;
460    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
461}
462
463static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
464{
465    REQUIRE_64BIT(ctx);
466    REQUIRE_EXT(ctx, RVB);
467    ctx->w = true;
468    return gen_shift(ctx, a, EXT_NONE, gen_bext);
469}
470
471static bool trans_slow(DisasContext *ctx, arg_slow *a)
472{
473    REQUIRE_64BIT(ctx);
474    REQUIRE_EXT(ctx, RVB);
475    ctx->w = true;
476    return gen_shift(ctx, a, EXT_NONE, gen_slo);
477}
478
479static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
480{
481    REQUIRE_64BIT(ctx);
482    REQUIRE_EXT(ctx, RVB);
483    ctx->w = true;
484    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
485}
486
487static bool trans_srow(DisasContext *ctx, arg_srow *a)
488{
489    REQUIRE_64BIT(ctx);
490    REQUIRE_EXT(ctx, RVB);
491    ctx->w = true;
492    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
493}
494
495static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
496{
497    REQUIRE_64BIT(ctx);
498    REQUIRE_EXT(ctx, RVB);
499    ctx->w = true;
500    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
501}
502
503static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
504{
505    TCGv_i32 t1 = tcg_temp_new_i32();
506    TCGv_i32 t2 = tcg_temp_new_i32();
507
508    /* truncate to 32-bits */
509    tcg_gen_trunc_tl_i32(t1, arg1);
510    tcg_gen_trunc_tl_i32(t2, arg2);
511
512    tcg_gen_rotr_i32(t1, t1, t2);
513
514    /* sign-extend 64-bits */
515    tcg_gen_ext_i32_tl(ret, t1);
516
517    tcg_temp_free_i32(t1);
518    tcg_temp_free_i32(t2);
519}
520
521static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
522{
523    REQUIRE_64BIT(ctx);
524    REQUIRE_EXT(ctx, RVB);
525    ctx->w = true;
526    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
527}
528
529static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
530{
531    REQUIRE_64BIT(ctx);
532    REQUIRE_EXT(ctx, RVB);
533    ctx->w = true;
534    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
535}
536
537static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
538{
539    TCGv_i32 t1 = tcg_temp_new_i32();
540    TCGv_i32 t2 = tcg_temp_new_i32();
541
542    /* truncate to 32-bits */
543    tcg_gen_trunc_tl_i32(t1, arg1);
544    tcg_gen_trunc_tl_i32(t2, arg2);
545
546    tcg_gen_rotl_i32(t1, t1, t2);
547
548    /* sign-extend 64-bits */
549    tcg_gen_ext_i32_tl(ret, t1);
550
551    tcg_temp_free_i32(t1);
552    tcg_temp_free_i32(t2);
553}
554
555static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
556{
557    REQUIRE_64BIT(ctx);
558    REQUIRE_EXT(ctx, RVB);
559    ctx->w = true;
560    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
561}
562
563static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
564{
565    REQUIRE_64BIT(ctx);
566    REQUIRE_EXT(ctx, RVB);
567    ctx->w = true;
568    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
569}
570
571static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
572{
573    REQUIRE_64BIT(ctx);
574    REQUIRE_EXT(ctx, RVB);
575    ctx->w = true;
576    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
577}
578
579static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
580{
581    REQUIRE_64BIT(ctx);
582    REQUIRE_EXT(ctx, RVB);
583    ctx->w = true;
584    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
585}
586
587static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
588{
589    REQUIRE_64BIT(ctx);
590    REQUIRE_EXT(ctx, RVB);
591    ctx->w = true;
592    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
593}
594
595#define GEN_SHADD_UW(SHAMT)                                       \
596static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
597{                                                                 \
598    TCGv t = tcg_temp_new();                                      \
599                                                                  \
600    tcg_gen_ext32u_tl(t, arg1);                                   \
601                                                                  \
602    tcg_gen_shli_tl(t, t, SHAMT);                                 \
603    tcg_gen_add_tl(ret, t, arg2);                                 \
604                                                                  \
605    tcg_temp_free(t);                                             \
606}
607
608GEN_SHADD_UW(1)
609GEN_SHADD_UW(2)
610GEN_SHADD_UW(3)
611
612#define GEN_TRANS_SHADD_UW(SHAMT)                             \
613static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
614                                    arg_sh##SHAMT##add_uw *a) \
615{                                                             \
616    REQUIRE_64BIT(ctx);                                       \
617    REQUIRE_EXT(ctx, RVB);                                    \
618    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
619}
620
621GEN_TRANS_SHADD_UW(1)
622GEN_TRANS_SHADD_UW(2)
623GEN_TRANS_SHADD_UW(3)
624
625static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
626{
627    tcg_gen_ext32u_tl(arg1, arg1);
628    tcg_gen_add_tl(ret, arg1, arg2);
629}
630
631static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
632{
633    REQUIRE_64BIT(ctx);
634    REQUIRE_EXT(ctx, RVB);
635    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
636}
637
638static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
639{
640    REQUIRE_64BIT(ctx);
641    REQUIRE_EXT(ctx, RVB);
642
643    TCGv source1 = tcg_temp_new();
644    gen_get_gpr(ctx, source1, a->rs1);
645
646    if (a->shamt < 32) {
647        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
648    } else {
649        tcg_gen_shli_tl(source1, source1, a->shamt);
650    }
651
652    gen_set_gpr(ctx, a->rd, source1);
653    tcg_temp_free(source1);
654    return true;
655}
656