1/*
2 * RISC-V translation routines for the Zb[abcs] Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27#define REQUIRE_ZBB(ctx) do {                    \
28    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
29        return false;                            \
30    }                                            \
31} while (0)
32
33#define REQUIRE_ZBC(ctx) do {                    \
34    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
35        return false;                            \
36    }                                            \
37} while (0)
38
39#define REQUIRE_ZBS(ctx) do {                    \
40    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
41        return false;                            \
42    }                                            \
43} while (0)
44
45static void gen_clz(TCGv ret, TCGv arg1)
46{
47    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
48}
49
50static bool trans_clz(DisasContext *ctx, arg_clz *a)
51{
52    REQUIRE_ZBB(ctx);
53    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
54}
55
56static void gen_ctz(TCGv ret, TCGv arg1)
57{
58    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
59}
60
61static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
62{
63    REQUIRE_ZBB(ctx);
64    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
65}
66
67static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
68{
69    REQUIRE_ZBB(ctx);
70    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
71}
72
73static bool trans_andn(DisasContext *ctx, arg_andn *a)
74{
75    REQUIRE_ZBB(ctx);
76    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
77}
78
79static bool trans_orn(DisasContext *ctx, arg_orn *a)
80{
81    REQUIRE_ZBB(ctx);
82    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
83}
84
85static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
86{
87    REQUIRE_ZBB(ctx);
88    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
89}
90
91static bool trans_min(DisasContext *ctx, arg_min *a)
92{
93    REQUIRE_ZBB(ctx);
94    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
95}
96
97static bool trans_max(DisasContext *ctx, arg_max *a)
98{
99    REQUIRE_ZBB(ctx);
100    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
101}
102
103static bool trans_minu(DisasContext *ctx, arg_minu *a)
104{
105    REQUIRE_ZBB(ctx);
106    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
107}
108
109static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
110{
111    REQUIRE_ZBB(ctx);
112    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
113}
114
115static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
116{
117    REQUIRE_ZBB(ctx);
118    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
119}
120
121static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
122{
123    REQUIRE_ZBB(ctx);
124    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
125}
126
127static void gen_sbop_mask(TCGv ret, TCGv shamt)
128{
129    tcg_gen_movi_tl(ret, 1);
130    tcg_gen_shl_tl(ret, ret, shamt);
131}
132
133static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
134{
135    TCGv t = tcg_temp_new();
136
137    gen_sbop_mask(t, shamt);
138    tcg_gen_or_tl(ret, arg1, t);
139
140    tcg_temp_free(t);
141}
142
143static bool trans_bset(DisasContext *ctx, arg_bset *a)
144{
145    REQUIRE_ZBS(ctx);
146    return gen_shift(ctx, a, EXT_NONE, gen_bset);
147}
148
149static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
150{
151    REQUIRE_ZBS(ctx);
152    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
153}
154
155static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
156{
157    TCGv t = tcg_temp_new();
158
159    gen_sbop_mask(t, shamt);
160    tcg_gen_andc_tl(ret, arg1, t);
161
162    tcg_temp_free(t);
163}
164
165static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
166{
167    REQUIRE_ZBS(ctx);
168    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
169}
170
171static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
172{
173    REQUIRE_ZBS(ctx);
174    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
175}
176
177static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
178{
179    TCGv t = tcg_temp_new();
180
181    gen_sbop_mask(t, shamt);
182    tcg_gen_xor_tl(ret, arg1, t);
183
184    tcg_temp_free(t);
185}
186
187static bool trans_binv(DisasContext *ctx, arg_binv *a)
188{
189    REQUIRE_ZBS(ctx);
190    return gen_shift(ctx, a, EXT_NONE, gen_binv);
191}
192
193static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
194{
195    REQUIRE_ZBS(ctx);
196    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
197}
198
199static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
200{
201    tcg_gen_shr_tl(ret, arg1, shamt);
202    tcg_gen_andi_tl(ret, ret, 1);
203}
204
205static bool trans_bext(DisasContext *ctx, arg_bext *a)
206{
207    REQUIRE_ZBS(ctx);
208    return gen_shift(ctx, a, EXT_NONE, gen_bext);
209}
210
211static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
212{
213    REQUIRE_ZBS(ctx);
214    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
215}
216
217static bool trans_ror(DisasContext *ctx, arg_ror *a)
218{
219    REQUIRE_ZBB(ctx);
220    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
221}
222
223static bool trans_rori(DisasContext *ctx, arg_rori *a)
224{
225    REQUIRE_ZBB(ctx);
226    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
227}
228
229static bool trans_rol(DisasContext *ctx, arg_rol *a)
230{
231    REQUIRE_ZBB(ctx);
232    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
233}
234
235static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
236{
237    REQUIRE_32BIT(ctx);
238    REQUIRE_ZBB(ctx);
239    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
240}
241
242static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
243{
244    REQUIRE_64BIT(ctx);
245    REQUIRE_ZBB(ctx);
246    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
247}
248
249static void gen_orc_b(TCGv ret, TCGv source1)
250{
251    TCGv  tmp = tcg_temp_new();
252    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
253
254    /* Set msb in each byte if the byte was non-zero. */
255    tcg_gen_and_tl(tmp, source1, low7);
256    tcg_gen_add_tl(tmp, tmp, low7);
257    tcg_gen_or_tl(tmp, tmp, source1);
258
259    /* Extract the msb to the lsb in each byte */
260    tcg_gen_andc_tl(tmp, tmp, low7);
261    tcg_gen_shri_tl(tmp, tmp, 7);
262
263    /* Replicate the lsb of each byte across the byte. */
264    tcg_gen_muli_tl(ret, tmp, 0xff);
265
266    tcg_temp_free(tmp);
267}
268
269static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
270{
271    REQUIRE_ZBB(ctx);
272    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
273}
274
275#define GEN_SHADD(SHAMT)                                       \
276static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
277{                                                              \
278    TCGv t = tcg_temp_new();                                   \
279                                                               \
280    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
281    tcg_gen_add_tl(ret, t, arg2);                              \
282                                                               \
283    tcg_temp_free(t);                                          \
284}
285
286GEN_SHADD(1)
287GEN_SHADD(2)
288GEN_SHADD(3)
289
290#define GEN_TRANS_SHADD(SHAMT)                                             \
291static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
292{                                                                          \
293    REQUIRE_ZBA(ctx);                                                      \
294    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
295}
296
297GEN_TRANS_SHADD(1)
298GEN_TRANS_SHADD(2)
299GEN_TRANS_SHADD(3)
300
301static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
302{
303    REQUIRE_32BIT(ctx);
304    REQUIRE_ZBB(ctx);
305    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
306}
307
308static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
309{
310    REQUIRE_64BIT(ctx);
311    REQUIRE_ZBB(ctx);
312    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
313}
314
315static void gen_clzw(TCGv ret, TCGv arg1)
316{
317    TCGv t = tcg_temp_new();
318    tcg_gen_shli_tl(t, arg1, 32);
319    tcg_gen_clzi_tl(ret, t, 32);
320    tcg_temp_free(t);
321}
322
323static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
324{
325    REQUIRE_64BIT(ctx);
326    REQUIRE_ZBB(ctx);
327    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
328}
329
330static void gen_ctzw(TCGv ret, TCGv arg1)
331{
332    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
333    tcg_gen_ctzi_tl(ret, ret, 64);
334}
335
336static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
337{
338    REQUIRE_64BIT(ctx);
339    REQUIRE_ZBB(ctx);
340    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
341}
342
343static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
344{
345    REQUIRE_64BIT(ctx);
346    REQUIRE_ZBB(ctx);
347    ctx->ol = MXL_RV32;
348    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
349}
350
351static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
352{
353    TCGv_i32 t1 = tcg_temp_new_i32();
354    TCGv_i32 t2 = tcg_temp_new_i32();
355
356    /* truncate to 32-bits */
357    tcg_gen_trunc_tl_i32(t1, arg1);
358    tcg_gen_trunc_tl_i32(t2, arg2);
359
360    tcg_gen_rotr_i32(t1, t1, t2);
361
362    /* sign-extend 64-bits */
363    tcg_gen_ext_i32_tl(ret, t1);
364
365    tcg_temp_free_i32(t1);
366    tcg_temp_free_i32(t2);
367}
368
369static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
370{
371    REQUIRE_64BIT(ctx);
372    REQUIRE_ZBB(ctx);
373    ctx->ol = MXL_RV32;
374    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
375}
376
377static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
378{
379    REQUIRE_64BIT(ctx);
380    REQUIRE_ZBB(ctx);
381    ctx->ol = MXL_RV32;
382    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
383}
384
385static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
386{
387    TCGv_i32 t1 = tcg_temp_new_i32();
388    TCGv_i32 t2 = tcg_temp_new_i32();
389
390    /* truncate to 32-bits */
391    tcg_gen_trunc_tl_i32(t1, arg1);
392    tcg_gen_trunc_tl_i32(t2, arg2);
393
394    tcg_gen_rotl_i32(t1, t1, t2);
395
396    /* sign-extend 64-bits */
397    tcg_gen_ext_i32_tl(ret, t1);
398
399    tcg_temp_free_i32(t1);
400    tcg_temp_free_i32(t2);
401}
402
403static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
404{
405    REQUIRE_64BIT(ctx);
406    REQUIRE_ZBB(ctx);
407    ctx->ol = MXL_RV32;
408    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
409}
410
411#define GEN_SHADD_UW(SHAMT)                                       \
412static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
413{                                                                 \
414    TCGv t = tcg_temp_new();                                      \
415                                                                  \
416    tcg_gen_ext32u_tl(t, arg1);                                   \
417                                                                  \
418    tcg_gen_shli_tl(t, t, SHAMT);                                 \
419    tcg_gen_add_tl(ret, t, arg2);                                 \
420                                                                  \
421    tcg_temp_free(t);                                             \
422}
423
424GEN_SHADD_UW(1)
425GEN_SHADD_UW(2)
426GEN_SHADD_UW(3)
427
428#define GEN_TRANS_SHADD_UW(SHAMT)                             \
429static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
430                                    arg_sh##SHAMT##add_uw *a) \
431{                                                             \
432    REQUIRE_64BIT(ctx);                                       \
433    REQUIRE_ZBA(ctx);                                         \
434    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
435}
436
437GEN_TRANS_SHADD_UW(1)
438GEN_TRANS_SHADD_UW(2)
439GEN_TRANS_SHADD_UW(3)
440
441static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
442{
443    TCGv t = tcg_temp_new();
444    tcg_gen_ext32u_tl(t, arg1);
445    tcg_gen_add_tl(ret, t, arg2);
446    tcg_temp_free(t);
447}
448
449static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
450{
451    REQUIRE_64BIT(ctx);
452    REQUIRE_ZBA(ctx);
453    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
454}
455
456static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
457{
458    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
459}
460
461static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
462{
463    REQUIRE_64BIT(ctx);
464    REQUIRE_ZBA(ctx);
465    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
466}
467
468static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
469{
470    REQUIRE_ZBC(ctx);
471    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
472}
473
474static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
475{
476     gen_helper_clmulr(dst, src1, src2);
477     tcg_gen_shri_tl(dst, dst, 1);
478}
479
480static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
481{
482    REQUIRE_ZBC(ctx);
483    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
484}
485
486static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
487{
488    REQUIRE_ZBC(ctx);
489    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
490}
491