1/*
2 * RISC-V translation routines for the RVB draft and Zba Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_ZBA(ctx) do {                    \
22    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
23        return false;                            \
24    }                                            \
25} while (0)
26
27static void gen_clz(TCGv ret, TCGv arg1)
28{
29    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
30}
31
32static bool trans_clz(DisasContext *ctx, arg_clz *a)
33{
34    REQUIRE_EXT(ctx, RVB);
35    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
36}
37
38static void gen_ctz(TCGv ret, TCGv arg1)
39{
40    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
41}
42
43static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
44{
45    REQUIRE_EXT(ctx, RVB);
46    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
47}
48
49static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
50{
51    REQUIRE_EXT(ctx, RVB);
52    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
53}
54
55static bool trans_andn(DisasContext *ctx, arg_andn *a)
56{
57    REQUIRE_EXT(ctx, RVB);
58    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
59}
60
61static bool trans_orn(DisasContext *ctx, arg_orn *a)
62{
63    REQUIRE_EXT(ctx, RVB);
64    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
65}
66
67static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
68{
69    REQUIRE_EXT(ctx, RVB);
70    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
71}
72
73static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
74{
75    tcg_gen_deposit_tl(ret, arg1, arg2,
76                       TARGET_LONG_BITS / 2,
77                       TARGET_LONG_BITS / 2);
78}
79
80static bool trans_pack(DisasContext *ctx, arg_pack *a)
81{
82    REQUIRE_EXT(ctx, RVB);
83    return gen_arith(ctx, a, EXT_NONE, gen_pack);
84}
85
86static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
87{
88    TCGv t = tcg_temp_new();
89    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
90    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
91    tcg_temp_free(t);
92}
93
94static bool trans_packu(DisasContext *ctx, arg_packu *a)
95{
96    REQUIRE_EXT(ctx, RVB);
97    return gen_arith(ctx, a, EXT_NONE, gen_packu);
98}
99
100static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
101{
102    TCGv t = tcg_temp_new();
103    tcg_gen_ext8u_tl(t, arg2);
104    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
105    tcg_temp_free(t);
106}
107
108static bool trans_packh(DisasContext *ctx, arg_packh *a)
109{
110    REQUIRE_EXT(ctx, RVB);
111    return gen_arith(ctx, a, EXT_NONE, gen_packh);
112}
113
114static bool trans_min(DisasContext *ctx, arg_min *a)
115{
116    REQUIRE_EXT(ctx, RVB);
117    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
118}
119
120static bool trans_max(DisasContext *ctx, arg_max *a)
121{
122    REQUIRE_EXT(ctx, RVB);
123    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
124}
125
126static bool trans_minu(DisasContext *ctx, arg_minu *a)
127{
128    REQUIRE_EXT(ctx, RVB);
129    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
130}
131
132static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
133{
134    REQUIRE_EXT(ctx, RVB);
135    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
136}
137
138static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
139{
140    REQUIRE_EXT(ctx, RVB);
141    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
142}
143
144static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
145{
146    REQUIRE_EXT(ctx, RVB);
147    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
148}
149
150static void gen_sbop_mask(TCGv ret, TCGv shamt)
151{
152    tcg_gen_movi_tl(ret, 1);
153    tcg_gen_shl_tl(ret, ret, shamt);
154}
155
156static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
157{
158    TCGv t = tcg_temp_new();
159
160    gen_sbop_mask(t, shamt);
161    tcg_gen_or_tl(ret, arg1, t);
162
163    tcg_temp_free(t);
164}
165
166static bool trans_bset(DisasContext *ctx, arg_bset *a)
167{
168    REQUIRE_EXT(ctx, RVB);
169    return gen_shift(ctx, a, EXT_NONE, gen_bset);
170}
171
172static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
173{
174    REQUIRE_EXT(ctx, RVB);
175    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
176}
177
178static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
179{
180    TCGv t = tcg_temp_new();
181
182    gen_sbop_mask(t, shamt);
183    tcg_gen_andc_tl(ret, arg1, t);
184
185    tcg_temp_free(t);
186}
187
188static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
189{
190    REQUIRE_EXT(ctx, RVB);
191    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
192}
193
194static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
195{
196    REQUIRE_EXT(ctx, RVB);
197    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
198}
199
200static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
201{
202    TCGv t = tcg_temp_new();
203
204    gen_sbop_mask(t, shamt);
205    tcg_gen_xor_tl(ret, arg1, t);
206
207    tcg_temp_free(t);
208}
209
210static bool trans_binv(DisasContext *ctx, arg_binv *a)
211{
212    REQUIRE_EXT(ctx, RVB);
213    return gen_shift(ctx, a, EXT_NONE, gen_binv);
214}
215
216static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
217{
218    REQUIRE_EXT(ctx, RVB);
219    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
220}
221
222static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
223{
224    tcg_gen_shr_tl(ret, arg1, shamt);
225    tcg_gen_andi_tl(ret, ret, 1);
226}
227
228static bool trans_bext(DisasContext *ctx, arg_bext *a)
229{
230    REQUIRE_EXT(ctx, RVB);
231    return gen_shift(ctx, a, EXT_NONE, gen_bext);
232}
233
234static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
235{
236    REQUIRE_EXT(ctx, RVB);
237    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
238}
239
240static bool trans_ror(DisasContext *ctx, arg_ror *a)
241{
242    REQUIRE_EXT(ctx, RVB);
243    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
244}
245
246static bool trans_rori(DisasContext *ctx, arg_rori *a)
247{
248    REQUIRE_EXT(ctx, RVB);
249    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
250}
251
252static bool trans_rol(DisasContext *ctx, arg_rol *a)
253{
254    REQUIRE_EXT(ctx, RVB);
255    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
256}
257
258static bool trans_grev(DisasContext *ctx, arg_grev *a)
259{
260    REQUIRE_EXT(ctx, RVB);
261    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
262}
263
264static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
265{
266    if (shamt == TARGET_LONG_BITS - 8) {
267        /* rev8, byte swaps */
268        tcg_gen_bswap_tl(dest, src);
269    } else {
270        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
271    }
272}
273
274static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
275{
276    REQUIRE_EXT(ctx, RVB);
277    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
278}
279
280static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
281{
282    REQUIRE_EXT(ctx, RVB);
283    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
284}
285
286static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
287{
288    REQUIRE_EXT(ctx, RVB);
289    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
290}
291
292#define GEN_SHADD(SHAMT)                                       \
293static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
294{                                                              \
295    TCGv t = tcg_temp_new();                                   \
296                                                               \
297    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
298    tcg_gen_add_tl(ret, t, arg2);                              \
299                                                               \
300    tcg_temp_free(t);                                          \
301}
302
303GEN_SHADD(1)
304GEN_SHADD(2)
305GEN_SHADD(3)
306
307#define GEN_TRANS_SHADD(SHAMT)                                             \
308static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
309{                                                                          \
310    REQUIRE_ZBA(ctx);                                                      \
311    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
312}
313
314GEN_TRANS_SHADD(1)
315GEN_TRANS_SHADD(2)
316GEN_TRANS_SHADD(3)
317
318static void gen_clzw(TCGv ret, TCGv arg1)
319{
320    TCGv t = tcg_temp_new();
321    tcg_gen_shli_tl(t, arg1, 32);
322    tcg_gen_clzi_tl(ret, t, 32);
323    tcg_temp_free(t);
324}
325
326static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
327{
328    REQUIRE_64BIT(ctx);
329    REQUIRE_EXT(ctx, RVB);
330    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
331}
332
333static void gen_ctzw(TCGv ret, TCGv arg1)
334{
335    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
336    tcg_gen_ctzi_tl(ret, ret, 64);
337}
338
339static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
340{
341    REQUIRE_64BIT(ctx);
342    REQUIRE_EXT(ctx, RVB);
343    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
344}
345
346static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
347{
348    REQUIRE_64BIT(ctx);
349    REQUIRE_EXT(ctx, RVB);
350    ctx->w = true;
351    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
352}
353
354static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
355{
356    TCGv t = tcg_temp_new();
357    tcg_gen_ext16s_tl(t, arg2);
358    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
359    tcg_temp_free(t);
360}
361
362static bool trans_packw(DisasContext *ctx, arg_packw *a)
363{
364    REQUIRE_64BIT(ctx);
365    REQUIRE_EXT(ctx, RVB);
366    return gen_arith(ctx, a, EXT_NONE, gen_packw);
367}
368
369static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
370{
371    TCGv t = tcg_temp_new();
372    tcg_gen_shri_tl(t, arg1, 16);
373    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
374    tcg_gen_ext32s_tl(ret, ret);
375    tcg_temp_free(t);
376}
377
378static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
379{
380    REQUIRE_64BIT(ctx);
381    REQUIRE_EXT(ctx, RVB);
382    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
383}
384
385static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
386{
387    TCGv_i32 t1 = tcg_temp_new_i32();
388    TCGv_i32 t2 = tcg_temp_new_i32();
389
390    /* truncate to 32-bits */
391    tcg_gen_trunc_tl_i32(t1, arg1);
392    tcg_gen_trunc_tl_i32(t2, arg2);
393
394    tcg_gen_rotr_i32(t1, t1, t2);
395
396    /* sign-extend 64-bits */
397    tcg_gen_ext_i32_tl(ret, t1);
398
399    tcg_temp_free_i32(t1);
400    tcg_temp_free_i32(t2);
401}
402
403static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
404{
405    REQUIRE_64BIT(ctx);
406    REQUIRE_EXT(ctx, RVB);
407    ctx->w = true;
408    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
409}
410
411static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
412{
413    REQUIRE_64BIT(ctx);
414    REQUIRE_EXT(ctx, RVB);
415    ctx->w = true;
416    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
417}
418
419static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
420{
421    TCGv_i32 t1 = tcg_temp_new_i32();
422    TCGv_i32 t2 = tcg_temp_new_i32();
423
424    /* truncate to 32-bits */
425    tcg_gen_trunc_tl_i32(t1, arg1);
426    tcg_gen_trunc_tl_i32(t2, arg2);
427
428    tcg_gen_rotl_i32(t1, t1, t2);
429
430    /* sign-extend 64-bits */
431    tcg_gen_ext_i32_tl(ret, t1);
432
433    tcg_temp_free_i32(t1);
434    tcg_temp_free_i32(t2);
435}
436
437static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
438{
439    REQUIRE_64BIT(ctx);
440    REQUIRE_EXT(ctx, RVB);
441    ctx->w = true;
442    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
443}
444
445static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
446{
447    REQUIRE_64BIT(ctx);
448    REQUIRE_EXT(ctx, RVB);
449    ctx->w = true;
450    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
451}
452
453static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
454{
455    REQUIRE_64BIT(ctx);
456    REQUIRE_EXT(ctx, RVB);
457    ctx->w = true;
458    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
459}
460
461static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
462{
463    REQUIRE_64BIT(ctx);
464    REQUIRE_EXT(ctx, RVB);
465    ctx->w = true;
466    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
467}
468
469static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
470{
471    REQUIRE_64BIT(ctx);
472    REQUIRE_EXT(ctx, RVB);
473    ctx->w = true;
474    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
475}
476
477#define GEN_SHADD_UW(SHAMT)                                       \
478static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
479{                                                                 \
480    TCGv t = tcg_temp_new();                                      \
481                                                                  \
482    tcg_gen_ext32u_tl(t, arg1);                                   \
483                                                                  \
484    tcg_gen_shli_tl(t, t, SHAMT);                                 \
485    tcg_gen_add_tl(ret, t, arg2);                                 \
486                                                                  \
487    tcg_temp_free(t);                                             \
488}
489
490GEN_SHADD_UW(1)
491GEN_SHADD_UW(2)
492GEN_SHADD_UW(3)
493
494#define GEN_TRANS_SHADD_UW(SHAMT)                             \
495static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
496                                    arg_sh##SHAMT##add_uw *a) \
497{                                                             \
498    REQUIRE_64BIT(ctx);                                       \
499    REQUIRE_ZBA(ctx);                                         \
500    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
501}
502
503GEN_TRANS_SHADD_UW(1)
504GEN_TRANS_SHADD_UW(2)
505GEN_TRANS_SHADD_UW(3)
506
507static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
508{
509    TCGv t = tcg_temp_new();
510    tcg_gen_ext32u_tl(t, arg1);
511    tcg_gen_add_tl(ret, t, arg2);
512    tcg_temp_free(t);
513}
514
515static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
516{
517    REQUIRE_64BIT(ctx);
518    REQUIRE_ZBA(ctx);
519    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
520}
521
522static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
523{
524    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
525}
526
527static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
528{
529    REQUIRE_64BIT(ctx);
530    REQUIRE_ZBA(ctx);
531    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
532}
533