1/*
2 * RISC-V translation routines for the RVB Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21static void gen_clz(TCGv ret, TCGv arg1)
22{
23    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
24}
25
26static bool trans_clz(DisasContext *ctx, arg_clz *a)
27{
28    REQUIRE_EXT(ctx, RVB);
29    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
30}
31
32static void gen_ctz(TCGv ret, TCGv arg1)
33{
34    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
35}
36
37static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
38{
39    REQUIRE_EXT(ctx, RVB);
40    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
41}
42
43static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
44{
45    REQUIRE_EXT(ctx, RVB);
46    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
47}
48
49static bool trans_andn(DisasContext *ctx, arg_andn *a)
50{
51    REQUIRE_EXT(ctx, RVB);
52    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
53}
54
55static bool trans_orn(DisasContext *ctx, arg_orn *a)
56{
57    REQUIRE_EXT(ctx, RVB);
58    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
59}
60
61static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
62{
63    REQUIRE_EXT(ctx, RVB);
64    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
65}
66
67static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
68{
69    tcg_gen_deposit_tl(ret, arg1, arg2,
70                       TARGET_LONG_BITS / 2,
71                       TARGET_LONG_BITS / 2);
72}
73
74static bool trans_pack(DisasContext *ctx, arg_pack *a)
75{
76    REQUIRE_EXT(ctx, RVB);
77    return gen_arith(ctx, a, EXT_NONE, gen_pack);
78}
79
80static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
81{
82    TCGv t = tcg_temp_new();
83    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
84    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
85    tcg_temp_free(t);
86}
87
88static bool trans_packu(DisasContext *ctx, arg_packu *a)
89{
90    REQUIRE_EXT(ctx, RVB);
91    return gen_arith(ctx, a, EXT_NONE, gen_packu);
92}
93
94static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
95{
96    TCGv t = tcg_temp_new();
97    tcg_gen_ext8u_tl(t, arg2);
98    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
99    tcg_temp_free(t);
100}
101
102static bool trans_packh(DisasContext *ctx, arg_packh *a)
103{
104    REQUIRE_EXT(ctx, RVB);
105    return gen_arith(ctx, a, EXT_NONE, gen_packh);
106}
107
108static bool trans_min(DisasContext *ctx, arg_min *a)
109{
110    REQUIRE_EXT(ctx, RVB);
111    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
112}
113
114static bool trans_max(DisasContext *ctx, arg_max *a)
115{
116    REQUIRE_EXT(ctx, RVB);
117    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
118}
119
120static bool trans_minu(DisasContext *ctx, arg_minu *a)
121{
122    REQUIRE_EXT(ctx, RVB);
123    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
124}
125
126static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
127{
128    REQUIRE_EXT(ctx, RVB);
129    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
130}
131
132static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
133{
134    REQUIRE_EXT(ctx, RVB);
135    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
136}
137
138static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
139{
140    REQUIRE_EXT(ctx, RVB);
141    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
142}
143
144static void gen_sbop_mask(TCGv ret, TCGv shamt)
145{
146    tcg_gen_movi_tl(ret, 1);
147    tcg_gen_shl_tl(ret, ret, shamt);
148}
149
150static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
151{
152    TCGv t = tcg_temp_new();
153
154    gen_sbop_mask(t, shamt);
155    tcg_gen_or_tl(ret, arg1, t);
156
157    tcg_temp_free(t);
158}
159
160static bool trans_bset(DisasContext *ctx, arg_bset *a)
161{
162    REQUIRE_EXT(ctx, RVB);
163    return gen_shift(ctx, a, gen_bset);
164}
165
166static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
167{
168    REQUIRE_EXT(ctx, RVB);
169    return gen_shifti(ctx, a, gen_bset);
170}
171
172static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
173{
174    TCGv t = tcg_temp_new();
175
176    gen_sbop_mask(t, shamt);
177    tcg_gen_andc_tl(ret, arg1, t);
178
179    tcg_temp_free(t);
180}
181
182static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
183{
184    REQUIRE_EXT(ctx, RVB);
185    return gen_shift(ctx, a, gen_bclr);
186}
187
188static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
189{
190    REQUIRE_EXT(ctx, RVB);
191    return gen_shifti(ctx, a, gen_bclr);
192}
193
194static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
195{
196    TCGv t = tcg_temp_new();
197
198    gen_sbop_mask(t, shamt);
199    tcg_gen_xor_tl(ret, arg1, t);
200
201    tcg_temp_free(t);
202}
203
204static bool trans_binv(DisasContext *ctx, arg_binv *a)
205{
206    REQUIRE_EXT(ctx, RVB);
207    return gen_shift(ctx, a, gen_binv);
208}
209
210static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
211{
212    REQUIRE_EXT(ctx, RVB);
213    return gen_shifti(ctx, a, gen_binv);
214}
215
216static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
217{
218    tcg_gen_shr_tl(ret, arg1, shamt);
219    tcg_gen_andi_tl(ret, ret, 1);
220}
221
222static bool trans_bext(DisasContext *ctx, arg_bext *a)
223{
224    REQUIRE_EXT(ctx, RVB);
225    return gen_shift(ctx, a, gen_bext);
226}
227
228static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
229{
230    REQUIRE_EXT(ctx, RVB);
231    return gen_shifti(ctx, a, gen_bext);
232}
233
234static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
235{
236    tcg_gen_not_tl(ret, arg1);
237    tcg_gen_shl_tl(ret, ret, arg2);
238    tcg_gen_not_tl(ret, ret);
239}
240
241static bool trans_slo(DisasContext *ctx, arg_slo *a)
242{
243    REQUIRE_EXT(ctx, RVB);
244    return gen_shift(ctx, a, gen_slo);
245}
246
247static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
248{
249    REQUIRE_EXT(ctx, RVB);
250    return gen_shifti(ctx, a, gen_slo);
251}
252
253static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
254{
255    tcg_gen_not_tl(ret, arg1);
256    tcg_gen_shr_tl(ret, ret, arg2);
257    tcg_gen_not_tl(ret, ret);
258}
259
260static bool trans_sro(DisasContext *ctx, arg_sro *a)
261{
262    REQUIRE_EXT(ctx, RVB);
263    return gen_shift(ctx, a, gen_sro);
264}
265
266static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
267{
268    REQUIRE_EXT(ctx, RVB);
269    return gen_shifti(ctx, a, gen_sro);
270}
271
272static bool trans_ror(DisasContext *ctx, arg_ror *a)
273{
274    REQUIRE_EXT(ctx, RVB);
275    return gen_shift(ctx, a, tcg_gen_rotr_tl);
276}
277
278static bool trans_rori(DisasContext *ctx, arg_rori *a)
279{
280    REQUIRE_EXT(ctx, RVB);
281    return gen_shifti(ctx, a, tcg_gen_rotr_tl);
282}
283
284static bool trans_rol(DisasContext *ctx, arg_rol *a)
285{
286    REQUIRE_EXT(ctx, RVB);
287    return gen_shift(ctx, a, tcg_gen_rotl_tl);
288}
289
290static bool trans_grev(DisasContext *ctx, arg_grev *a)
291{
292    REQUIRE_EXT(ctx, RVB);
293    return gen_shift(ctx, a, gen_helper_grev);
294}
295
296static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
297{
298    TCGv source1 = tcg_temp_new();
299    TCGv source2;
300
301    gen_get_gpr(ctx, source1, a->rs1);
302
303    if (a->shamt == (TARGET_LONG_BITS - 8)) {
304        /* rev8, byte swaps */
305        tcg_gen_bswap_tl(source1, source1);
306    } else {
307        source2 = tcg_temp_new();
308        tcg_gen_movi_tl(source2, a->shamt);
309        gen_helper_grev(source1, source1, source2);
310        tcg_temp_free(source2);
311    }
312
313    gen_set_gpr(ctx, a->rd, source1);
314    tcg_temp_free(source1);
315    return true;
316}
317
318static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
319{
320    REQUIRE_EXT(ctx, RVB);
321
322    if (a->shamt >= TARGET_LONG_BITS) {
323        return false;
324    }
325
326    return gen_grevi(ctx, a);
327}
328
329static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
330{
331    REQUIRE_EXT(ctx, RVB);
332    return gen_shift(ctx, a, gen_helper_gorc);
333}
334
335static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
336{
337    REQUIRE_EXT(ctx, RVB);
338    return gen_shifti(ctx, a, gen_helper_gorc);
339}
340
341#define GEN_SHADD(SHAMT)                                       \
342static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
343{                                                              \
344    TCGv t = tcg_temp_new();                                   \
345                                                               \
346    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
347    tcg_gen_add_tl(ret, t, arg2);                              \
348                                                               \
349    tcg_temp_free(t);                                          \
350}
351
352GEN_SHADD(1)
353GEN_SHADD(2)
354GEN_SHADD(3)
355
356#define GEN_TRANS_SHADD(SHAMT)                                             \
357static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
358{                                                                          \
359    REQUIRE_EXT(ctx, RVB);                                                 \
360    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
361}
362
363GEN_TRANS_SHADD(1)
364GEN_TRANS_SHADD(2)
365GEN_TRANS_SHADD(3)
366
367static void gen_clzw(TCGv ret, TCGv arg1)
368{
369    tcg_gen_clzi_tl(ret, ret, 64);
370    tcg_gen_subi_tl(ret, ret, 32);
371}
372
373static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
374{
375    REQUIRE_64BIT(ctx);
376    REQUIRE_EXT(ctx, RVB);
377    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
378}
379
380static void gen_ctzw(TCGv ret, TCGv arg1)
381{
382    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
383    tcg_gen_ctzi_tl(ret, ret, 64);
384}
385
386static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
387{
388    REQUIRE_64BIT(ctx);
389    REQUIRE_EXT(ctx, RVB);
390    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
391}
392
393static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
394{
395    REQUIRE_64BIT(ctx);
396    REQUIRE_EXT(ctx, RVB);
397    ctx->w = true;
398    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
399}
400
401static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
402{
403    TCGv t = tcg_temp_new();
404    tcg_gen_ext16s_tl(t, arg2);
405    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
406    tcg_temp_free(t);
407}
408
409static bool trans_packw(DisasContext *ctx, arg_packw *a)
410{
411    REQUIRE_64BIT(ctx);
412    REQUIRE_EXT(ctx, RVB);
413    return gen_arith(ctx, a, EXT_NONE, gen_packw);
414}
415
416static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
417{
418    TCGv t = tcg_temp_new();
419    tcg_gen_shri_tl(t, arg1, 16);
420    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
421    tcg_gen_ext32s_tl(ret, ret);
422    tcg_temp_free(t);
423}
424
425static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
426{
427    REQUIRE_64BIT(ctx);
428    REQUIRE_EXT(ctx, RVB);
429    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
430}
431
432static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
433{
434    REQUIRE_64BIT(ctx);
435    REQUIRE_EXT(ctx, RVB);
436    return gen_shiftw(ctx, a, gen_bset);
437}
438
439static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
440{
441    REQUIRE_64BIT(ctx);
442    REQUIRE_EXT(ctx, RVB);
443    return gen_shiftiw(ctx, a, gen_bset);
444}
445
446static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
447{
448    REQUIRE_64BIT(ctx);
449    REQUIRE_EXT(ctx, RVB);
450    return gen_shiftw(ctx, a, gen_bclr);
451}
452
453static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
454{
455    REQUIRE_64BIT(ctx);
456    REQUIRE_EXT(ctx, RVB);
457    return gen_shiftiw(ctx, a, gen_bclr);
458}
459
460static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
461{
462    REQUIRE_64BIT(ctx);
463    REQUIRE_EXT(ctx, RVB);
464    return gen_shiftw(ctx, a, gen_binv);
465}
466
467static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
468{
469    REQUIRE_64BIT(ctx);
470    REQUIRE_EXT(ctx, RVB);
471    return gen_shiftiw(ctx, a, gen_binv);
472}
473
474static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
475{
476    REQUIRE_64BIT(ctx);
477    REQUIRE_EXT(ctx, RVB);
478    return gen_shiftw(ctx, a, gen_bext);
479}
480
481static bool trans_slow(DisasContext *ctx, arg_slow *a)
482{
483    REQUIRE_64BIT(ctx);
484    REQUIRE_EXT(ctx, RVB);
485    return gen_shiftw(ctx, a, gen_slo);
486}
487
488static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
489{
490    REQUIRE_64BIT(ctx);
491    REQUIRE_EXT(ctx, RVB);
492    return gen_shiftiw(ctx, a, gen_slo);
493}
494
495static bool trans_srow(DisasContext *ctx, arg_srow *a)
496{
497    REQUIRE_64BIT(ctx);
498    REQUIRE_EXT(ctx, RVB);
499    return gen_shiftw(ctx, a, gen_sro);
500}
501
502static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
503{
504    REQUIRE_64BIT(ctx);
505    REQUIRE_EXT(ctx, RVB);
506    return gen_shiftiw(ctx, a, gen_sro);
507}
508
509static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
510{
511    TCGv_i32 t1 = tcg_temp_new_i32();
512    TCGv_i32 t2 = tcg_temp_new_i32();
513
514    /* truncate to 32-bits */
515    tcg_gen_trunc_tl_i32(t1, arg1);
516    tcg_gen_trunc_tl_i32(t2, arg2);
517
518    tcg_gen_rotr_i32(t1, t1, t2);
519
520    /* sign-extend 64-bits */
521    tcg_gen_ext_i32_tl(ret, t1);
522
523    tcg_temp_free_i32(t1);
524    tcg_temp_free_i32(t2);
525}
526
527static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
528{
529    REQUIRE_64BIT(ctx);
530    REQUIRE_EXT(ctx, RVB);
531    return gen_shiftw(ctx, a, gen_rorw);
532}
533
534static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
535{
536    REQUIRE_64BIT(ctx);
537    REQUIRE_EXT(ctx, RVB);
538    return gen_shiftiw(ctx, a, gen_rorw);
539}
540
541static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
542{
543    TCGv_i32 t1 = tcg_temp_new_i32();
544    TCGv_i32 t2 = tcg_temp_new_i32();
545
546    /* truncate to 32-bits */
547    tcg_gen_trunc_tl_i32(t1, arg1);
548    tcg_gen_trunc_tl_i32(t2, arg2);
549
550    tcg_gen_rotl_i32(t1, t1, t2);
551
552    /* sign-extend 64-bits */
553    tcg_gen_ext_i32_tl(ret, t1);
554
555    tcg_temp_free_i32(t1);
556    tcg_temp_free_i32(t2);
557}
558
559static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
560{
561    REQUIRE_64BIT(ctx);
562    REQUIRE_EXT(ctx, RVB);
563    return gen_shiftw(ctx, a, gen_rolw);
564}
565
566static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
567{
568    tcg_gen_ext32u_tl(arg1, arg1);
569    gen_helper_grev(ret, arg1, arg2);
570}
571
572static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
573{
574    REQUIRE_64BIT(ctx);
575    REQUIRE_EXT(ctx, RVB);
576    return gen_shiftw(ctx, a, gen_grevw);
577}
578
579static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
580{
581    REQUIRE_64BIT(ctx);
582    REQUIRE_EXT(ctx, RVB);
583    return gen_shiftiw(ctx, a, gen_grevw);
584}
585
586static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
587{
588    tcg_gen_ext32u_tl(arg1, arg1);
589    gen_helper_gorcw(ret, arg1, arg2);
590}
591
592static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
593{
594    REQUIRE_64BIT(ctx);
595    REQUIRE_EXT(ctx, RVB);
596    return gen_shiftw(ctx, a, gen_gorcw);
597}
598
599static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
600{
601    REQUIRE_64BIT(ctx);
602    REQUIRE_EXT(ctx, RVB);
603    return gen_shiftiw(ctx, a, gen_gorcw);
604}
605
606#define GEN_SHADD_UW(SHAMT)                                       \
607static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
608{                                                                 \
609    TCGv t = tcg_temp_new();                                      \
610                                                                  \
611    tcg_gen_ext32u_tl(t, arg1);                                   \
612                                                                  \
613    tcg_gen_shli_tl(t, t, SHAMT);                                 \
614    tcg_gen_add_tl(ret, t, arg2);                                 \
615                                                                  \
616    tcg_temp_free(t);                                             \
617}
618
619GEN_SHADD_UW(1)
620GEN_SHADD_UW(2)
621GEN_SHADD_UW(3)
622
623#define GEN_TRANS_SHADD_UW(SHAMT)                             \
624static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
625                                    arg_sh##SHAMT##add_uw *a) \
626{                                                             \
627    REQUIRE_64BIT(ctx);                                       \
628    REQUIRE_EXT(ctx, RVB);                                    \
629    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
630}
631
632GEN_TRANS_SHADD_UW(1)
633GEN_TRANS_SHADD_UW(2)
634GEN_TRANS_SHADD_UW(3)
635
636static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
637{
638    tcg_gen_ext32u_tl(arg1, arg1);
639    tcg_gen_add_tl(ret, arg1, arg2);
640}
641
642static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
643{
644    REQUIRE_64BIT(ctx);
645    REQUIRE_EXT(ctx, RVB);
646    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
647}
648
649static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
650{
651    REQUIRE_64BIT(ctx);
652    REQUIRE_EXT(ctx, RVB);
653
654    TCGv source1 = tcg_temp_new();
655    gen_get_gpr(ctx, source1, a->rs1);
656
657    if (a->shamt < 32) {
658        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
659    } else {
660        tcg_gen_shli_tl(source1, source1, a->shamt);
661    }
662
663    gen_set_gpr(ctx, a->rd, source1);
664    tcg_temp_free(source1);
665    return true;
666}
667