1/*
2 * RISC-V translation routines for the RVB Standard Extension.
3 *
4 * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
5 * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21static void gen_clz(TCGv ret, TCGv arg1)
22{
23    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
24}
25
26static bool trans_clz(DisasContext *ctx, arg_clz *a)
27{
28    REQUIRE_EXT(ctx, RVB);
29    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
30}
31
32static void gen_ctz(TCGv ret, TCGv arg1)
33{
34    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
35}
36
37static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
38{
39    REQUIRE_EXT(ctx, RVB);
40    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
41}
42
43static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
44{
45    REQUIRE_EXT(ctx, RVB);
46    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
47}
48
49static bool trans_andn(DisasContext *ctx, arg_andn *a)
50{
51    REQUIRE_EXT(ctx, RVB);
52    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
53}
54
55static bool trans_orn(DisasContext *ctx, arg_orn *a)
56{
57    REQUIRE_EXT(ctx, RVB);
58    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
59}
60
61static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
62{
63    REQUIRE_EXT(ctx, RVB);
64    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
65}
66
67static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
68{
69    tcg_gen_deposit_tl(ret, arg1, arg2,
70                       TARGET_LONG_BITS / 2,
71                       TARGET_LONG_BITS / 2);
72}
73
74static bool trans_pack(DisasContext *ctx, arg_pack *a)
75{
76    REQUIRE_EXT(ctx, RVB);
77    return gen_arith(ctx, a, EXT_NONE, gen_pack);
78}
79
80static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
81{
82    TCGv t = tcg_temp_new();
83    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
84    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
85    tcg_temp_free(t);
86}
87
88static bool trans_packu(DisasContext *ctx, arg_packu *a)
89{
90    REQUIRE_EXT(ctx, RVB);
91    return gen_arith(ctx, a, EXT_NONE, gen_packu);
92}
93
94static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
95{
96    TCGv t = tcg_temp_new();
97    tcg_gen_ext8u_tl(t, arg2);
98    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
99    tcg_temp_free(t);
100}
101
102static bool trans_packh(DisasContext *ctx, arg_packh *a)
103{
104    REQUIRE_EXT(ctx, RVB);
105    return gen_arith(ctx, a, EXT_NONE, gen_packh);
106}
107
108static bool trans_min(DisasContext *ctx, arg_min *a)
109{
110    REQUIRE_EXT(ctx, RVB);
111    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
112}
113
114static bool trans_max(DisasContext *ctx, arg_max *a)
115{
116    REQUIRE_EXT(ctx, RVB);
117    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
118}
119
120static bool trans_minu(DisasContext *ctx, arg_minu *a)
121{
122    REQUIRE_EXT(ctx, RVB);
123    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
124}
125
126static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
127{
128    REQUIRE_EXT(ctx, RVB);
129    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
130}
131
132static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
133{
134    REQUIRE_EXT(ctx, RVB);
135    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
136}
137
138static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
139{
140    REQUIRE_EXT(ctx, RVB);
141    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
142}
143
144static void gen_sbop_mask(TCGv ret, TCGv shamt)
145{
146    tcg_gen_movi_tl(ret, 1);
147    tcg_gen_shl_tl(ret, ret, shamt);
148}
149
150static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
151{
152    TCGv t = tcg_temp_new();
153
154    gen_sbop_mask(t, shamt);
155    tcg_gen_or_tl(ret, arg1, t);
156
157    tcg_temp_free(t);
158}
159
160static bool trans_bset(DisasContext *ctx, arg_bset *a)
161{
162    REQUIRE_EXT(ctx, RVB);
163    return gen_shift(ctx, a, EXT_NONE, gen_bset);
164}
165
166static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
167{
168    REQUIRE_EXT(ctx, RVB);
169    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
170}
171
172static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
173{
174    TCGv t = tcg_temp_new();
175
176    gen_sbop_mask(t, shamt);
177    tcg_gen_andc_tl(ret, arg1, t);
178
179    tcg_temp_free(t);
180}
181
182static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
183{
184    REQUIRE_EXT(ctx, RVB);
185    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
186}
187
188static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
189{
190    REQUIRE_EXT(ctx, RVB);
191    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
192}
193
194static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
195{
196    TCGv t = tcg_temp_new();
197
198    gen_sbop_mask(t, shamt);
199    tcg_gen_xor_tl(ret, arg1, t);
200
201    tcg_temp_free(t);
202}
203
204static bool trans_binv(DisasContext *ctx, arg_binv *a)
205{
206    REQUIRE_EXT(ctx, RVB);
207    return gen_shift(ctx, a, EXT_NONE, gen_binv);
208}
209
210static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
211{
212    REQUIRE_EXT(ctx, RVB);
213    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
214}
215
216static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
217{
218    tcg_gen_shr_tl(ret, arg1, shamt);
219    tcg_gen_andi_tl(ret, ret, 1);
220}
221
222static bool trans_bext(DisasContext *ctx, arg_bext *a)
223{
224    REQUIRE_EXT(ctx, RVB);
225    return gen_shift(ctx, a, EXT_NONE, gen_bext);
226}
227
228static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
229{
230    REQUIRE_EXT(ctx, RVB);
231    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
232}
233
234static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
235{
236    tcg_gen_not_tl(ret, arg1);
237    tcg_gen_shl_tl(ret, ret, arg2);
238    tcg_gen_not_tl(ret, ret);
239}
240
241static bool trans_slo(DisasContext *ctx, arg_slo *a)
242{
243    REQUIRE_EXT(ctx, RVB);
244    return gen_shift(ctx, a, EXT_NONE, gen_slo);
245}
246
247static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
248{
249    REQUIRE_EXT(ctx, RVB);
250    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
251}
252
253static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
254{
255    tcg_gen_not_tl(ret, arg1);
256    tcg_gen_shr_tl(ret, ret, arg2);
257    tcg_gen_not_tl(ret, ret);
258}
259
260static bool trans_sro(DisasContext *ctx, arg_sro *a)
261{
262    REQUIRE_EXT(ctx, RVB);
263    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
264}
265
266static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
267{
268    REQUIRE_EXT(ctx, RVB);
269    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
270}
271
272static bool trans_ror(DisasContext *ctx, arg_ror *a)
273{
274    REQUIRE_EXT(ctx, RVB);
275    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
276}
277
278static bool trans_rori(DisasContext *ctx, arg_rori *a)
279{
280    REQUIRE_EXT(ctx, RVB);
281    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
282}
283
284static bool trans_rol(DisasContext *ctx, arg_rol *a)
285{
286    REQUIRE_EXT(ctx, RVB);
287    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
288}
289
290static bool trans_grev(DisasContext *ctx, arg_grev *a)
291{
292    REQUIRE_EXT(ctx, RVB);
293    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
294}
295
296static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
297{
298    if (shamt == TARGET_LONG_BITS - 8) {
299        /* rev8, byte swaps */
300        tcg_gen_bswap_tl(dest, src);
301    } else {
302        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
303    }
304}
305
306static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
307{
308    REQUIRE_EXT(ctx, RVB);
309    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
310}
311
312static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
313{
314    REQUIRE_EXT(ctx, RVB);
315    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
316}
317
318static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
319{
320    REQUIRE_EXT(ctx, RVB);
321    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
322}
323
324#define GEN_SHADD(SHAMT)                                       \
325static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
326{                                                              \
327    TCGv t = tcg_temp_new();                                   \
328                                                               \
329    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
330    tcg_gen_add_tl(ret, t, arg2);                              \
331                                                               \
332    tcg_temp_free(t);                                          \
333}
334
335GEN_SHADD(1)
336GEN_SHADD(2)
337GEN_SHADD(3)
338
339#define GEN_TRANS_SHADD(SHAMT)                                             \
340static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
341{                                                                          \
342    REQUIRE_EXT(ctx, RVB);                                                 \
343    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
344}
345
346GEN_TRANS_SHADD(1)
347GEN_TRANS_SHADD(2)
348GEN_TRANS_SHADD(3)
349
350static void gen_clzw(TCGv ret, TCGv arg1)
351{
352    TCGv t = tcg_temp_new();
353    tcg_gen_shli_tl(t, arg1, 32);
354    tcg_gen_clzi_tl(ret, t, 32);
355    tcg_temp_free(t);
356}
357
358static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
359{
360    REQUIRE_64BIT(ctx);
361    REQUIRE_EXT(ctx, RVB);
362    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
363}
364
365static void gen_ctzw(TCGv ret, TCGv arg1)
366{
367    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
368    tcg_gen_ctzi_tl(ret, ret, 64);
369}
370
371static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
372{
373    REQUIRE_64BIT(ctx);
374    REQUIRE_EXT(ctx, RVB);
375    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
376}
377
378static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
379{
380    REQUIRE_64BIT(ctx);
381    REQUIRE_EXT(ctx, RVB);
382    ctx->w = true;
383    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
384}
385
386static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
387{
388    TCGv t = tcg_temp_new();
389    tcg_gen_ext16s_tl(t, arg2);
390    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
391    tcg_temp_free(t);
392}
393
394static bool trans_packw(DisasContext *ctx, arg_packw *a)
395{
396    REQUIRE_64BIT(ctx);
397    REQUIRE_EXT(ctx, RVB);
398    return gen_arith(ctx, a, EXT_NONE, gen_packw);
399}
400
401static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
402{
403    TCGv t = tcg_temp_new();
404    tcg_gen_shri_tl(t, arg1, 16);
405    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
406    tcg_gen_ext32s_tl(ret, ret);
407    tcg_temp_free(t);
408}
409
410static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
411{
412    REQUIRE_64BIT(ctx);
413    REQUIRE_EXT(ctx, RVB);
414    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
415}
416
417static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
418{
419    REQUIRE_64BIT(ctx);
420    REQUIRE_EXT(ctx, RVB);
421    ctx->w = true;
422    return gen_shift(ctx, a, EXT_NONE, gen_bset);
423}
424
425static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
426{
427    REQUIRE_64BIT(ctx);
428    REQUIRE_EXT(ctx, RVB);
429    ctx->w = true;
430    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
431}
432
433static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
434{
435    REQUIRE_64BIT(ctx);
436    REQUIRE_EXT(ctx, RVB);
437    ctx->w = true;
438    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
439}
440
441static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
442{
443    REQUIRE_64BIT(ctx);
444    REQUIRE_EXT(ctx, RVB);
445    ctx->w = true;
446    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
447}
448
449static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
450{
451    REQUIRE_64BIT(ctx);
452    REQUIRE_EXT(ctx, RVB);
453    ctx->w = true;
454    return gen_shift(ctx, a, EXT_NONE, gen_binv);
455}
456
457static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
458{
459    REQUIRE_64BIT(ctx);
460    REQUIRE_EXT(ctx, RVB);
461    ctx->w = true;
462    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
463}
464
465static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
466{
467    REQUIRE_64BIT(ctx);
468    REQUIRE_EXT(ctx, RVB);
469    ctx->w = true;
470    return gen_shift(ctx, a, EXT_NONE, gen_bext);
471}
472
473static bool trans_slow(DisasContext *ctx, arg_slow *a)
474{
475    REQUIRE_64BIT(ctx);
476    REQUIRE_EXT(ctx, RVB);
477    ctx->w = true;
478    return gen_shift(ctx, a, EXT_NONE, gen_slo);
479}
480
481static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
482{
483    REQUIRE_64BIT(ctx);
484    REQUIRE_EXT(ctx, RVB);
485    ctx->w = true;
486    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
487}
488
489static bool trans_srow(DisasContext *ctx, arg_srow *a)
490{
491    REQUIRE_64BIT(ctx);
492    REQUIRE_EXT(ctx, RVB);
493    ctx->w = true;
494    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
495}
496
497static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
498{
499    REQUIRE_64BIT(ctx);
500    REQUIRE_EXT(ctx, RVB);
501    ctx->w = true;
502    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
503}
504
505static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
506{
507    TCGv_i32 t1 = tcg_temp_new_i32();
508    TCGv_i32 t2 = tcg_temp_new_i32();
509
510    /* truncate to 32-bits */
511    tcg_gen_trunc_tl_i32(t1, arg1);
512    tcg_gen_trunc_tl_i32(t2, arg2);
513
514    tcg_gen_rotr_i32(t1, t1, t2);
515
516    /* sign-extend 64-bits */
517    tcg_gen_ext_i32_tl(ret, t1);
518
519    tcg_temp_free_i32(t1);
520    tcg_temp_free_i32(t2);
521}
522
523static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
524{
525    REQUIRE_64BIT(ctx);
526    REQUIRE_EXT(ctx, RVB);
527    ctx->w = true;
528    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
529}
530
531static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
532{
533    REQUIRE_64BIT(ctx);
534    REQUIRE_EXT(ctx, RVB);
535    ctx->w = true;
536    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
537}
538
539static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
540{
541    TCGv_i32 t1 = tcg_temp_new_i32();
542    TCGv_i32 t2 = tcg_temp_new_i32();
543
544    /* truncate to 32-bits */
545    tcg_gen_trunc_tl_i32(t1, arg1);
546    tcg_gen_trunc_tl_i32(t2, arg2);
547
548    tcg_gen_rotl_i32(t1, t1, t2);
549
550    /* sign-extend 64-bits */
551    tcg_gen_ext_i32_tl(ret, t1);
552
553    tcg_temp_free_i32(t1);
554    tcg_temp_free_i32(t2);
555}
556
557static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
558{
559    REQUIRE_64BIT(ctx);
560    REQUIRE_EXT(ctx, RVB);
561    ctx->w = true;
562    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
563}
564
565static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
566{
567    REQUIRE_64BIT(ctx);
568    REQUIRE_EXT(ctx, RVB);
569    ctx->w = true;
570    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
571}
572
573static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
574{
575    REQUIRE_64BIT(ctx);
576    REQUIRE_EXT(ctx, RVB);
577    ctx->w = true;
578    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
579}
580
581static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
582{
583    REQUIRE_64BIT(ctx);
584    REQUIRE_EXT(ctx, RVB);
585    ctx->w = true;
586    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
587}
588
589static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
590{
591    REQUIRE_64BIT(ctx);
592    REQUIRE_EXT(ctx, RVB);
593    ctx->w = true;
594    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
595}
596
597#define GEN_SHADD_UW(SHAMT)                                       \
598static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
599{                                                                 \
600    TCGv t = tcg_temp_new();                                      \
601                                                                  \
602    tcg_gen_ext32u_tl(t, arg1);                                   \
603                                                                  \
604    tcg_gen_shli_tl(t, t, SHAMT);                                 \
605    tcg_gen_add_tl(ret, t, arg2);                                 \
606                                                                  \
607    tcg_temp_free(t);                                             \
608}
609
610GEN_SHADD_UW(1)
611GEN_SHADD_UW(2)
612GEN_SHADD_UW(3)
613
614#define GEN_TRANS_SHADD_UW(SHAMT)                             \
615static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
616                                    arg_sh##SHAMT##add_uw *a) \
617{                                                             \
618    REQUIRE_64BIT(ctx);                                       \
619    REQUIRE_EXT(ctx, RVB);                                    \
620    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
621}
622
623GEN_TRANS_SHADD_UW(1)
624GEN_TRANS_SHADD_UW(2)
625GEN_TRANS_SHADD_UW(3)
626
627static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
628{
629    TCGv t = tcg_temp_new();
630    tcg_gen_ext32u_tl(t, arg1);
631    tcg_gen_add_tl(ret, t, arg2);
632    tcg_temp_free(t);
633}
634
635static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
636{
637    REQUIRE_64BIT(ctx);
638    REQUIRE_EXT(ctx, RVB);
639    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
640}
641
642static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
643{
644    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
645}
646
647static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
648{
649    REQUIRE_64BIT(ctx);
650    REQUIRE_EXT(ctx, RVB);
651    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
652}
653