1/*
2 * RISC-V translation routines for the RV64A Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_A_OR_ZAAMO(ctx) do {                      \
22    if (!ctx->cfg_ptr->ext_zaamo && !has_ext(ctx, RVA)) { \
23        return false;                                     \
24    }                                                     \
25} while (0)
26
27#define REQUIRE_A_OR_ZALRSC(ctx) do {                      \
28    if (!ctx->cfg_ptr->ext_zalrsc && !has_ext(ctx, RVA)) { \
29        return false;                                     \
30    }                                                     \
31} while (0)
32
33static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
34{
35    TCGv src1;
36
37    decode_save_opc(ctx);
38    src1 = get_address(ctx, a->rs1, 0);
39    if (a->rl) {
40        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
41    }
42    tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
43    if (a->aq) {
44        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
45    }
46
47    /* Put addr in load_res, data in load_val.  */
48    tcg_gen_mov_tl(load_res, src1);
49    gen_set_gpr(ctx, a->rd, load_val);
50
51    return true;
52}
53
54static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
55{
56    TCGv dest, src1, src2;
57    TCGLabel *l1 = gen_new_label();
58    TCGLabel *l2 = gen_new_label();
59
60    decode_save_opc(ctx);
61    src1 = get_address(ctx, a->rs1, 0);
62    tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
63
64    /*
65     * Note that the TCG atomic primitives are SC,
66     * so we can ignore AQ/RL along this path.
67     */
68    dest = dest_gpr(ctx, a->rd);
69    src2 = get_gpr(ctx, a->rs2, EXT_NONE);
70    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
71                              ctx->mem_idx, mop);
72    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
73    gen_set_gpr(ctx, a->rd, dest);
74    tcg_gen_br(l2);
75
76    gen_set_label(l1);
77    /*
78     * Address comparison failure.  However, we still need to
79     * provide the memory barrier implied by AQ/RL.
80     */
81    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
82    gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
83
84    gen_set_label(l2);
85    /*
86     * Clear the load reservation, since an SC must fail if there is
87     * an SC to any address, in between an LR and SC pair.
88     */
89    tcg_gen_movi_tl(load_res, -1);
90
91    return true;
92}
93
94static bool gen_amo(DisasContext *ctx, arg_atomic *a,
95                    void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
96                    MemOp mop)
97{
98    TCGv dest = dest_gpr(ctx, a->rd);
99    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
100
101    decode_save_opc(ctx);
102    src1 = get_address(ctx, a->rs1, 0);
103    func(dest, src1, src2, ctx->mem_idx, mop);
104
105    gen_set_gpr(ctx, a->rd, dest);
106    return true;
107}
108
109static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
110{
111    REQUIRE_A_OR_ZALRSC(ctx);
112    return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
113}
114
115static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
116{
117    REQUIRE_A_OR_ZALRSC(ctx);
118    return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
119}
120
121static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
122{
123    REQUIRE_A_OR_ZAAMO(ctx);
124    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
125}
126
127static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
128{
129    REQUIRE_A_OR_ZAAMO(ctx);
130    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
131}
132
133static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
134{
135    REQUIRE_A_OR_ZAAMO(ctx);
136    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
137}
138
139static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
140{
141    REQUIRE_A_OR_ZAAMO(ctx);
142    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
143}
144
145static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
146{
147    REQUIRE_A_OR_ZAAMO(ctx);
148    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
149}
150
151static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
152{
153    REQUIRE_A_OR_ZAAMO(ctx);
154    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
155}
156
157static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
158{
159    REQUIRE_A_OR_ZAAMO(ctx);
160    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
161}
162
163static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
164{
165    REQUIRE_A_OR_ZAAMO(ctx);
166    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
167}
168
169static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
170{
171    REQUIRE_A_OR_ZAAMO(ctx);
172    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
173}
174
175static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
176{
177    REQUIRE_64BIT(ctx);
178    REQUIRE_A_OR_ZALRSC(ctx);
179    return gen_lr(ctx, a, MO_ALIGN | MO_TEUQ);
180}
181
182static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
183{
184    REQUIRE_64BIT(ctx);
185    REQUIRE_A_OR_ZALRSC(ctx);
186    return gen_sc(ctx, a, (MO_ALIGN | MO_TEUQ));
187}
188
189static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
190{
191    REQUIRE_64BIT(ctx);
192    REQUIRE_A_OR_ZAAMO(ctx);
193    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ));
194}
195
196static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
197{
198    REQUIRE_64BIT(ctx);
199    REQUIRE_A_OR_ZAAMO(ctx);
200    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEUQ));
201}
202
203static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
204{
205    REQUIRE_64BIT(ctx);
206    REQUIRE_A_OR_ZAAMO(ctx);
207    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEUQ));
208}
209
210static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
211{
212    REQUIRE_64BIT(ctx);
213    REQUIRE_A_OR_ZAAMO(ctx);
214    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEUQ));
215}
216
217static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
218{
219    REQUIRE_64BIT(ctx);
220    REQUIRE_A_OR_ZAAMO(ctx);
221    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEUQ));
222}
223
224static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
225{
226    REQUIRE_64BIT(ctx);
227    REQUIRE_A_OR_ZAAMO(ctx);
228    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEUQ));
229}
230
231static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
232{
233    REQUIRE_64BIT(ctx);
234    REQUIRE_A_OR_ZAAMO(ctx);
235    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEUQ));
236}
237
238static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
239{
240    REQUIRE_64BIT(ctx);
241    REQUIRE_A_OR_ZAAMO(ctx);
242    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEUQ));
243}
244
245static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
246{
247    REQUIRE_64BIT(ctx);
248    REQUIRE_A_OR_ZAAMO(ctx);
249    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEUQ));
250}
251