1/*
2 * RISC-V translation routines for the RV64A Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define REQUIRE_A_OR_ZAAMO(ctx) do {                      \
22    if (!ctx->cfg_ptr->ext_zaamo && !has_ext(ctx, RVA)) { \
23        return false;                                     \
24    }                                                     \
25} while (0)
26
27#define REQUIRE_A_OR_ZALRSC(ctx) do {                      \
28    if (!ctx->cfg_ptr->ext_zalrsc && !has_ext(ctx, RVA)) { \
29        return false;                                     \
30    }                                                     \
31} while (0)
32
33static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
34{
35    TCGv src1;
36
37    decode_save_opc(ctx, 0);
38    src1 = get_address(ctx, a->rs1, 0);
39    if (a->rl) {
40        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
41    }
42    tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
43    /*
44     * TSO defines AMOs as acquire+release-RCsc, but does not define LR/SC as
45     * AMOs.  Instead treat them like loads.
46     */
47    if (a->aq || ctx->ztso) {
48        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
49    }
50
51    /* Put addr in load_res, data in load_val.  */
52    tcg_gen_mov_tl(load_res, src1);
53    gen_set_gpr(ctx, a->rd, load_val);
54
55    return true;
56}
57
58static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
59{
60    TCGv dest, src1, src2;
61    TCGLabel *l1 = gen_new_label();
62    TCGLabel *l2 = gen_new_label();
63
64    decode_save_opc(ctx, 0);
65    src1 = get_address(ctx, a->rs1, 0);
66    tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
67
68    /*
69     * Note that the TCG atomic primitives are SC,
70     * so we can ignore AQ/RL along this path.
71     */
72    dest = dest_gpr(ctx, a->rd);
73    src2 = get_gpr(ctx, a->rs2, EXT_NONE);
74    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
75                              ctx->mem_idx, mop);
76    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
77    gen_set_gpr(ctx, a->rd, dest);
78    tcg_gen_br(l2);
79
80    gen_set_label(l1);
81    /*
82     * Address comparison failure.  However, we still need to
83     * provide the memory barrier implied by AQ/RL/TSO.
84     */
85    TCGBar bar_strl = (ctx->ztso || a->rl) ? TCG_BAR_STRL : 0;
86    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + bar_strl);
87    gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
88
89    gen_set_label(l2);
90    /*
91     * Clear the load reservation, since an SC must fail if there is
92     * an SC to any address, in between an LR and SC pair.
93     */
94    tcg_gen_movi_tl(load_res, -1);
95
96    return true;
97}
98
99static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
100{
101    REQUIRE_A_OR_ZALRSC(ctx);
102    return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
103}
104
105static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
106{
107    REQUIRE_A_OR_ZALRSC(ctx);
108    return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
109}
110
111static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
112{
113    REQUIRE_A_OR_ZAAMO(ctx);
114    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TESL);
115}
116
117static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
118{
119    REQUIRE_A_OR_ZAAMO(ctx);
120    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TESL);
121}
122
123static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
124{
125    REQUIRE_A_OR_ZAAMO(ctx);
126    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TESL);
127}
128
129static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
130{
131    REQUIRE_A_OR_ZAAMO(ctx);
132    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TESL);
133}
134
135static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
136{
137    REQUIRE_A_OR_ZAAMO(ctx);
138    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TESL);
139}
140
141static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
142{
143    REQUIRE_A_OR_ZAAMO(ctx);
144    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TESL);
145}
146
147static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
148{
149    REQUIRE_A_OR_ZAAMO(ctx);
150    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TESL);
151}
152
153static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
154{
155    REQUIRE_A_OR_ZAAMO(ctx);
156    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TESL);
157}
158
159static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
160{
161    REQUIRE_A_OR_ZAAMO(ctx);
162    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TESL);
163}
164
165static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
166{
167    REQUIRE_64BIT(ctx);
168    REQUIRE_A_OR_ZALRSC(ctx);
169    return gen_lr(ctx, a, MO_ALIGN | MO_TEUQ);
170}
171
172static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
173{
174    REQUIRE_64BIT(ctx);
175    REQUIRE_A_OR_ZALRSC(ctx);
176    return gen_sc(ctx, a, (MO_ALIGN | MO_TEUQ));
177}
178
179static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
180{
181    REQUIRE_64BIT(ctx);
182    REQUIRE_A_OR_ZAAMO(ctx);
183    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_TEUQ);
184}
185
186static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
187{
188    REQUIRE_64BIT(ctx);
189    REQUIRE_A_OR_ZAAMO(ctx);
190    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_TEUQ);
191}
192
193static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
194{
195    REQUIRE_64BIT(ctx);
196    REQUIRE_A_OR_ZAAMO(ctx);
197    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_TEUQ);
198}
199
200static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
201{
202    REQUIRE_64BIT(ctx);
203    REQUIRE_A_OR_ZAAMO(ctx);
204    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_TEUQ);
205}
206
207static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
208{
209    REQUIRE_64BIT(ctx);
210    REQUIRE_A_OR_ZAAMO(ctx);
211    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_TEUQ);
212}
213
214static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
215{
216    REQUIRE_64BIT(ctx);
217    REQUIRE_A_OR_ZAAMO(ctx);
218    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_TEUQ);
219}
220
221static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
222{
223    REQUIRE_64BIT(ctx);
224    REQUIRE_A_OR_ZAAMO(ctx);
225    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_TEUQ);
226}
227
228static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
229{
230    REQUIRE_64BIT(ctx);
231    REQUIRE_A_OR_ZAAMO(ctx);
232    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_TEUQ);
233}
234
235static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
236{
237    REQUIRE_64BIT(ctx);
238    REQUIRE_A_OR_ZAAMO(ctx);
239    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_TEUQ);
240}
241