1/*
2 * RISC-V translation routines for the RV64A Standard Extension.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
22{
23    TCGv src1;
24
25    decode_save_opc(ctx);
26    src1 = get_address(ctx, a->rs1, 0);
27    if (a->rl) {
28        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
29    }
30    tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
31    if (a->aq) {
32        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
33    }
34
35    /* Put addr in load_res, data in load_val.  */
36    tcg_gen_mov_tl(load_res, src1);
37    gen_set_gpr(ctx, a->rd, load_val);
38
39    return true;
40}
41
42static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
43{
44    TCGv dest, src1, src2;
45    TCGLabel *l1 = gen_new_label();
46    TCGLabel *l2 = gen_new_label();
47
48    decode_save_opc(ctx);
49    src1 = get_address(ctx, a->rs1, 0);
50    tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
51
52    /*
53     * Note that the TCG atomic primitives are SC,
54     * so we can ignore AQ/RL along this path.
55     */
56    dest = dest_gpr(ctx, a->rd);
57    src2 = get_gpr(ctx, a->rs2, EXT_NONE);
58    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
59                              ctx->mem_idx, mop);
60    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
61    gen_set_gpr(ctx, a->rd, dest);
62    tcg_gen_br(l2);
63
64    gen_set_label(l1);
65    /*
66     * Address comparison failure.  However, we still need to
67     * provide the memory barrier implied by AQ/RL.
68     */
69    tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
70    gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
71
72    gen_set_label(l2);
73    /*
74     * Clear the load reservation, since an SC must fail if there is
75     * an SC to any address, in between an LR and SC pair.
76     */
77    tcg_gen_movi_tl(load_res, -1);
78
79    return true;
80}
81
82static bool gen_amo(DisasContext *ctx, arg_atomic *a,
83                    void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
84                    MemOp mop)
85{
86    TCGv dest = dest_gpr(ctx, a->rd);
87    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
88
89    decode_save_opc(ctx);
90    src1 = get_address(ctx, a->rs1, 0);
91    func(dest, src1, src2, ctx->mem_idx, mop);
92
93    gen_set_gpr(ctx, a->rd, dest);
94    return true;
95}
96
97static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
98{
99    REQUIRE_EXT(ctx, RVA);
100    return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
101}
102
103static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
104{
105    REQUIRE_EXT(ctx, RVA);
106    return gen_sc(ctx, a, (MO_ALIGN | MO_TESL));
107}
108
109static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
110{
111    REQUIRE_EXT(ctx, RVA);
112    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
113}
114
115static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
116{
117    REQUIRE_EXT(ctx, RVA);
118    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
119}
120
121static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
122{
123    REQUIRE_EXT(ctx, RVA);
124    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
125}
126
127static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
128{
129    REQUIRE_EXT(ctx, RVA);
130    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
131}
132
133static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
134{
135    REQUIRE_EXT(ctx, RVA);
136    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
137}
138
139static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
140{
141    REQUIRE_EXT(ctx, RVA);
142    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
143}
144
145static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
146{
147    REQUIRE_EXT(ctx, RVA);
148    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
149}
150
151static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
152{
153    REQUIRE_EXT(ctx, RVA);
154    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
155}
156
157static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
158{
159    REQUIRE_EXT(ctx, RVA);
160    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
161}
162
163static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
164{
165    REQUIRE_64BIT(ctx);
166    return gen_lr(ctx, a, MO_ALIGN | MO_TEUQ);
167}
168
169static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
170{
171    REQUIRE_64BIT(ctx);
172    return gen_sc(ctx, a, (MO_ALIGN | MO_TEUQ));
173}
174
175static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
176{
177    REQUIRE_64BIT(ctx);
178    return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ));
179}
180
181static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
182{
183    REQUIRE_64BIT(ctx);
184    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEUQ));
185}
186
187static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
188{
189    REQUIRE_64BIT(ctx);
190    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEUQ));
191}
192
193static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
194{
195    REQUIRE_64BIT(ctx);
196    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEUQ));
197}
198
199static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
200{
201    REQUIRE_64BIT(ctx);
202    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEUQ));
203}
204
205static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
206{
207    REQUIRE_64BIT(ctx);
208    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEUQ));
209}
210
211static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
212{
213    REQUIRE_64BIT(ctx);
214    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEUQ));
215}
216
217static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
218{
219    REQUIRE_64BIT(ctx);
220    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEUQ));
221}
222
223static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
224{
225    REQUIRE_64BIT(ctx);
226    return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEUQ));
227}
228