1/*
2 * RISC-V translation routines for the RISC-V privileged instructions.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
22{
23    /* always generates U-level ECALL, fixed in do_interrupt handler */
24    generate_exception(ctx, RISCV_EXCP_U_ECALL);
25    return true;
26}
27
28static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
29{
30    target_ulong    ebreak_addr = ctx->base.pc_next;
31    target_ulong    pre_addr = ebreak_addr - 4;
32    target_ulong    post_addr = ebreak_addr + 4;
33    uint32_t pre    = 0;
34    uint32_t ebreak = 0;
35    uint32_t post   = 0;
36
37    /*
38     * The RISC-V semihosting spec specifies the following
39     * three-instruction sequence to flag a semihosting call:
40     *
41     *      slli zero, zero, 0x1f       0x01f01013
42     *      ebreak                      0x00100073
43     *      srai zero, zero, 0x7        0x40705013
44     *
45     * The two shift operations on the zero register are no-ops, used
46     * here to signify a semihosting exception, rather than a breakpoint.
47     *
48     * Uncompressed instructions are required so that the sequence is easy
49     * to validate.
50     *
51     * The three instructions are required to lie in the same page so
52     * that no exception will be raised when fetching them.
53     */
54
55    if (semihosting_enabled(ctx->mem_idx < PRV_S) &&
56        (pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
57        pre    = opcode_at(&ctx->base, pre_addr);
58        ebreak = opcode_at(&ctx->base, ebreak_addr);
59        post   = opcode_at(&ctx->base, post_addr);
60    }
61
62    if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
63        generate_exception(ctx, RISCV_EXCP_SEMIHOST);
64    } else {
65        generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
66    }
67    return true;
68}
69
70static bool trans_uret(DisasContext *ctx, arg_uret *a)
71{
72    return false;
73}
74
75static bool trans_sret(DisasContext *ctx, arg_sret *a)
76{
77#ifndef CONFIG_USER_ONLY
78    if (has_ext(ctx, RVS)) {
79        decode_save_opc(ctx);
80        gen_helper_sret(cpu_pc, cpu_env);
81        exit_tb(ctx); /* no chaining */
82        ctx->base.is_jmp = DISAS_NORETURN;
83    } else {
84        return false;
85    }
86    return true;
87#else
88    return false;
89#endif
90}
91
92static bool trans_mret(DisasContext *ctx, arg_mret *a)
93{
94#ifndef CONFIG_USER_ONLY
95    decode_save_opc(ctx);
96    gen_helper_mret(cpu_pc, cpu_env);
97    exit_tb(ctx); /* no chaining */
98    ctx->base.is_jmp = DISAS_NORETURN;
99    return true;
100#else
101    return false;
102#endif
103}
104
105static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
106{
107#ifndef CONFIG_USER_ONLY
108    decode_save_opc(ctx);
109    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
110    gen_helper_wfi(cpu_env);
111    return true;
112#else
113    return false;
114#endif
115}
116
117static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
118{
119#ifndef CONFIG_USER_ONLY
120    decode_save_opc(ctx);
121    gen_helper_tlb_flush(cpu_env);
122    return true;
123#endif
124    return false;
125}
126
127static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
128{
129    return false;
130}
131