1/* 2 * RISC-V translation routines for the RISC-V privileged instructions. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#define REQUIRE_SMRNMI(ctx) do { \ 22 if (!ctx->cfg_ptr->ext_smrnmi) { \ 23 return false; \ 24 } \ 25} while (0) 26 27static bool trans_ecall(DisasContext *ctx, arg_ecall *a) 28{ 29 /* always generates U-level ECALL, fixed in do_interrupt handler */ 30 generate_exception(ctx, RISCV_EXCP_U_ECALL); 31 return true; 32} 33 34static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) 35{ 36 target_ulong ebreak_addr = ctx->base.pc_next; 37 target_ulong pre_addr = ebreak_addr - 4; 38 target_ulong post_addr = ebreak_addr + 4; 39 uint32_t pre = 0; 40 uint32_t ebreak = 0; 41 uint32_t post = 0; 42 43 /* 44 * The RISC-V semihosting spec specifies the following 45 * three-instruction sequence to flag a semihosting call: 46 * 47 * slli zero, zero, 0x1f 0x01f01013 48 * ebreak 0x00100073 49 * srai zero, zero, 0x7 0x40705013 50 * 51 * The two shift operations on the zero register are no-ops, used 52 * here to signify a semihosting exception, rather than a breakpoint. 53 * 54 * Uncompressed instructions are required so that the sequence is easy 55 * to validate. 56 * 57 * The three instructions are required to lie in the same page so 58 * that no exception will be raised when fetching them. 59 */ 60 61 if (semihosting_enabled(ctx->priv == PRV_U) && 62 (pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) { 63 pre = opcode_at(&ctx->base, pre_addr); 64 ebreak = opcode_at(&ctx->base, ebreak_addr); 65 post = opcode_at(&ctx->base, post_addr); 66 } 67 68 if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { 69 generate_exception(ctx, RISCV_EXCP_SEMIHOST); 70 } else { 71 tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, 72 offsetof(CPURISCVState, badaddr)); 73 generate_exception(ctx, RISCV_EXCP_BREAKPOINT); 74 } 75 return true; 76} 77 78static bool trans_uret(DisasContext *ctx, arg_uret *a) 79{ 80 return false; 81} 82 83static bool trans_sret(DisasContext *ctx, arg_sret *a) 84{ 85#ifndef CONFIG_USER_ONLY 86 if (has_ext(ctx, RVS)) { 87 decode_save_opc(ctx, 0); 88 translator_io_start(&ctx->base); 89 gen_helper_sret(cpu_pc, tcg_env); 90 exit_tb(ctx); /* no chaining */ 91 ctx->base.is_jmp = DISAS_NORETURN; 92 } else { 93 return false; 94 } 95 return true; 96#else 97 return false; 98#endif 99} 100 101static bool trans_mret(DisasContext *ctx, arg_mret *a) 102{ 103#ifndef CONFIG_USER_ONLY 104 decode_save_opc(ctx, 0); 105 translator_io_start(&ctx->base); 106 gen_helper_mret(cpu_pc, tcg_env); 107 exit_tb(ctx); /* no chaining */ 108 ctx->base.is_jmp = DISAS_NORETURN; 109 return true; 110#else 111 return false; 112#endif 113} 114 115static bool trans_mnret(DisasContext *ctx, arg_mnret *a) 116{ 117#ifndef CONFIG_USER_ONLY 118 REQUIRE_SMRNMI(ctx); 119 decode_save_opc(ctx, 0); 120 gen_helper_mnret(cpu_pc, tcg_env); 121 tcg_gen_exit_tb(NULL, 0); /* no chaining */ 122 ctx->base.is_jmp = DISAS_NORETURN; 123 return true; 124#else 125 return false; 126#endif 127} 128 129static bool trans_wfi(DisasContext *ctx, arg_wfi *a) 130{ 131#ifndef CONFIG_USER_ONLY 132 decode_save_opc(ctx, 0); 133 gen_update_pc(ctx, ctx->cur_insn_len); 134 gen_helper_wfi(tcg_env); 135 return true; 136#else 137 return false; 138#endif 139} 140 141static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) 142{ 143#ifndef CONFIG_USER_ONLY 144 decode_save_opc(ctx, 0); 145 gen_helper_tlb_flush(tcg_env); 146 return true; 147#endif 148 return false; 149} 150 151static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) 152{ 153 return false; 154} 155