1/* 2 * RISC-V translation routines for the RISC-V privileged instructions. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#define REQUIRE_SMRNMI(ctx) do { \ 22 if (!ctx->cfg_ptr->ext_smrnmi) { \ 23 return false; \ 24 } \ 25} while (0) 26 27static bool trans_ecall(DisasContext *ctx, arg_ecall *a) 28{ 29 /* always generates U-level ECALL, fixed in do_interrupt handler */ 30 generate_exception(ctx, RISCV_EXCP_U_ECALL); 31 return true; 32} 33 34static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) 35{ 36 target_ulong ebreak_addr = ctx->base.pc_next; 37 target_ulong pre_addr = ebreak_addr - 4; 38 target_ulong post_addr = ebreak_addr + 4; 39 uint32_t pre = 0; 40 uint32_t ebreak = 0; 41 uint32_t post = 0; 42 43 /* 44 * The RISC-V semihosting spec specifies the following 45 * three-instruction sequence to flag a semihosting call: 46 * 47 * slli zero, zero, 0x1f 0x01f01013 48 * ebreak 0x00100073 49 * srai zero, zero, 0x7 0x40705013 50 * 51 * The two shift operations on the zero register are no-ops, used 52 * here to signify a semihosting exception, rather than a breakpoint. 53 * 54 * Uncompressed instructions are required so that the sequence is easy 55 * to validate. 56 * 57 * The three instructions are required to lie in the same page so 58 * that no exception will be raised when fetching them. 59 */ 60 61 if (semihosting_enabled(ctx->priv == PRV_U) && 62 (pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) { 63 pre = opcode_at(&ctx->base, pre_addr); 64 ebreak = opcode_at(&ctx->base, ebreak_addr); 65 post = opcode_at(&ctx->base, post_addr); 66 } 67 68 if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { 69 generate_exception(ctx, RISCV_EXCP_SEMIHOST); 70 } else { 71 tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, 72 offsetof(CPURISCVState, badaddr)); 73 generate_exception(ctx, RISCV_EXCP_BREAKPOINT); 74 } 75 return true; 76} 77 78static bool trans_sctrclr(DisasContext *ctx, arg_sctrclr *a) 79{ 80#ifndef CONFIG_USER_ONLY 81 if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) { 82 gen_helper_ctr_clear(tcg_env); 83 return true; 84 } 85#endif 86 return false; 87} 88 89static bool trans_uret(DisasContext *ctx, arg_uret *a) 90{ 91 return false; 92} 93 94static bool trans_sret(DisasContext *ctx, arg_sret *a) 95{ 96#ifndef CONFIG_USER_ONLY 97 if (has_ext(ctx, RVS)) { 98 decode_save_opc(ctx, 0); 99 translator_io_start(&ctx->base); 100 gen_update_pc(ctx, 0); 101 gen_helper_sret(cpu_pc, tcg_env); 102 exit_tb(ctx); /* no chaining */ 103 ctx->base.is_jmp = DISAS_NORETURN; 104 } else { 105 return false; 106 } 107 return true; 108#else 109 return false; 110#endif 111} 112 113static bool trans_mret(DisasContext *ctx, arg_mret *a) 114{ 115#ifndef CONFIG_USER_ONLY 116 decode_save_opc(ctx, 0); 117 translator_io_start(&ctx->base); 118 gen_update_pc(ctx, 0); 119 gen_helper_mret(cpu_pc, tcg_env); 120 exit_tb(ctx); /* no chaining */ 121 ctx->base.is_jmp = DISAS_NORETURN; 122 return true; 123#else 124 return false; 125#endif 126} 127 128static bool trans_mnret(DisasContext *ctx, arg_mnret *a) 129{ 130#ifndef CONFIG_USER_ONLY 131 REQUIRE_SMRNMI(ctx); 132 decode_save_opc(ctx, 0); 133 gen_helper_mnret(cpu_pc, tcg_env); 134 tcg_gen_exit_tb(NULL, 0); /* no chaining */ 135 ctx->base.is_jmp = DISAS_NORETURN; 136 return true; 137#else 138 return false; 139#endif 140} 141 142static bool trans_wfi(DisasContext *ctx, arg_wfi *a) 143{ 144#ifndef CONFIG_USER_ONLY 145 decode_save_opc(ctx, 0); 146 gen_update_pc(ctx, ctx->cur_insn_len); 147 gen_helper_wfi(tcg_env); 148 return true; 149#else 150 return false; 151#endif 152} 153 154static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) 155{ 156#ifndef CONFIG_USER_ONLY 157 decode_save_opc(ctx, 0); 158 gen_helper_tlb_flush(tcg_env); 159 return true; 160#endif 161 return false; 162} 163