xref: /openbmc/qemu/target/riscv/insn32.decode (revision ae3c12a0)
1#
2# RISC-V translation routines for the RVXI Base Integer Instruction Set.
3#
4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
5#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
6#
7# This program is free software; you can redistribute it and/or modify it
8# under the terms and conditions of the GNU General Public License,
9# version 2 or later, as published by the Free Software Foundation.
10#
11# This program is distributed in the hope it will be useful, but WITHOUT
12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14# more details.
15#
16# You should have received a copy of the GNU General Public License along with
17# this program.  If not, see <http://www.gnu.org/licenses/>.
18
19# Fields:
20%rs3       27:5
21%rs2       20:5
22%rs1       15:5
23%rd        7:5
24
25%sh10    20:10
26%csr    20:12
27%rm     12:3
28
29# immediates:
30%imm_i    20:s12
31%imm_s    25:s7 7:5
32%imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
33%imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
34%imm_u    12:s20                 !function=ex_shift_12
35
36# Argument sets:
37&b    imm rs2 rs1
38&i    imm rs1 rd
39&r    rd rs1 rs2
40&shift     shamt rs1 rd
41&atomic    aq rl rs2 rs1 rd
42
43# Formats 32:
44@r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
45@i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
46@b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
47@s       .......   ..... ..... ... ..... .......         imm=%imm_s %rs2 %rs1
48@u       ....................      ..... .......         imm=%imm_u          %rd
49@j       ....................      ..... .......         imm=%imm_j          %rd
50
51@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
52@csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
53
54@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
55@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd
56
57@r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
58@r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
59@r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
60@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
61
62@sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
63@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
64
65
66# *** Privileged Instructions ***
67ecall      000000000000     00000 000 00000 1110011
68ebreak     000000000001     00000 000 00000 1110011
69uret       0000000    00010 00000 000 00000 1110011
70sret       0001000    00010 00000 000 00000 1110011
71hret       0010000    00010 00000 000 00000 1110011
72mret       0011000    00010 00000 000 00000 1110011
73wfi        0001000    00101 00000 000 00000 1110011
74sfence_vma 0001001    ..... ..... 000 00000 1110011 @sfence_vma
75sfence_vm  0001000    00100 ..... 000 00000 1110011 @sfence_vm
76
77# *** RV32I Base Instruction Set ***
78lui      ....................       ..... 0110111 @u
79auipc    ....................       ..... 0010111 @u
80jal      ....................       ..... 1101111 @j
81jalr     ............     ..... 000 ..... 1100111 @i
82beq      ....... .....    ..... 000 ..... 1100011 @b
83bne      ....... .....    ..... 001 ..... 1100011 @b
84blt      ....... .....    ..... 100 ..... 1100011 @b
85bge      ....... .....    ..... 101 ..... 1100011 @b
86bltu     ....... .....    ..... 110 ..... 1100011 @b
87bgeu     ....... .....    ..... 111 ..... 1100011 @b
88lb       ............     ..... 000 ..... 0000011 @i
89lh       ............     ..... 001 ..... 0000011 @i
90lw       ............     ..... 010 ..... 0000011 @i
91lbu      ............     ..... 100 ..... 0000011 @i
92lhu      ............     ..... 101 ..... 0000011 @i
93sb       .......  .....   ..... 000 ..... 0100011 @s
94sh       .......  .....   ..... 001 ..... 0100011 @s
95sw       .......  .....   ..... 010 ..... 0100011 @s
96addi     ............     ..... 000 ..... 0010011 @i
97slti     ............     ..... 010 ..... 0010011 @i
98sltiu    ............     ..... 011 ..... 0010011 @i
99xori     ............     ..... 100 ..... 0010011 @i
100ori      ............     ..... 110 ..... 0010011 @i
101andi     ............     ..... 111 ..... 0010011 @i
102slli     00.... ......    ..... 001 ..... 0010011 @sh
103srli     00.... ......    ..... 101 ..... 0010011 @sh
104srai     01.... ......    ..... 101 ..... 0010011 @sh
105add      0000000 .....    ..... 000 ..... 0110011 @r
106sub      0100000 .....    ..... 000 ..... 0110011 @r
107sll      0000000 .....    ..... 001 ..... 0110011 @r
108slt      0000000 .....    ..... 010 ..... 0110011 @r
109sltu     0000000 .....    ..... 011 ..... 0110011 @r
110xor      0000000 .....    ..... 100 ..... 0110011 @r
111srl      0000000 .....    ..... 101 ..... 0110011 @r
112sra      0100000 .....    ..... 101 ..... 0110011 @r
113or       0000000 .....    ..... 110 ..... 0110011 @r
114and      0000000 .....    ..... 111 ..... 0110011 @r
115fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
116fence_i  ---- ----   ----   ----- 001 ----- 0001111
117csrrw    ............     ..... 001 ..... 1110011 @csr
118csrrs    ............     ..... 010 ..... 1110011 @csr
119csrrc    ............     ..... 011 ..... 1110011 @csr
120csrrwi   ............     ..... 101 ..... 1110011 @csr
121csrrsi   ............     ..... 110 ..... 1110011 @csr
122csrrci   ............     ..... 111 ..... 1110011 @csr
123
124# *** RV32M Standard Extension ***
125mul      0000001 .....  ..... 000 ..... 0110011 @r
126mulh     0000001 .....  ..... 001 ..... 0110011 @r
127mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
128mulhu    0000001 .....  ..... 011 ..... 0110011 @r
129div      0000001 .....  ..... 100 ..... 0110011 @r
130divu     0000001 .....  ..... 101 ..... 0110011 @r
131rem      0000001 .....  ..... 110 ..... 0110011 @r
132remu     0000001 .....  ..... 111 ..... 0110011 @r
133
134# *** RV32A Standard Extension ***
135lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
136sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
137amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
138amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
139amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
140amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
141amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
142amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
143amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
144amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
145amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
146
147# *** RV32F Standard Extension ***
148flw        ............   ..... 010 ..... 0000111 @i
149fsw        .......  ..... ..... 010 ..... 0100111 @s
150fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
151fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
152fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
153fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
154fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
155fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
156fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
157fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
158fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
159fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
160fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
161fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
162fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
163fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
164fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
165fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
166fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
167feq_s      1010000  ..... ..... 010 ..... 1010011 @r
168flt_s      1010000  ..... ..... 001 ..... 1010011 @r
169fle_s      1010000  ..... ..... 000 ..... 1010011 @r
170fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
171fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
172fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
173fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
174
175# *** RV32D Standard Extension ***
176fld        ............   ..... 011 ..... 0000111 @i
177fsd        ....... .....  ..... 011 ..... 0100111 @s
178fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
179fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
180fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
181fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
182fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
183fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
184fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
185fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
186fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
187fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
188fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
189fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
190fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
191fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
192fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
193fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
194feq_d      1010001  ..... ..... 010 ..... 1010011 @r
195flt_d      1010001  ..... ..... 001 ..... 1010011 @r
196fle_d      1010001  ..... ..... 000 ..... 1010011 @r
197fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
198fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
199fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
200fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
201fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
202