1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24 25%sh10 20:10 26%csr 20:12 27%rm 12:3 28%nf 29:3 !function=ex_plus_1 29 30# immediates: 31%imm_i 20:s12 32%imm_s 25:s7 7:5 33%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 34%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 35%imm_u 12:s20 !function=ex_shift_12 36 37# Argument sets: 38&empty 39&b imm rs2 rs1 40&i imm rs1 rd 41&j imm rd 42&r rd rs1 rs2 43&s imm rs1 rs2 44&u imm rd 45&shift shamt rs1 rd 46&atomic aq rl rs2 rs1 rd 47&rmrr vm rd rs1 rs2 48&rwdvm vm wd rd rs1 rs2 49&r2nfvm vm rd rs1 nf 50&rnfvm vm rd rs1 rs2 nf 51 52# Formats 32: 53@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 54@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 55@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 56@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 57@u .................... ..... ....... &u imm=%imm_u %rd 58@j .................... ..... ....... &j imm=%imm_j %rd 59 60@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd 61@csr ............ ..... ... ..... ....... %csr %rs1 %rd 62 63@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 64@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 65 66@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 67@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 68@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 69@r2 ....... ..... ..... ... ..... ....... %rs1 %rd 70@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 71@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 72@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd 73@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd 74@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd 75@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd 76@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd 77 78@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 79@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 80 81@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 82@sfence_vm ....... ..... ..... ... ..... ....... %rs1 83 84 85# *** Privileged Instructions *** 86ecall 000000000000 00000 000 00000 1110011 87ebreak 000000000001 00000 000 00000 1110011 88uret 0000000 00010 00000 000 00000 1110011 89sret 0001000 00010 00000 000 00000 1110011 90mret 0011000 00010 00000 000 00000 1110011 91wfi 0001000 00101 00000 000 00000 1110011 92sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 93sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 94 95# *** RV32I Base Instruction Set *** 96lui .................... ..... 0110111 @u 97auipc .................... ..... 0010111 @u 98jal .................... ..... 1101111 @j 99jalr ............ ..... 000 ..... 1100111 @i 100beq ....... ..... ..... 000 ..... 1100011 @b 101bne ....... ..... ..... 001 ..... 1100011 @b 102blt ....... ..... ..... 100 ..... 1100011 @b 103bge ....... ..... ..... 101 ..... 1100011 @b 104bltu ....... ..... ..... 110 ..... 1100011 @b 105bgeu ....... ..... ..... 111 ..... 1100011 @b 106lb ............ ..... 000 ..... 0000011 @i 107lh ............ ..... 001 ..... 0000011 @i 108lw ............ ..... 010 ..... 0000011 @i 109lbu ............ ..... 100 ..... 0000011 @i 110lhu ............ ..... 101 ..... 0000011 @i 111sb ....... ..... ..... 000 ..... 0100011 @s 112sh ....... ..... ..... 001 ..... 0100011 @s 113sw ....... ..... ..... 010 ..... 0100011 @s 114addi ............ ..... 000 ..... 0010011 @i 115slti ............ ..... 010 ..... 0010011 @i 116sltiu ............ ..... 011 ..... 0010011 @i 117xori ............ ..... 100 ..... 0010011 @i 118ori ............ ..... 110 ..... 0010011 @i 119andi ............ ..... 111 ..... 0010011 @i 120slli 00.... ...... ..... 001 ..... 0010011 @sh 121srli 00.... ...... ..... 101 ..... 0010011 @sh 122srai 01.... ...... ..... 101 ..... 0010011 @sh 123add 0000000 ..... ..... 000 ..... 0110011 @r 124sub 0100000 ..... ..... 000 ..... 0110011 @r 125sll 0000000 ..... ..... 001 ..... 0110011 @r 126slt 0000000 ..... ..... 010 ..... 0110011 @r 127sltu 0000000 ..... ..... 011 ..... 0110011 @r 128xor 0000000 ..... ..... 100 ..... 0110011 @r 129srl 0000000 ..... ..... 101 ..... 0110011 @r 130sra 0100000 ..... ..... 101 ..... 0110011 @r 131or 0000000 ..... ..... 110 ..... 0110011 @r 132and 0000000 ..... ..... 111 ..... 0110011 @r 133fence ---- pred:4 succ:4 ----- 000 ----- 0001111 134fence_i ---- ---- ---- ----- 001 ----- 0001111 135csrrw ............ ..... 001 ..... 1110011 @csr 136csrrs ............ ..... 010 ..... 1110011 @csr 137csrrc ............ ..... 011 ..... 1110011 @csr 138csrrwi ............ ..... 101 ..... 1110011 @csr 139csrrsi ............ ..... 110 ..... 1110011 @csr 140csrrci ............ ..... 111 ..... 1110011 @csr 141 142# *** RV32M Standard Extension *** 143mul 0000001 ..... ..... 000 ..... 0110011 @r 144mulh 0000001 ..... ..... 001 ..... 0110011 @r 145mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 146mulhu 0000001 ..... ..... 011 ..... 0110011 @r 147div 0000001 ..... ..... 100 ..... 0110011 @r 148divu 0000001 ..... ..... 101 ..... 0110011 @r 149rem 0000001 ..... ..... 110 ..... 0110011 @r 150remu 0000001 ..... ..... 111 ..... 0110011 @r 151 152# *** RV32A Standard Extension *** 153lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 154sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 155amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 156amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 157amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 158amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 159amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 160amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 161amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 162amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 163amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 164 165# *** RV32F Standard Extension *** 166flw ............ ..... 010 ..... 0000111 @i 167fsw ....... ..... ..... 010 ..... 0100111 @s 168fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 169fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 170fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 171fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 172fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 173fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 174fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 175fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 176fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 177fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 178fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 179fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 180fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 181fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 182fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 183fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 184fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 185feq_s 1010000 ..... ..... 010 ..... 1010011 @r 186flt_s 1010000 ..... ..... 001 ..... 1010011 @r 187fle_s 1010000 ..... ..... 000 ..... 1010011 @r 188fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 189fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 190fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 191fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 192 193# *** RV32D Standard Extension *** 194fld ............ ..... 011 ..... 0000111 @i 195fsd ....... ..... ..... 011 ..... 0100111 @s 196fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 197fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 198fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 199fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 200fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 201fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 202fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 203fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 204fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 205fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 206fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 207fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 208fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 209fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 210fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 211fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 212feq_d 1010001 ..... ..... 010 ..... 1010011 @r 213flt_d 1010001 ..... ..... 001 ..... 1010011 @r 214fle_d 1010001 ..... ..... 000 ..... 1010011 @r 215fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 216fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 217fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 218fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 219fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 220 221# *** RV32H Base Instruction Set *** 222hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 223hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 224 225# *** RV32V Extension *** 226 227# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 228vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm 229vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm 230vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm 231vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 232vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 233vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 234vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 235vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm 236vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm 237vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm 238vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 239vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 240vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 241vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 242vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 243vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 244vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 245vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 246 247vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm 248vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm 249vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm 250vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 251vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 252vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 253vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 254vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 255vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 256vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 257vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 258 259vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm 260vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm 261vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm 262vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm 263vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm 264vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm 265vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm 266# Vector ordered-indexed and unordered-indexed store insns. 267vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm 268vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm 269vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm 270vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm 271 272#*** Vector AMO operations are encoded under the standard AMO major opcode *** 273vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm 274vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm 275vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm 276vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm 277vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm 278vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm 279vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm 280vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm 281vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm 282 283# *** new major opcode OP-V *** 284vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm 285vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm 286vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm 287vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm 288vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm 289vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm 290vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm 291vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm 292vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm 293vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm 294vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm 295vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm 296vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm 297vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm 298vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm 299vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm 300vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm 301vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm 302vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm 303vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm 304vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm 305vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm 306vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm 307vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1 308vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1 309vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1 310vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1 311vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1 312vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1 313vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1 314vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1 315vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1 316vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1 317vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm 318vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm 319vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm 320vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm 321vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm 322vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm 323vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm 324vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm 325vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm 326vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm 327vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm 328vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm 329vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm 330vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm 331vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm 332vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm 333vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm 334vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm 335vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm 336vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm 337vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm 338vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm 339vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm 340vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm 341vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm 342vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm 343vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm 344vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm 345vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm 346vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm 347vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm 348vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm 349vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm 350vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm 351vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm 352vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm 353vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm 354vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm 355vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm 356vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm 357vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm 358vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm 359vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm 360vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm 361vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm 362vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm 363vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm 364vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm 365vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm 366vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm 367vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm 368vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm 369vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm 370vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm 371vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm 372vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm 373vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm 374vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm 375vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm 376vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm 377vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm 378vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm 379vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm 380vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm 381vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm 382vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm 383vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm 384vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm 385vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm 386vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm 387vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm 388vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm 389vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm 390vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm 391vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm 392vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm 393vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm 394vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm 395vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm 396vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm 397vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm 398vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm 399vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm 400vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm 401vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm 402vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm 403vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm 404vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm 405vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm 406vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 407vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 408vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 409vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 410vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 411vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 412vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm 413vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm 414vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm 415vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm 416vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm 417vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm 418vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm 419vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm 420vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm 421vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm 422vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm 423vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm 424vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm 425vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm 426vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm 427vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm 428vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm 429 430vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm 431vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 432