1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24%sh5 20:5 25 26%sh7 20:7 27%csr 20:12 28%rm 12:3 29%nf 29:3 !function=ex_plus_1 30 31# immediates: 32%imm_i 20:s12 33%imm_s 25:s7 7:5 34%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 35%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 36%imm_u 12:s20 !function=ex_shift_12 37 38# Argument sets: 39&empty 40&b imm rs2 rs1 41&i imm rs1 rd 42&j imm rd 43&r rd rs1 rs2 44&r2 rd rs1 45&r2_s rs1 rs2 46&s imm rs1 rs2 47&u imm rd 48&shift shamt rs1 rd 49&atomic aq rl rs2 rs1 rd 50&rmrr vm rd rs1 rs2 51&rmr vm rd rs2 52&r2nfvm vm rd rs1 nf 53&rnfvm vm rd rs1 rs2 nf 54 55# Formats 32: 56@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 57@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 58@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 59@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 60@u .................... ..... ....... &u imm=%imm_u %rd 61@j .................... ..... ....... &j imm=%imm_j %rd 62 63@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd 64@csr ............ ..... ... ..... ....... %csr %rs1 %rd 65 66@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 67@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 68 69@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 70@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 71@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 72@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd 73@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 74@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd 75@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd 76@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 77@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd 78@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd 79@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd 80@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd 81@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd 82@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 83 84@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 85@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 86 87@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 88@sfence_vm ....... ..... ..... ... ..... ....... %rs1 89 90# Formats 64: 91@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd 92 93# *** Privileged Instructions *** 94ecall 000000000000 00000 000 00000 1110011 95ebreak 000000000001 00000 000 00000 1110011 96uret 0000000 00010 00000 000 00000 1110011 97sret 0001000 00010 00000 000 00000 1110011 98mret 0011000 00010 00000 000 00000 1110011 99wfi 0001000 00101 00000 000 00000 1110011 100sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 101sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 102 103# *** RV32I Base Instruction Set *** 104lui .................... ..... 0110111 @u 105auipc .................... ..... 0010111 @u 106jal .................... ..... 1101111 @j 107jalr ............ ..... 000 ..... 1100111 @i 108beq ....... ..... ..... 000 ..... 1100011 @b 109bne ....... ..... ..... 001 ..... 1100011 @b 110blt ....... ..... ..... 100 ..... 1100011 @b 111bge ....... ..... ..... 101 ..... 1100011 @b 112bltu ....... ..... ..... 110 ..... 1100011 @b 113bgeu ....... ..... ..... 111 ..... 1100011 @b 114lb ............ ..... 000 ..... 0000011 @i 115lh ............ ..... 001 ..... 0000011 @i 116lw ............ ..... 010 ..... 0000011 @i 117lbu ............ ..... 100 ..... 0000011 @i 118lhu ............ ..... 101 ..... 0000011 @i 119sb ....... ..... ..... 000 ..... 0100011 @s 120sh ....... ..... ..... 001 ..... 0100011 @s 121sw ....... ..... ..... 010 ..... 0100011 @s 122addi ............ ..... 000 ..... 0010011 @i 123slti ............ ..... 010 ..... 0010011 @i 124sltiu ............ ..... 011 ..... 0010011 @i 125xori ............ ..... 100 ..... 0010011 @i 126ori ............ ..... 110 ..... 0010011 @i 127andi ............ ..... 111 ..... 0010011 @i 128slli 00000. ...... ..... 001 ..... 0010011 @sh 129srli 00000. ...... ..... 101 ..... 0010011 @sh 130srai 01000. ...... ..... 101 ..... 0010011 @sh 131add 0000000 ..... ..... 000 ..... 0110011 @r 132sub 0100000 ..... ..... 000 ..... 0110011 @r 133sll 0000000 ..... ..... 001 ..... 0110011 @r 134slt 0000000 ..... ..... 010 ..... 0110011 @r 135sltu 0000000 ..... ..... 011 ..... 0110011 @r 136xor 0000000 ..... ..... 100 ..... 0110011 @r 137srl 0000000 ..... ..... 101 ..... 0110011 @r 138sra 0100000 ..... ..... 101 ..... 0110011 @r 139or 0000000 ..... ..... 110 ..... 0110011 @r 140and 0000000 ..... ..... 111 ..... 0110011 @r 141fence ---- pred:4 succ:4 ----- 000 ----- 0001111 142fence_i ---- ---- ---- ----- 001 ----- 0001111 143csrrw ............ ..... 001 ..... 1110011 @csr 144csrrs ............ ..... 010 ..... 1110011 @csr 145csrrc ............ ..... 011 ..... 1110011 @csr 146csrrwi ............ ..... 101 ..... 1110011 @csr 147csrrsi ............ ..... 110 ..... 1110011 @csr 148csrrci ............ ..... 111 ..... 1110011 @csr 149 150# *** RV64I Base Instruction Set (in addition to RV32I) *** 151lwu ............ ..... 110 ..... 0000011 @i 152ld ............ ..... 011 ..... 0000011 @i 153sd ....... ..... ..... 011 ..... 0100011 @s 154addiw ............ ..... 000 ..... 0011011 @i 155slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 156srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 157sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 158addw 0000000 ..... ..... 000 ..... 0111011 @r 159subw 0100000 ..... ..... 000 ..... 0111011 @r 160sllw 0000000 ..... ..... 001 ..... 0111011 @r 161srlw 0000000 ..... ..... 101 ..... 0111011 @r 162sraw 0100000 ..... ..... 101 ..... 0111011 @r 163 164# *** RV32M Standard Extension *** 165mul 0000001 ..... ..... 000 ..... 0110011 @r 166mulh 0000001 ..... ..... 001 ..... 0110011 @r 167mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 168mulhu 0000001 ..... ..... 011 ..... 0110011 @r 169div 0000001 ..... ..... 100 ..... 0110011 @r 170divu 0000001 ..... ..... 101 ..... 0110011 @r 171rem 0000001 ..... ..... 110 ..... 0110011 @r 172remu 0000001 ..... ..... 111 ..... 0110011 @r 173 174# *** RV64M Standard Extension (in addition to RV32M) *** 175mulw 0000001 ..... ..... 000 ..... 0111011 @r 176divw 0000001 ..... ..... 100 ..... 0111011 @r 177divuw 0000001 ..... ..... 101 ..... 0111011 @r 178remw 0000001 ..... ..... 110 ..... 0111011 @r 179remuw 0000001 ..... ..... 111 ..... 0111011 @r 180 181# *** RV32A Standard Extension *** 182lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 183sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 184amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 185amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 186amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 187amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 188amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 189amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 190amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 191amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 192amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 193 194# *** RV64A Standard Extension (in addition to RV32A) *** 195lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld 196sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st 197amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st 198amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st 199amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st 200amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st 201amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st 202amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st 203amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st 204amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st 205amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st 206 207# *** RV32F Standard Extension *** 208flw ............ ..... 010 ..... 0000111 @i 209fsw ....... ..... ..... 010 ..... 0100111 @s 210fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 211fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 212fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 213fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 214fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 215fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 216fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 217fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 218fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 219fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 220fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 221fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 222fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 223fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 224fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 225fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 226fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 227feq_s 1010000 ..... ..... 010 ..... 1010011 @r 228flt_s 1010000 ..... ..... 001 ..... 1010011 @r 229fle_s 1010000 ..... ..... 000 ..... 1010011 @r 230fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 231fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 232fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 233fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 234 235# *** RV64F Standard Extension (in addition to RV32F) *** 236fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm 237fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm 238fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm 239fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm 240 241# *** RV32D Standard Extension *** 242fld ............ ..... 011 ..... 0000111 @i 243fsd ....... ..... ..... 011 ..... 0100111 @s 244fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 245fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 246fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 247fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 248fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 249fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 250fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 251fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 252fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 253fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 254fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 255fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 256fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 257fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 258fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 259fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 260feq_d 1010001 ..... ..... 010 ..... 1010011 @r 261flt_d 1010001 ..... ..... 001 ..... 1010011 @r 262fle_d 1010001 ..... ..... 000 ..... 1010011 @r 263fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 264fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 265fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 266fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 267fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 268 269# *** RV64D Standard Extension (in addition to RV32D) *** 270fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm 271fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm 272fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 273fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm 274fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm 275fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 276 277# *** RV32H Base Instruction Set *** 278hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 279hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 280hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 281hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 282hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 283hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 284hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 285hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s 286hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s 287hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s 288hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 289hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 290 291# *** RV64H Base Instruction Set *** 292hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 293hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 294hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s 295 296# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 297# Vector unit-stride load/store insns. 298vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 299vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 300vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 301vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 302vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 303vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 304vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 305vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 306 307# Vector strided insns. 308vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 309vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 310vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 311vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 312vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 313vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 314vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 315vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 316 317vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm 318vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm 319vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm 320vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 321vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 322vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 323vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 324 325vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm 326vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm 327vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm 328vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm 329vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm 330vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm 331vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm 332# Vector ordered-indexed and unordered-indexed store insns. 333vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm 334vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm 335vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm 336vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm 337 338# *** new major opcode OP-V *** 339vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm 340vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm 341vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm 342vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm 343vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm 344vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm 345vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm 346vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm 347vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm 348vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm 349vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm 350vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm 351vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm 352vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm 353vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm 354vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm 355vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm 356vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm 357vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm 358vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm 359vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm 360vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm 361vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm 362vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1 363vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1 364vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1 365vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1 366vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1 367vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1 368vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1 369vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1 370vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1 371vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1 372vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm 373vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm 374vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm 375vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm 376vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm 377vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm 378vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm 379vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm 380vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm 381vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm 382vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm 383vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm 384vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm 385vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm 386vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm 387vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm 388vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm 389vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm 390vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm 391vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm 392vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm 393vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm 394vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm 395vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm 396vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm 397vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm 398vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm 399vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm 400vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm 401vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm 402vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm 403vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm 404vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm 405vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm 406vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm 407vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm 408vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm 409vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm 410vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm 411vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm 412vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm 413vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm 414vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm 415vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm 416vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm 417vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm 418vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm 419vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm 420vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm 421vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm 422vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm 423vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm 424vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm 425vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm 426vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm 427vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm 428vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm 429vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm 430vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm 431vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm 432vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm 433vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm 434vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm 435vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm 436vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm 437vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm 438vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm 439vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm 440vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm 441vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm 442vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm 443vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm 444vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm 445vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm 446vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm 447vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm 448vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm 449vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm 450vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm 451vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm 452vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm 453vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm 454vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm 455vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm 456vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm 457vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm 458vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm 459vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm 460vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm 461vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 462vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 463vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 464vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 465vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 466vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 467vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm 468vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm 469vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm 470vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm 471vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm 472vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm 473vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm 474vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm 475vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm 476vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm 477vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm 478vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm 479vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm 480vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm 481vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm 482vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm 483vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm 484vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm 485vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm 486vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm 487vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm 488vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm 489vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm 490vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm 491vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm 492vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm 493vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm 494vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm 495vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm 496vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm 497vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm 498vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm 499vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm 500vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm 501vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm 502vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm 503vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm 504vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm 505vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm 506vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm 507vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm 508vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm 509vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm 510vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm 511vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm 512vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm 513vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm 514vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm 515vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm 516vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm 517vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm 518vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm 519vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm 520vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm 521vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm 522vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm 523vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm 524vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm 525vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm 526vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm 527vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm 528vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm 529vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm 530vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm 531vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm 532vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm 533vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm 534vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm 535vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm 536vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm 537vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm 538vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm 539vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm 540vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm 541vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm 542vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm 543vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm 544vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm 545vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm 546vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm 547vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm 548vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm 549vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm 550vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm 551vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm 552vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm 553vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm 554vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm 555vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm 556vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm 557vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm 558vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm 559vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm 560vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm 561vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm 562vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm 563vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm 564vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm 565vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm 566vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm 567vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm 568vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm 569vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm 570vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm 571vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 572vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 573vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm 574vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm 575vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm 576vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm 577vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm 578vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm 579vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm 580vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm 581vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm 582vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm 583vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm 584vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm 585vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm 586vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm 587vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm 588vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm 589vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm 590vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm 591vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm 592vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm 593vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm 594vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm 595vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm 596vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm 597# Vector ordered and unordered reduction sum 598vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm 599vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm 600vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm 601# Vector widening ordered and unordered float reduction sum 602vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm 603vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r 604vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r 605vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r 606vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r 607vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r 608vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r 609vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r 610vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r 611vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm 612vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm 613vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm 614vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm 615vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm 616viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm 617vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm 618vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r 619vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 620vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd 621vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 622vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm 623vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm 624vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm 625vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm 626vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm 627vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm 628vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm 629vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm 630vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm 631vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r 632 633vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm 634vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 635 636# *** RV32 Zba Standard Extension *** 637sh1add 0010000 .......... 010 ..... 0110011 @r 638sh2add 0010000 .......... 100 ..... 0110011 @r 639sh3add 0010000 .......... 110 ..... 0110011 @r 640 641# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** 642add_uw 0000100 .......... 000 ..... 0111011 @r 643sh1add_uw 0010000 .......... 010 ..... 0111011 @r 644sh2add_uw 0010000 .......... 100 ..... 0111011 @r 645sh3add_uw 0010000 .......... 110 ..... 0111011 @r 646slli_uw 00001 ............ 001 ..... 0011011 @sh 647 648# *** RV32 Zbb Standard Extension *** 649andn 0100000 .......... 111 ..... 0110011 @r 650clz 011000 000000 ..... 001 ..... 0010011 @r2 651cpop 011000 000010 ..... 001 ..... 0010011 @r2 652ctz 011000 000001 ..... 001 ..... 0010011 @r2 653max 0000101 .......... 110 ..... 0110011 @r 654maxu 0000101 .......... 111 ..... 0110011 @r 655min 0000101 .......... 100 ..... 0110011 @r 656minu 0000101 .......... 101 ..... 0110011 @r 657orc_b 001010 000111 ..... 101 ..... 0010011 @r2 658orn 0100000 .......... 110 ..... 0110011 @r 659# The encoding for rev8 differs between RV32 and RV64. 660# rev8_32 denotes the RV32 variant. 661rev8_32 011010 011000 ..... 101 ..... 0010011 @r2 662rol 0110000 .......... 001 ..... 0110011 @r 663ror 0110000 .......... 101 ..... 0110011 @r 664rori 01100 ............ 101 ..... 0010011 @sh 665sext_b 011000 000100 ..... 001 ..... 0010011 @r2 666sext_h 011000 000101 ..... 001 ..... 0010011 @r2 667xnor 0100000 .......... 100 ..... 0110011 @r 668# The encoding for zext.h differs between RV32 and RV64. 669# zext_h_32 denotes the RV32 variant. 670zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 671 672# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** 673clzw 0110000 00000 ..... 001 ..... 0011011 @r2 674ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 675cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 676# The encoding for rev8 differs between RV32 and RV64. 677# When executing on RV64, the encoding used in RV32 is an illegal 678# instruction, so we use different handler functions to differentiate. 679rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 680rolw 0110000 .......... 001 ..... 0111011 @r 681roriw 0110000 .......... 101 ..... 0011011 @sh5 682rorw 0110000 .......... 101 ..... 0111011 @r 683# The encoding for zext.h differs between RV32 and RV64. 684# When executing on RV64, the encoding used in RV32 is an illegal 685# instruction, so we use different handler functions to differentiate. 686zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 687 688# *** RV32 Zbc Standard Extension *** 689clmul 0000101 .......... 001 ..... 0110011 @r 690clmulh 0000101 .......... 011 ..... 0110011 @r 691clmulr 0000101 .......... 010 ..... 0110011 @r 692 693# *** RV32 Zbs Standard Extension *** 694bclr 0100100 .......... 001 ..... 0110011 @r 695bclri 01001. ........... 001 ..... 0010011 @sh 696bext 0100100 .......... 101 ..... 0110011 @r 697bexti 01001. ........... 101 ..... 0010011 @sh 698binv 0110100 .......... 001 ..... 0110011 @r 699binvi 01101. ........... 001 ..... 0010011 @sh 700bset 0010100 .......... 001 ..... 0110011 @r 701bseti 00101. ........... 001 ..... 0010011 @sh 702 703# *** RV32 Zfh Extension *** 704flh ............ ..... 001 ..... 0000111 @i 705fsh ....... ..... ..... 001 ..... 0100111 @s 706fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm 707fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm 708fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm 709fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm 710fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm 711fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm 712fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm 713fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm 714fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm 715fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r 716fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r 717fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r 718fmin_h 0010110 ..... ..... 000 ..... 1010011 @r 719fmax_h 0010110 ..... ..... 001 ..... 1010011 @r 720fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm 721fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm 722fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm 723fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm 724fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm 725fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm 726fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 727feq_h 1010010 ..... ..... 010 ..... 1010011 @r 728flt_h 1010010 ..... ..... 001 ..... 1010011 @r 729fle_h 1010010 ..... ..... 000 ..... 1010011 @r 730fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 731fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm 732fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm 733fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 734 735# *** RV64 Zfh Extension (in addition to RV32 Zfh) *** 736fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm 737fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm 738fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm 739fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm 740