1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24%sh5 20:5 25%sh6 20:6 26 27%sh7 20:7 28%csr 20:12 29%rm 12:3 30%nf 29:3 !function=ex_plus_1 31 32# immediates: 33%imm_i 20:s12 34%imm_s 25:s7 7:5 35%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 36%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 37%imm_u 12:s20 !function=ex_shift_12 38%imm_bs 30:2 !function=ex_shift_3 39%imm_rnum 20:4 40%imm_z6 26:1 15:5 41%imm_mop5 30:1 26:2 20:2 42%imm_mop3 30:1 26:2 43 44# Argument sets: 45&empty 46&b imm rs2 rs1 47&i imm rs1 rd 48&j imm rd 49&r rd rs1 rs2 50&r2 rd rs1 51&r2_s rs1 rs2 52&s imm rs1 rs2 53&u imm rd 54&shift shamt rs1 rd 55&atomic aq rl rs2 rs1 rd 56&rmrr vm rd rs1 rs2 57&rmr vm rd rs2 58&r2nfvm vm rd rs1 nf 59&rnfvm vm rd rs1 rs2 nf 60&k_aes shamt rs2 rs1 rd 61&mop5 imm rd rs1 62&mop3 imm rd rs1 rs2 63 64# Formats 32: 65@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 66@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 67@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 68@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 69@u .................... ..... ....... &u imm=%imm_u %rd 70@j .................... ..... ....... &j imm=%imm_j %rd 71 72@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd 73@csr ............ ..... ... ..... ....... %csr %rs1 %rd 74 75@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 76@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 77 78@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 79@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 80@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 81@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd 82@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd 83@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 84@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd 85@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd 86@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 87@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd 88@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd 89@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd 90@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd 91@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=%imm_z6 %rd 92@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd 93@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd 94@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 95 96@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 97@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 98 99@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 100@sfence_vm ....... ..... ..... ... ..... ....... %rs1 101 102@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd 103@i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd 104 105@mop5 . . .. .. .... .. ..... ... ..... ....... &mop5 imm=%imm_mop5 %rd %rs1 106@mop3 . . .. .. . ..... ..... ... ..... ....... &mop3 imm=%imm_mop3 %rd %rs1 %rs2 107 108# Formats 64: 109@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd 110 111# Formats 128: 112@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd 113 114# *** Privileged Instructions *** 115ecall 000000000000 00000 000 00000 1110011 116ebreak 000000000001 00000 000 00000 1110011 117uret 0000000 00010 00000 000 00000 1110011 118sret 0001000 00010 00000 000 00000 1110011 119mret 0011000 00010 00000 000 00000 1110011 120wfi 0001000 00101 00000 000 00000 1110011 121sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 122sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 123 124# *** RV32I Base Instruction Set *** 125lui .................... ..... 0110111 @u 126{ 127 lpad label:20 00000 0010111 128 auipc .................... ..... 0010111 @u 129} 130jal .................... ..... 1101111 @j 131jalr ............ ..... 000 ..... 1100111 @i 132beq ....... ..... ..... 000 ..... 1100011 @b 133bne ....... ..... ..... 001 ..... 1100011 @b 134blt ....... ..... ..... 100 ..... 1100011 @b 135bge ....... ..... ..... 101 ..... 1100011 @b 136bltu ....... ..... ..... 110 ..... 1100011 @b 137bgeu ....... ..... ..... 111 ..... 1100011 @b 138lb ............ ..... 000 ..... 0000011 @i 139lh ............ ..... 001 ..... 0000011 @i 140lw ............ ..... 010 ..... 0000011 @i 141lbu ............ ..... 100 ..... 0000011 @i 142lhu ............ ..... 101 ..... 0000011 @i 143sb ....... ..... ..... 000 ..... 0100011 @s 144sh ....... ..... ..... 001 ..... 0100011 @s 145sw ....... ..... ..... 010 ..... 0100011 @s 146addi ............ ..... 000 ..... 0010011 @i 147slti ............ ..... 010 ..... 0010011 @i 148sltiu ............ ..... 011 ..... 0010011 @i 149xori ............ ..... 100 ..... 0010011 @i 150# cbo.prefetch_{i,r,m} instructions are ori with rd=x0 and not decoded. 151ori ............ ..... 110 ..... 0010011 @i 152andi ............ ..... 111 ..... 0010011 @i 153slli 00000. ...... ..... 001 ..... 0010011 @sh 154srli 00000. ...... ..... 101 ..... 0010011 @sh 155srai 01000. ...... ..... 101 ..... 0010011 @sh 156add 0000000 ..... ..... 000 ..... 0110011 @r 157sub 0100000 ..... ..... 000 ..... 0110011 @r 158sll 0000000 ..... ..... 001 ..... 0110011 @r 159slt 0000000 ..... ..... 010 ..... 0110011 @r 160sltu 0000000 ..... ..... 011 ..... 0110011 @r 161xor 0000000 ..... ..... 100 ..... 0110011 @r 162srl 0000000 ..... ..... 101 ..... 0110011 @r 163sra 0100000 ..... ..... 101 ..... 0110011 @r 164or 0000000 ..... ..... 110 ..... 0110011 @r 165and 0000000 ..... ..... 111 ..... 0110011 @r 166 167{ 168 pause 0000 0001 0000 00000 000 00000 0001111 169 fence ---- pred:4 succ:4 ----- 000 ----- 0001111 170} 171 172fence_i ---- ---- ---- ----- 001 ----- 0001111 173csrrw ............ ..... 001 ..... 1110011 @csr 174csrrs ............ ..... 010 ..... 1110011 @csr 175csrrc ............ ..... 011 ..... 1110011 @csr 176csrrwi ............ ..... 101 ..... 1110011 @csr 177csrrsi ............ ..... 110 ..... 1110011 @csr 178csrrci ............ ..... 111 ..... 1110011 @csr 179 180# *** RV64I Base Instruction Set (in addition to RV32I) *** 181lwu ............ ..... 110 ..... 0000011 @i 182ld ............ ..... 011 ..... 0000011 @i 183sd ....... ..... ..... 011 ..... 0100011 @s 184addiw ............ ..... 000 ..... 0011011 @i 185slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 186srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 187sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 188addw 0000000 ..... ..... 000 ..... 0111011 @r 189subw 0100000 ..... ..... 000 ..... 0111011 @r 190sllw 0000000 ..... ..... 001 ..... 0111011 @r 191srlw 0000000 ..... ..... 101 ..... 0111011 @r 192sraw 0100000 ..... ..... 101 ..... 0111011 @r 193 194# *** RV128I Base Instruction Set (in addition to RV64I) *** 195ldu ............ ..... 111 ..... 0000011 @i 196{ 197 [ 198 # *** RV32 Zicbom Standard Extension *** 199 cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm 200 cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm 201 cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm 202 203 # *** RV32 Zicboz Standard Extension *** 204 cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm 205 ] 206 207 # *** RVI128 lq *** 208 lq ............ ..... 010 ..... 0001111 @i 209} 210sq ............ ..... 100 ..... 0100011 @s 211addid ............ ..... 000 ..... 1011011 @i 212sllid 000000 ...... ..... 001 ..... 1011011 @sh6 213srlid 000000 ...... ..... 101 ..... 1011011 @sh6 214sraid 010000 ...... ..... 101 ..... 1011011 @sh6 215addd 0000000 ..... ..... 000 ..... 1111011 @r 216subd 0100000 ..... ..... 000 ..... 1111011 @r 217slld 0000000 ..... ..... 001 ..... 1111011 @r 218srld 0000000 ..... ..... 101 ..... 1111011 @r 219srad 0100000 ..... ..... 101 ..... 1111011 @r 220 221# *** RV32M Standard Extension *** 222mul 0000001 ..... ..... 000 ..... 0110011 @r 223mulh 0000001 ..... ..... 001 ..... 0110011 @r 224mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 225mulhu 0000001 ..... ..... 011 ..... 0110011 @r 226div 0000001 ..... ..... 100 ..... 0110011 @r 227divu 0000001 ..... ..... 101 ..... 0110011 @r 228rem 0000001 ..... ..... 110 ..... 0110011 @r 229remu 0000001 ..... ..... 111 ..... 0110011 @r 230 231# *** RV64M Standard Extension (in addition to RV32M) *** 232mulw 0000001 ..... ..... 000 ..... 0111011 @r 233divw 0000001 ..... ..... 100 ..... 0111011 @r 234divuw 0000001 ..... ..... 101 ..... 0111011 @r 235remw 0000001 ..... ..... 110 ..... 0111011 @r 236remuw 0000001 ..... ..... 111 ..... 0111011 @r 237 238# *** RV128M Standard Extension (in addition to RV64M) *** 239muld 0000001 ..... ..... 000 ..... 1111011 @r 240divd 0000001 ..... ..... 100 ..... 1111011 @r 241divud 0000001 ..... ..... 101 ..... 1111011 @r 242remd 0000001 ..... ..... 110 ..... 1111011 @r 243remud 0000001 ..... ..... 111 ..... 1111011 @r 244 245# *** RV32A Standard Extension *** 246lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 247sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 248amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 249ssamoswap_w 01001 . . ..... ..... 010 ..... 0101111 @atom_st 250amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 251amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 252amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 253amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 254amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 255amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 256amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 257amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 258 259# *** RV64A Standard Extension (in addition to RV32A) *** 260lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld 261sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st 262amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st 263ssamoswap_d 01001 . . ..... ..... 011 ..... 0101111 @atom_st 264amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st 265amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st 266amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st 267amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st 268amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st 269amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st 270amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st 271amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st 272 273# *** RV32F Standard Extension *** 274flw ............ ..... 010 ..... 0000111 @i 275fsw ....... ..... ..... 010 ..... 0100111 @s 276fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 277fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 278fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 279fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 280fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 281fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 282fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 283fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 284fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 285fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 286fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 287fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 288fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 289fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 290fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 291fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 292fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 293feq_s 1010000 ..... ..... 010 ..... 1010011 @r 294flt_s 1010000 ..... ..... 001 ..... 1010011 @r 295fle_s 1010000 ..... ..... 000 ..... 1010011 @r 296fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 297fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 298fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 299fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 300 301# *** RV64F Standard Extension (in addition to RV32F) *** 302fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm 303fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm 304fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm 305fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm 306 307# *** RV32D Standard Extension *** 308fld ............ ..... 011 ..... 0000111 @i 309fsd ....... ..... ..... 011 ..... 0100111 @s 310fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 311fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 312fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 313fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 314fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 315fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 316fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 317fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 318fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 319fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 320fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 321fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 322fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 323fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 324fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 325fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 326feq_d 1010001 ..... ..... 010 ..... 1010011 @r 327flt_d 1010001 ..... ..... 001 ..... 1010011 @r 328fle_d 1010001 ..... ..... 000 ..... 1010011 @r 329fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 330fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 331fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 332fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 333fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 334 335# *** RV64D Standard Extension (in addition to RV32D) *** 336fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm 337fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm 338fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 339fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm 340fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm 341fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 342 343# *** RV32H Base Instruction Set *** 344hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 345hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 346hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 347hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 348hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 349hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 350hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 351hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s 352hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s 353hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s 354hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 355hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 356 357# *** RV64H Base Instruction Set *** 358hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 359hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 360hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s 361 362# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 363# Vector unit-stride load/store insns. 364vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 365vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 366vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 367vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 368vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 369vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 370vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 371vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 372 373# Vector unit-stride mask load/store insns. 374vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2 375vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2 376 377# Vector strided insns. 378vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 379vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 380vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 381vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 382vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 383vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 384vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 385vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 386 387# Vector ordered-indexed and unordered-indexed load insns. 388vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm 389vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm 390vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm 391vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm 392 393# Vector ordered-indexed and unordered-indexed store insns. 394vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm 395vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm 396vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm 397vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm 398 399# Vector unit-stride fault-only-first load insns. 400vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 401vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 402vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 403vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 404 405# Vector whole register insns 406vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 407vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2 408vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2 409vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2 410vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2 411vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2 412vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2 413vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2 414vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2 415vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2 416vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2 417vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2 418vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2 419vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2 420vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2 421vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2 422vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 423vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2 424vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2 425vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2 426 427# *** new major opcode OP-V *** 428vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm 429vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm 430vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm 431vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm 432vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm 433vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm 434vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm 435vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm 436vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm 437vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm 438vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm 439vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm 440vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm 441vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm 442vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm 443vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm 444vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm 445vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm 446vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm 447vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm 448vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm 449vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm 450vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm 451vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 452vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 453vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 454vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm 455vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm 456vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm 457vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 458vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 459vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm 460vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm 461vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm 462vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm 463vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm 464vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm 465vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm 466vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm 467vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm 468vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm 469vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm 470vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm 471vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm 472vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm 473vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm 474vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm 475vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm 476vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm 477vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm 478vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm 479vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm 480vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm 481vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm 482vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm 483vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm 484vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm 485vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm 486vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm 487vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm 488vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm 489vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm 490vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm 491vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm 492vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm 493vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm 494vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm 495vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm 496vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm 497vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm 498vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm 499vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm 500vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm 501vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm 502vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm 503vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm 504vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm 505vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm 506vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm 507vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm 508vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm 509vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm 510vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm 511vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm 512vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm 513vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm 514vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm 515vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm 516vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm 517vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm 518vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm 519vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm 520vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm 521vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm 522vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm 523vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm 524vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm 525vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm 526vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm 527vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm 528vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm 529vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm 530vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm 531vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm 532vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm 533vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm 534vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm 535vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm 536vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm 537vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm 538vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm 539vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm 540vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm 541vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm 542vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm 543vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm 544vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm 545vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm 546vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm 547vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm 548vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm 549vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm 550vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 551vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 552vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 553vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 554vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 555vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 556vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm 557vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm 558vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm 559vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm 560vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm 561vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm 562vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm 563vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm 564vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm 565vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm 566vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm 567vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm 568vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm 569vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm 570vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm 571vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm 572vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm 573vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm 574vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm 575vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm 576vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm 577vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm 578vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm 579vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm 580vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm 581vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm 582vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm 583vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm 584vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm 585vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm 586vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm 587vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm 588vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm 589vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm 590vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm 591vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm 592vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm 593vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm 594vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm 595vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm 596vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm 597vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm 598vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm 599vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm 600vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm 601vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm 602vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm 603vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm 604vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm 605vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm 606vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm 607vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm 608vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm 609vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm 610vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm 611vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm 612vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm 613vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm 614vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm 615vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm 616vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm 617vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm 618vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm 619vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm 620vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm 621vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm 622vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm 623vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm 624vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm 625vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm 626vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm 627vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm 628vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm 629vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm 630vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm 631vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm 632vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm 633vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm 634vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm 635vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm 636vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm 637vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm 638vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm 639vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm 640vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm 641vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm 642vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm 643vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm 644vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm 645vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm 646vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm 647vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm 648vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm 649vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm 650vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm 651vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm 652vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm 653vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm 654vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm 655vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm 656vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm 657vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm 658vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 659vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 660 661vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm 662vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm 663vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm 664vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm 665vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm 666vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm 667 668vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm 669vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm 670vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm 671vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm 672vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm 673vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm 674vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm 675 676vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm 677vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm 678vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm 679vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm 680vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm 681vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm 682vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm 683vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm 684 685vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm 686vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm 687vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm 688vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm 689vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm 690vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm 691vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm 692vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm 693vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm 694vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm 695# Vector ordered and unordered reduction sum 696vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm 697vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm 698vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm 699vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm 700# Vector widening ordered and unordered float reduction sum 701vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm 702vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm 703vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r 704vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r 705vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r 706vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r 707vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r 708vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r 709vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r 710vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r 711vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm 712vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm 713vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm 714vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm 715vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm 716viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm 717vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm 718vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd 719vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 720vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd 721vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 722vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm 723vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm 724vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm 725vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm 726vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm 727vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm 728vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm 729vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm 730vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm 731vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm 732vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r 733vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd 734vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd 735vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd 736vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd 737 738# Vector Integer Extension 739vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm 740vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm 741vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm 742vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm 743vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm 744vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm 745 746vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 747vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 748vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 749 750# *** Zawrs Standard Extension *** 751wrs_nto 000000001101 00000 000 00000 1110011 752wrs_sto 000000011101 00000 000 00000 1110011 753 754# *** RV32 Zba Standard Extension *** 755sh1add 0010000 .......... 010 ..... 0110011 @r 756sh2add 0010000 .......... 100 ..... 0110011 @r 757sh3add 0010000 .......... 110 ..... 0110011 @r 758 759# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** 760add_uw 0000100 .......... 000 ..... 0111011 @r 761sh1add_uw 0010000 .......... 010 ..... 0111011 @r 762sh2add_uw 0010000 .......... 100 ..... 0111011 @r 763sh3add_uw 0010000 .......... 110 ..... 0111011 @r 764slli_uw 00001 ............ 001 ..... 0011011 @sh 765 766# *** RV32 Zbb/Zbkb Standard Extension *** 767andn 0100000 .......... 111 ..... 0110011 @r 768rol 0110000 .......... 001 ..... 0110011 @r 769ror 0110000 .......... 101 ..... 0110011 @r 770rori 01100 ............ 101 ..... 0010011 @sh 771# The encoding for rev8 differs between RV32 and RV64. 772# rev8_32 denotes the RV32 variant. 773rev8_32 011010 011000 ..... 101 ..... 0010011 @r2 774# The encoding for zext.h differs between RV32 and RV64. 775# zext_h_32 denotes the RV32 variant. 776{ 777 zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 778 pack 0000100 ..... ..... 100 ..... 0110011 @r 779} 780xnor 0100000 .......... 100 ..... 0110011 @r 781# *** RV32 extra Zbb Standard Extension *** 782clz 011000 000000 ..... 001 ..... 0010011 @r2 783cpop 011000 000010 ..... 001 ..... 0010011 @r2 784ctz 011000 000001 ..... 001 ..... 0010011 @r2 785max 0000101 .......... 110 ..... 0110011 @r 786maxu 0000101 .......... 111 ..... 0110011 @r 787min 0000101 .......... 100 ..... 0110011 @r 788minu 0000101 .......... 101 ..... 0110011 @r 789orc_b 001010 000111 ..... 101 ..... 0010011 @r2 790orn 0100000 .......... 110 ..... 0110011 @r 791sext_b 011000 000100 ..... 001 ..... 0010011 @r2 792sext_h 011000 000101 ..... 001 ..... 0010011 @r2 793# *** RV32 extra Zbkb Standard Extension *** 794brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi 795packh 0000100 .......... 111 ..... 0110011 @r 796unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl 797zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl 798 799# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) *** 800# The encoding for rev8 differs between RV32 and RV64. 801# When executing on RV64, the encoding used in RV32 is an illegal 802# instruction, so we use different handler functions to differentiate. 803rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 804rolw 0110000 .......... 001 ..... 0111011 @r 805roriw 0110000 .......... 101 ..... 0011011 @sh5 806rorw 0110000 .......... 101 ..... 0111011 @r 807# The encoding for zext.h differs between RV32 and RV64. 808# When executing on RV64, the encoding used in RV32 is an illegal 809# instruction, so we use different handler functions to differentiate. 810{ 811 zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 812 packw 0000100 ..... ..... 100 ..... 0111011 @r 813} 814# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) *** 815clzw 0110000 00000 ..... 001 ..... 0011011 @r2 816ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 817cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 818 819# *** RV32 Zbc/Zbkc Standard Extension *** 820clmul 0000101 .......... 001 ..... 0110011 @r 821clmulh 0000101 .......... 011 ..... 0110011 @r 822# *** RV32 extra Zbc Standard Extension *** 823clmulr 0000101 .......... 010 ..... 0110011 @r 824 825# *** RV32 Zbkx Standard Extension *** 826xperm4 0010100 .......... 010 ..... 0110011 @r 827xperm8 0010100 .......... 100 ..... 0110011 @r 828 829# *** RV32 Zbs Standard Extension *** 830bclr 0100100 .......... 001 ..... 0110011 @r 831bclri 01001. ........... 001 ..... 0010011 @sh 832bext 0100100 .......... 101 ..... 0110011 @r 833bexti 01001. ........... 101 ..... 0010011 @sh 834binv 0110100 .......... 001 ..... 0110011 @r 835binvi 01101. ........... 001 ..... 0010011 @sh 836bset 0010100 .......... 001 ..... 0110011 @r 837bseti 00101. ........... 001 ..... 0010011 @sh 838 839# *** Zfa Standard Extension *** 840fli_s 1111000 00001 ..... 000 ..... 1010011 @r2 841fli_d 1111001 00001 ..... 000 ..... 1010011 @r2 842fli_h 1111010 00001 ..... 000 ..... 1010011 @r2 843fminm_s 0010100 ..... ..... 010 ..... 1010011 @r 844fmaxm_s 0010100 ..... ..... 011 ..... 1010011 @r 845fminm_d 0010101 ..... ..... 010 ..... 1010011 @r 846fmaxm_d 0010101 ..... ..... 011 ..... 1010011 @r 847fminm_h 0010110 ..... ..... 010 ..... 1010011 @r 848fmaxm_h 0010110 ..... ..... 011 ..... 1010011 @r 849fround_s 0100000 00100 ..... ... ..... 1010011 @r2_rm 850froundnx_s 0100000 00101 ..... ... ..... 1010011 @r2_rm 851fround_d 0100001 00100 ..... ... ..... 1010011 @r2_rm 852froundnx_d 0100001 00101 ..... ... ..... 1010011 @r2_rm 853fround_h 0100010 00100 ..... ... ..... 1010011 @r2_rm 854froundnx_h 0100010 00101 ..... ... ..... 1010011 @r2_rm 855fcvtmod_w_d 1100001 01000 ..... 001 ..... 1010011 @r2 856fmvh_x_d 1110001 00001 ..... 000 ..... 1010011 @r2 857fmvp_d_x 1011001 ..... ..... 000 ..... 1010011 @r 858fleq_s 1010000 ..... ..... 100 ..... 1010011 @r 859fltq_s 1010000 ..... ..... 101 ..... 1010011 @r 860fleq_d 1010001 ..... ..... 100 ..... 1010011 @r 861fltq_d 1010001 ..... ..... 101 ..... 1010011 @r 862fleq_h 1010010 ..... ..... 100 ..... 1010011 @r 863fltq_h 1010010 ..... ..... 101 ..... 1010011 @r 864 865# *** RV32 Zfh Extension *** 866flh ............ ..... 001 ..... 0000111 @i 867fsh ....... ..... ..... 001 ..... 0100111 @s 868fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm 869fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm 870fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm 871fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm 872fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm 873fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm 874fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm 875fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm 876fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm 877fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r 878fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r 879fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r 880fmin_h 0010110 ..... ..... 000 ..... 1010011 @r 881fmax_h 0010110 ..... ..... 001 ..... 1010011 @r 882fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm 883fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm 884fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm 885fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm 886fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm 887fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm 888fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 889feq_h 1010010 ..... ..... 010 ..... 1010011 @r 890flt_h 1010010 ..... ..... 001 ..... 1010011 @r 891fle_h 1010010 ..... ..... 000 ..... 1010011 @r 892fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 893fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm 894fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm 895fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 896 897# *** RV64 Zfh Extension (in addition to RV32 Zfh) *** 898fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm 899fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm 900fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm 901fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm 902 903# *** Svinval Standard Extension *** 904sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma 905sfence_w_inval 0001100 00000 00000 000 00000 1110011 906sfence_inval_ir 0001100 00001 00000 000 00000 1110011 907hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma 908hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma 909 910# *** RV32 Zknd Standard Extension *** 911aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes 912aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes 913# *** RV64 Zknd Standard Extension *** 914aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r 915aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r 916aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2 917# *** RV32 Zkne Standard Extension *** 918aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes 919aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes 920# *** RV64 Zkne Standard Extension *** 921aes64es 00 11001 ..... ..... 000 ..... 0110011 @r 922aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r 923# *** RV64 Zkne/zknd Standard Extension *** 924aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r 925aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes 926# *** RV32 Zknh Standard Extension *** 927sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 928sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 929sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 930sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 931sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r 932sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r 933sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r 934sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r 935sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r 936sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r 937# *** RV64 Zknh Standard Extension *** 938sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2 939sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2 940sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2 941sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2 942# *** RV32 Zksh Standard Extension *** 943sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2 944sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2 945# *** RV32 Zksed Standard Extension *** 946sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes 947sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes 948 949# *** RV32 Zicond Standard Extension *** 950czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r 951czero_nez 0000111 ..... ..... 111 ..... 0110011 @r 952 953# *** Zfbfmin Standard Extension *** 954fcvt_bf16_s 0100010 01000 ..... ... ..... 1010011 @r2_rm 955fcvt_s_bf16 0100000 00110 ..... ... ..... 1010011 @r2_rm 956 957# *** Zvfbfmin Standard Extension *** 958vfncvtbf16_f_f_w 010010 . ..... 11101 001 ..... 1010111 @r2_vm 959vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm 960 961# *** Zvfbfwma Standard Extension *** 962vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm 963vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm 964 965# *** Zvbc vector crypto extension *** 966vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm 967vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm 968vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm 969vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm 970 971# *** Zvbb vector crypto extension *** 972vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm 973vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm 974vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm 975vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm 976vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6 977vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm 978vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm 979vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm 980vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm 981vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm 982vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm 983vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm 984vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm 985vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm 986vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm 987vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm 988 989# *** Zvkned vector crypto extension *** 990vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 991vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 992vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 993vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 994vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 995vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 996vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 997vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 998vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 999vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 1000vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 1001 1002# *** Zvknh vector crypto extension *** 1003vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 1004vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 1005vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 1006 1007# *** Zvksh vector crypto extension *** 1008vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 1009vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 1010 1011# *** Zvkg vector crypto extension *** 1012vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 1013vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 1014 1015# *** Zvksed vector crypto extension *** 1016vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 1017vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 1018vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 1019 1020# *** RV32 Zacas Standard Extension *** 1021amocas_w 00101 . . ..... ..... 010 ..... 0101111 @atom_st 1022amocas_d 00101 . . ..... ..... 011 ..... 0101111 @atom_st 1023# *** RV64 Zacas Standard Extension *** 1024amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st 1025 1026# *** Zimop may-be-operation extension *** 1027{ 1028 # zicfiss instructions carved out of mop.r 1029 [ 1030 ssrdp 1100110 11100 00000 100 rd:5 1110011 1031 sspopchk 1100110 11100 00001 100 00000 1110011 &r2 rs1=1 rd=0 1032 sspopchk 1100110 11100 00101 100 00000 1110011 &r2 rs1=5 rd=0 1033 ] 1034 mop_r_n 1 . 00 .. 0111 .. ..... 100 ..... 1110011 @mop5 1035} 1036{ 1037 # zicfiss instruction carved out of mop.rr 1038 [ 1039 sspush 1100111 00001 00000 100 00000 1110011 &r2_s rs2=1 rs1=0 1040 sspush 1100111 00101 00000 100 00000 1110011 &r2_s rs2=5 rs1=0 1041 ] 1042 mop_rr_n 1 . 00 .. 1 ..... ..... 100 ..... 1110011 @mop3 1043} 1044 1045# *** Zabhb Standard Extension *** 1046amoswap_b 00001 . . ..... ..... 000 ..... 0101111 @atom_st 1047amoadd_b 00000 . . ..... ..... 000 ..... 0101111 @atom_st 1048amoxor_b 00100 . . ..... ..... 000 ..... 0101111 @atom_st 1049amoand_b 01100 . . ..... ..... 000 ..... 0101111 @atom_st 1050amoor_b 01000 . . ..... ..... 000 ..... 0101111 @atom_st 1051amomin_b 10000 . . ..... ..... 000 ..... 0101111 @atom_st 1052amomax_b 10100 . . ..... ..... 000 ..... 0101111 @atom_st 1053amominu_b 11000 . . ..... ..... 000 ..... 0101111 @atom_st 1054amomaxu_b 11100 . . ..... ..... 000 ..... 0101111 @atom_st 1055amoswap_h 00001 . . ..... ..... 001 ..... 0101111 @atom_st 1056amoadd_h 00000 . . ..... ..... 001 ..... 0101111 @atom_st 1057amoxor_h 00100 . . ..... ..... 001 ..... 0101111 @atom_st 1058amoand_h 01100 . . ..... ..... 001 ..... 0101111 @atom_st 1059amoor_h 01000 . . ..... ..... 001 ..... 0101111 @atom_st 1060amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st 1061amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st 1062amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st 1063amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st 1064amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st 1065amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st 1066