1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24%sh5 20:5 25 26%sh7 20:7 27%csr 20:12 28%rm 12:3 29%nf 29:3 !function=ex_plus_1 30 31# immediates: 32%imm_i 20:s12 33%imm_s 25:s7 7:5 34%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 35%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 36%imm_u 12:s20 !function=ex_shift_12 37 38# Argument sets: 39&empty 40&b imm rs2 rs1 41&i imm rs1 rd 42&j imm rd 43&r rd rs1 rs2 44&r2 rd rs1 45&r2_s rs1 rs2 46&s imm rs1 rs2 47&u imm rd 48&shift shamt rs1 rd 49&atomic aq rl rs2 rs1 rd 50&rmrr vm rd rs1 rs2 51&rmr vm rd rs2 52&r2nfvm vm rd rs1 nf 53&rnfvm vm rd rs1 rs2 nf 54 55# Formats 32: 56@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 57@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 58@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 59@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 60@u .................... ..... ....... &u imm=%imm_u %rd 61@j .................... ..... ....... &j imm=%imm_j %rd 62 63@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd 64@csr ............ ..... ... ..... ....... %csr %rs1 %rd 65 66@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 67@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 68 69@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 70@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 71@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 72@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd 73@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 74@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd 75@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd 76@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 77@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd 78@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd 79@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd 80@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd 81@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd 82@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 83 84@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 85@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 86 87@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 88@sfence_vm ....... ..... ..... ... ..... ....... %rs1 89 90# Formats 64: 91@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd 92 93# *** Privileged Instructions *** 94ecall 000000000000 00000 000 00000 1110011 95ebreak 000000000001 00000 000 00000 1110011 96uret 0000000 00010 00000 000 00000 1110011 97sret 0001000 00010 00000 000 00000 1110011 98mret 0011000 00010 00000 000 00000 1110011 99wfi 0001000 00101 00000 000 00000 1110011 100sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 101sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 102 103# *** RV32I Base Instruction Set *** 104lui .................... ..... 0110111 @u 105auipc .................... ..... 0010111 @u 106jal .................... ..... 1101111 @j 107jalr ............ ..... 000 ..... 1100111 @i 108beq ....... ..... ..... 000 ..... 1100011 @b 109bne ....... ..... ..... 001 ..... 1100011 @b 110blt ....... ..... ..... 100 ..... 1100011 @b 111bge ....... ..... ..... 101 ..... 1100011 @b 112bltu ....... ..... ..... 110 ..... 1100011 @b 113bgeu ....... ..... ..... 111 ..... 1100011 @b 114lb ............ ..... 000 ..... 0000011 @i 115lh ............ ..... 001 ..... 0000011 @i 116lw ............ ..... 010 ..... 0000011 @i 117lbu ............ ..... 100 ..... 0000011 @i 118lhu ............ ..... 101 ..... 0000011 @i 119sb ....... ..... ..... 000 ..... 0100011 @s 120sh ....... ..... ..... 001 ..... 0100011 @s 121sw ....... ..... ..... 010 ..... 0100011 @s 122addi ............ ..... 000 ..... 0010011 @i 123slti ............ ..... 010 ..... 0010011 @i 124sltiu ............ ..... 011 ..... 0010011 @i 125xori ............ ..... 100 ..... 0010011 @i 126ori ............ ..... 110 ..... 0010011 @i 127andi ............ ..... 111 ..... 0010011 @i 128slli 00000. ...... ..... 001 ..... 0010011 @sh 129srli 00000. ...... ..... 101 ..... 0010011 @sh 130srai 01000. ...... ..... 101 ..... 0010011 @sh 131add 0000000 ..... ..... 000 ..... 0110011 @r 132sub 0100000 ..... ..... 000 ..... 0110011 @r 133sll 0000000 ..... ..... 001 ..... 0110011 @r 134slt 0000000 ..... ..... 010 ..... 0110011 @r 135sltu 0000000 ..... ..... 011 ..... 0110011 @r 136xor 0000000 ..... ..... 100 ..... 0110011 @r 137srl 0000000 ..... ..... 101 ..... 0110011 @r 138sra 0100000 ..... ..... 101 ..... 0110011 @r 139or 0000000 ..... ..... 110 ..... 0110011 @r 140and 0000000 ..... ..... 111 ..... 0110011 @r 141fence ---- pred:4 succ:4 ----- 000 ----- 0001111 142fence_i ---- ---- ---- ----- 001 ----- 0001111 143csrrw ............ ..... 001 ..... 1110011 @csr 144csrrs ............ ..... 010 ..... 1110011 @csr 145csrrc ............ ..... 011 ..... 1110011 @csr 146csrrwi ............ ..... 101 ..... 1110011 @csr 147csrrsi ............ ..... 110 ..... 1110011 @csr 148csrrci ............ ..... 111 ..... 1110011 @csr 149 150# *** RV64I Base Instruction Set (in addition to RV32I) *** 151lwu ............ ..... 110 ..... 0000011 @i 152ld ............ ..... 011 ..... 0000011 @i 153sd ....... ..... ..... 011 ..... 0100011 @s 154addiw ............ ..... 000 ..... 0011011 @i 155slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 156srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 157sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 158addw 0000000 ..... ..... 000 ..... 0111011 @r 159subw 0100000 ..... ..... 000 ..... 0111011 @r 160sllw 0000000 ..... ..... 001 ..... 0111011 @r 161srlw 0000000 ..... ..... 101 ..... 0111011 @r 162sraw 0100000 ..... ..... 101 ..... 0111011 @r 163 164# *** RV32M Standard Extension *** 165mul 0000001 ..... ..... 000 ..... 0110011 @r 166mulh 0000001 ..... ..... 001 ..... 0110011 @r 167mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 168mulhu 0000001 ..... ..... 011 ..... 0110011 @r 169div 0000001 ..... ..... 100 ..... 0110011 @r 170divu 0000001 ..... ..... 101 ..... 0110011 @r 171rem 0000001 ..... ..... 110 ..... 0110011 @r 172remu 0000001 ..... ..... 111 ..... 0110011 @r 173 174# *** RV64M Standard Extension (in addition to RV32M) *** 175mulw 0000001 ..... ..... 000 ..... 0111011 @r 176divw 0000001 ..... ..... 100 ..... 0111011 @r 177divuw 0000001 ..... ..... 101 ..... 0111011 @r 178remw 0000001 ..... ..... 110 ..... 0111011 @r 179remuw 0000001 ..... ..... 111 ..... 0111011 @r 180 181# *** RV32A Standard Extension *** 182lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 183sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 184amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 185amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 186amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 187amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 188amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 189amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 190amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 191amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 192amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 193 194# *** RV64A Standard Extension (in addition to RV32A) *** 195lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld 196sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st 197amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st 198amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st 199amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st 200amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st 201amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st 202amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st 203amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st 204amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st 205amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st 206 207# *** RV32F Standard Extension *** 208flw ............ ..... 010 ..... 0000111 @i 209fsw ....... ..... ..... 010 ..... 0100111 @s 210fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 211fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 212fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 213fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 214fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 215fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 216fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 217fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 218fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 219fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 220fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 221fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 222fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 223fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 224fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 225fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 226fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 227feq_s 1010000 ..... ..... 010 ..... 1010011 @r 228flt_s 1010000 ..... ..... 001 ..... 1010011 @r 229fle_s 1010000 ..... ..... 000 ..... 1010011 @r 230fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 231fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 232fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 233fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 234 235# *** RV64F Standard Extension (in addition to RV32F) *** 236fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm 237fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm 238fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm 239fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm 240 241# *** RV32D Standard Extension *** 242fld ............ ..... 011 ..... 0000111 @i 243fsd ....... ..... ..... 011 ..... 0100111 @s 244fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 245fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 246fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 247fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 248fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 249fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 250fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 251fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 252fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 253fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 254fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 255fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 256fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 257fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 258fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 259fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 260feq_d 1010001 ..... ..... 010 ..... 1010011 @r 261flt_d 1010001 ..... ..... 001 ..... 1010011 @r 262fle_d 1010001 ..... ..... 000 ..... 1010011 @r 263fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 264fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 265fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 266fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 267fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 268 269# *** RV64D Standard Extension (in addition to RV32D) *** 270fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm 271fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm 272fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 273fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm 274fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm 275fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 276 277# *** RV32H Base Instruction Set *** 278hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 279hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 280hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 281hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 282hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 283hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 284hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 285hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s 286hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s 287hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s 288hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 289hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 290 291# *** RV64H Base Instruction Set *** 292hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 293hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 294hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s 295 296# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 297# Vector unit-stride load/store insns. 298vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 299vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 300vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 301vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 302vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 303vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 304vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 305vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 306 307# Vector strided insns. 308vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 309vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 310vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 311vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 312vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 313vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 314vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 315vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 316 317# Vector ordered-indexed and unordered-indexed load insns. 318vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm 319vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm 320vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm 321vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm 322 323# Vector ordered-indexed and unordered-indexed store insns. 324vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm 325vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm 326vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm 327vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm 328 329# Vector unit-stride fault-only-first load insns. 330vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 331vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 332vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 333vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 334 335# Vector whole register insns 336vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 337vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2 338vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2 339vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2 340vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2 341vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2 342vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2 343vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2 344vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2 345vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2 346vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2 347vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2 348vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2 349vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2 350vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2 351vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2 352vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 353vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2 354vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2 355vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2 356 357# *** new major opcode OP-V *** 358vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm 359vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm 360vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm 361vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm 362vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm 363vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm 364vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm 365vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm 366vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm 367vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm 368vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm 369vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm 370vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm 371vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm 372vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm 373vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm 374vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm 375vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm 376vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm 377vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm 378vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm 379vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm 380vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm 381vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 382vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 383vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 384vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm 385vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm 386vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm 387vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 388vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 389vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm 390vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm 391vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm 392vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm 393vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm 394vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm 395vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm 396vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm 397vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm 398vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm 399vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm 400vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm 401vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm 402vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm 403vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm 404vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm 405vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm 406vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm 407vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm 408vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm 409vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm 410vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm 411vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm 412vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm 413vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm 414vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm 415vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm 416vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm 417vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm 418vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm 419vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm 420vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm 421vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm 422vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm 423vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm 424vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm 425vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm 426vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm 427vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm 428vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm 429vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm 430vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm 431vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm 432vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm 433vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm 434vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm 435vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm 436vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm 437vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm 438vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm 439vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm 440vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm 441vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm 442vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm 443vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm 444vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm 445vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm 446vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm 447vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm 448vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm 449vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm 450vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm 451vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm 452vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm 453vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm 454vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm 455vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm 456vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm 457vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm 458vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm 459vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm 460vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm 461vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm 462vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm 463vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm 464vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm 465vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm 466vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm 467vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm 468vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm 469vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm 470vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm 471vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm 472vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm 473vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm 474vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm 475vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm 476vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm 477vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm 478vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm 479vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm 480vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 481vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 482vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 483vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 484vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 485vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 486vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm 487vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm 488vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm 489vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm 490vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm 491vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm 492vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm 493vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm 494vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm 495vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm 496vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm 497vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm 498vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm 499vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm 500vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm 501vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm 502vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm 503vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm 504vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm 505vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm 506vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm 507vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm 508vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm 509vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm 510vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm 511vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm 512vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm 513vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm 514vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm 515vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm 516vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm 517vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm 518vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm 519vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm 520vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm 521vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm 522vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm 523vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm 524vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm 525vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm 526vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm 527vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm 528vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm 529vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm 530vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm 531vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm 532vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm 533vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm 534vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm 535vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm 536vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm 537vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm 538vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm 539vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm 540vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm 541vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm 542vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm 543vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm 544vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm 545vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm 546vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm 547vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm 548vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm 549vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm 550vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm 551vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm 552vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm 553vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm 554vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm 555vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm 556vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm 557vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm 558vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm 559vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm 560vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm 561vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm 562vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm 563vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm 564vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm 565vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm 566vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm 567vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm 568vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm 569vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm 570vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm 571vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm 572vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm 573vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm 574vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm 575vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm 576vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm 577vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm 578vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm 579vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm 580vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm 581vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm 582vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm 583vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm 584vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm 585vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm 586vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm 587vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm 588vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 589vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 590 591vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm 592vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm 593vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm 594vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm 595vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm 596vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm 597 598vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm 599vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm 600vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm 601vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm 602vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm 603vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm 604vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm 605 606vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm 607vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm 608vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm 609vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm 610vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm 611vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm 612vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm 613vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm 614 615vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm 616vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm 617vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm 618vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm 619vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm 620vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm 621vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm 622vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm 623vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm 624vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm 625# Vector ordered and unordered reduction sum 626vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm 627vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm 628vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm 629# Vector widening ordered and unordered float reduction sum 630vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm 631vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r 632vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r 633vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r 634vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r 635vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r 636vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r 637vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r 638vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r 639vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm 640vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm 641vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm 642vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm 643vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm 644viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm 645vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm 646vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd 647vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 648vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd 649vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 650vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm 651vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm 652vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm 653vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm 654vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm 655vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm 656vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm 657vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm 658vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm 659vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm 660vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r 661vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd 662vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd 663vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd 664vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd 665 666# Vector Integer Extension 667vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm 668vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm 669vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm 670vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm 671vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm 672vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm 673 674vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 675vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 676 677# *** RV32 Zba Standard Extension *** 678sh1add 0010000 .......... 010 ..... 0110011 @r 679sh2add 0010000 .......... 100 ..... 0110011 @r 680sh3add 0010000 .......... 110 ..... 0110011 @r 681 682# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** 683add_uw 0000100 .......... 000 ..... 0111011 @r 684sh1add_uw 0010000 .......... 010 ..... 0111011 @r 685sh2add_uw 0010000 .......... 100 ..... 0111011 @r 686sh3add_uw 0010000 .......... 110 ..... 0111011 @r 687slli_uw 00001 ............ 001 ..... 0011011 @sh 688 689# *** RV32 Zbb Standard Extension *** 690andn 0100000 .......... 111 ..... 0110011 @r 691clz 011000 000000 ..... 001 ..... 0010011 @r2 692cpop 011000 000010 ..... 001 ..... 0010011 @r2 693ctz 011000 000001 ..... 001 ..... 0010011 @r2 694max 0000101 .......... 110 ..... 0110011 @r 695maxu 0000101 .......... 111 ..... 0110011 @r 696min 0000101 .......... 100 ..... 0110011 @r 697minu 0000101 .......... 101 ..... 0110011 @r 698orc_b 001010 000111 ..... 101 ..... 0010011 @r2 699orn 0100000 .......... 110 ..... 0110011 @r 700# The encoding for rev8 differs between RV32 and RV64. 701# rev8_32 denotes the RV32 variant. 702rev8_32 011010 011000 ..... 101 ..... 0010011 @r2 703rol 0110000 .......... 001 ..... 0110011 @r 704ror 0110000 .......... 101 ..... 0110011 @r 705rori 01100 ............ 101 ..... 0010011 @sh 706sext_b 011000 000100 ..... 001 ..... 0010011 @r2 707sext_h 011000 000101 ..... 001 ..... 0010011 @r2 708xnor 0100000 .......... 100 ..... 0110011 @r 709# The encoding for zext.h differs between RV32 and RV64. 710# zext_h_32 denotes the RV32 variant. 711zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 712 713# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** 714clzw 0110000 00000 ..... 001 ..... 0011011 @r2 715ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 716cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 717# The encoding for rev8 differs between RV32 and RV64. 718# When executing on RV64, the encoding used in RV32 is an illegal 719# instruction, so we use different handler functions to differentiate. 720rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 721rolw 0110000 .......... 001 ..... 0111011 @r 722roriw 0110000 .......... 101 ..... 0011011 @sh5 723rorw 0110000 .......... 101 ..... 0111011 @r 724# The encoding for zext.h differs between RV32 and RV64. 725# When executing on RV64, the encoding used in RV32 is an illegal 726# instruction, so we use different handler functions to differentiate. 727zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 728 729# *** RV32 Zbc Standard Extension *** 730clmul 0000101 .......... 001 ..... 0110011 @r 731clmulh 0000101 .......... 011 ..... 0110011 @r 732clmulr 0000101 .......... 010 ..... 0110011 @r 733 734# *** RV32 Zbs Standard Extension *** 735bclr 0100100 .......... 001 ..... 0110011 @r 736bclri 01001. ........... 001 ..... 0010011 @sh 737bext 0100100 .......... 101 ..... 0110011 @r 738bexti 01001. ........... 101 ..... 0010011 @sh 739binv 0110100 .......... 001 ..... 0110011 @r 740binvi 01101. ........... 001 ..... 0010011 @sh 741bset 0010100 .......... 001 ..... 0110011 @r 742bseti 00101. ........... 001 ..... 0010011 @sh 743 744# *** RV32 Zfh Extension *** 745flh ............ ..... 001 ..... 0000111 @i 746fsh ....... ..... ..... 001 ..... 0100111 @s 747fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm 748fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm 749fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm 750fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm 751fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm 752fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm 753fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm 754fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm 755fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm 756fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r 757fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r 758fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r 759fmin_h 0010110 ..... ..... 000 ..... 1010011 @r 760fmax_h 0010110 ..... ..... 001 ..... 1010011 @r 761fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm 762fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm 763fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm 764fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm 765fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm 766fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm 767fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 768feq_h 1010010 ..... ..... 010 ..... 1010011 @r 769flt_h 1010010 ..... ..... 001 ..... 1010011 @r 770fle_h 1010010 ..... ..... 000 ..... 1010011 @r 771fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 772fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm 773fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm 774fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 775 776# *** RV64 Zfh Extension (in addition to RV32 Zfh) *** 777fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm 778fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm 779fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm 780fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm 781