1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24 25%sh10 20:10 26%csr 20:12 27%rm 12:3 28%nf 29:3 !function=ex_plus_1 29 30# immediates: 31%imm_i 20:s12 32%imm_s 25:s7 7:5 33%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 34%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 35%imm_u 12:s20 !function=ex_shift_12 36 37# Argument sets: 38&empty 39&b imm rs2 rs1 40&i imm rs1 rd 41&j imm rd 42&r rd rs1 rs2 43&s imm rs1 rs2 44&u imm rd 45&shift shamt rs1 rd 46&atomic aq rl rs2 rs1 rd 47&rmrr vm rd rs1 rs2 48&rwdvm vm wd rd rs1 rs2 49&r2nfvm vm rd rs1 nf 50&rnfvm vm rd rs1 rs2 nf 51 52# Formats 32: 53@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 54@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 55@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 56@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 57@u .................... ..... ....... &u imm=%imm_u %rd 58@j .................... ..... ....... &j imm=%imm_j %rd 59 60@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd 61@csr ............ ..... ... ..... ....... %csr %rs1 %rd 62 63@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 64@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 65 66@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 67@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 68@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 69@r2 ....... ..... ..... ... ..... ....... %rs1 %rd 70@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 71@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 72@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd 73@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd 74@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd 75 76@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 77@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 78 79@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 80@sfence_vm ....... ..... ..... ... ..... ....... %rs1 81 82 83# *** Privileged Instructions *** 84ecall 000000000000 00000 000 00000 1110011 85ebreak 000000000001 00000 000 00000 1110011 86uret 0000000 00010 00000 000 00000 1110011 87sret 0001000 00010 00000 000 00000 1110011 88mret 0011000 00010 00000 000 00000 1110011 89wfi 0001000 00101 00000 000 00000 1110011 90sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 91sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 92 93# *** RV32I Base Instruction Set *** 94lui .................... ..... 0110111 @u 95auipc .................... ..... 0010111 @u 96jal .................... ..... 1101111 @j 97jalr ............ ..... 000 ..... 1100111 @i 98beq ....... ..... ..... 000 ..... 1100011 @b 99bne ....... ..... ..... 001 ..... 1100011 @b 100blt ....... ..... ..... 100 ..... 1100011 @b 101bge ....... ..... ..... 101 ..... 1100011 @b 102bltu ....... ..... ..... 110 ..... 1100011 @b 103bgeu ....... ..... ..... 111 ..... 1100011 @b 104lb ............ ..... 000 ..... 0000011 @i 105lh ............ ..... 001 ..... 0000011 @i 106lw ............ ..... 010 ..... 0000011 @i 107lbu ............ ..... 100 ..... 0000011 @i 108lhu ............ ..... 101 ..... 0000011 @i 109sb ....... ..... ..... 000 ..... 0100011 @s 110sh ....... ..... ..... 001 ..... 0100011 @s 111sw ....... ..... ..... 010 ..... 0100011 @s 112addi ............ ..... 000 ..... 0010011 @i 113slti ............ ..... 010 ..... 0010011 @i 114sltiu ............ ..... 011 ..... 0010011 @i 115xori ............ ..... 100 ..... 0010011 @i 116ori ............ ..... 110 ..... 0010011 @i 117andi ............ ..... 111 ..... 0010011 @i 118slli 00.... ...... ..... 001 ..... 0010011 @sh 119srli 00.... ...... ..... 101 ..... 0010011 @sh 120srai 01.... ...... ..... 101 ..... 0010011 @sh 121add 0000000 ..... ..... 000 ..... 0110011 @r 122sub 0100000 ..... ..... 000 ..... 0110011 @r 123sll 0000000 ..... ..... 001 ..... 0110011 @r 124slt 0000000 ..... ..... 010 ..... 0110011 @r 125sltu 0000000 ..... ..... 011 ..... 0110011 @r 126xor 0000000 ..... ..... 100 ..... 0110011 @r 127srl 0000000 ..... ..... 101 ..... 0110011 @r 128sra 0100000 ..... ..... 101 ..... 0110011 @r 129or 0000000 ..... ..... 110 ..... 0110011 @r 130and 0000000 ..... ..... 111 ..... 0110011 @r 131fence ---- pred:4 succ:4 ----- 000 ----- 0001111 132fence_i ---- ---- ---- ----- 001 ----- 0001111 133csrrw ............ ..... 001 ..... 1110011 @csr 134csrrs ............ ..... 010 ..... 1110011 @csr 135csrrc ............ ..... 011 ..... 1110011 @csr 136csrrwi ............ ..... 101 ..... 1110011 @csr 137csrrsi ............ ..... 110 ..... 1110011 @csr 138csrrci ............ ..... 111 ..... 1110011 @csr 139 140# *** RV32M Standard Extension *** 141mul 0000001 ..... ..... 000 ..... 0110011 @r 142mulh 0000001 ..... ..... 001 ..... 0110011 @r 143mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 144mulhu 0000001 ..... ..... 011 ..... 0110011 @r 145div 0000001 ..... ..... 100 ..... 0110011 @r 146divu 0000001 ..... ..... 101 ..... 0110011 @r 147rem 0000001 ..... ..... 110 ..... 0110011 @r 148remu 0000001 ..... ..... 111 ..... 0110011 @r 149 150# *** RV32A Standard Extension *** 151lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 152sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 153amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 154amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 155amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 156amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 157amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 158amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 159amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 160amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 161amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 162 163# *** RV32F Standard Extension *** 164flw ............ ..... 010 ..... 0000111 @i 165fsw ....... ..... ..... 010 ..... 0100111 @s 166fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 167fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 168fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 169fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 170fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 171fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 172fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 173fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 174fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 175fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 176fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 177fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 178fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 179fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 180fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 181fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 182fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 183feq_s 1010000 ..... ..... 010 ..... 1010011 @r 184flt_s 1010000 ..... ..... 001 ..... 1010011 @r 185fle_s 1010000 ..... ..... 000 ..... 1010011 @r 186fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 187fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 188fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 189fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 190 191# *** RV32D Standard Extension *** 192fld ............ ..... 011 ..... 0000111 @i 193fsd ....... ..... ..... 011 ..... 0100111 @s 194fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 195fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 196fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 197fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 198fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 199fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 200fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 201fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 202fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 203fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 204fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 205fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 206fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 207fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 208fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 209fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 210feq_d 1010001 ..... ..... 010 ..... 1010011 @r 211flt_d 1010001 ..... ..... 001 ..... 1010011 @r 212fle_d 1010001 ..... ..... 000 ..... 1010011 @r 213fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 214fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 215fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 216fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 217fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 218 219# *** RV32H Base Instruction Set *** 220hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 221hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 222 223# *** RV32V Extension *** 224 225# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 226vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm 227vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm 228vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm 229vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 230vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 231vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 232vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 233vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm 234vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm 235vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm 236vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 237vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 238vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 239vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 240vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 241vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 242vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 243vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 244 245vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm 246vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm 247vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm 248vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 249vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 250vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 251vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 252vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 253vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 254vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 255vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 256 257vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm 258vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm 259vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm 260vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm 261vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm 262vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm 263vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm 264# Vector ordered-indexed and unordered-indexed store insns. 265vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm 266vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm 267vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm 268vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm 269 270#*** Vector AMO operations are encoded under the standard AMO major opcode *** 271vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm 272vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm 273vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm 274vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm 275vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm 276vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm 277vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm 278vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm 279vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm 280 281# *** new major opcode OP-V *** 282vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm 283vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm 284vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm 285vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm 286vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm 287vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm 288vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm 289 290vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm 291vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 292