1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24%sh5 20:5 25 26%sh7 20:7 27%csr 20:12 28%rm 12:3 29%nf 29:3 !function=ex_plus_1 30 31# immediates: 32%imm_i 20:s12 33%imm_s 25:s7 7:5 34%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 35%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 36%imm_u 12:s20 !function=ex_shift_12 37 38# Argument sets: 39&empty 40&b imm rs2 rs1 41&i imm rs1 rd 42&j imm rd 43&r rd rs1 rs2 44&r2 rd rs1 45&r2_s rs1 rs2 46&s imm rs1 rs2 47&u imm rd 48&shift shamt rs1 rd 49&atomic aq rl rs2 rs1 rd 50&rmrr vm rd rs1 rs2 51&rmr vm rd rs2 52&r2nfvm vm rd rs1 nf 53&rnfvm vm rd rs1 rs2 nf 54 55# Formats 32: 56@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 57@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 58@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 59@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 60@u .................... ..... ....... &u imm=%imm_u %rd 61@j .................... ..... ....... &j imm=%imm_j %rd 62 63@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd 64@csr ............ ..... ... ..... ....... %csr %rs1 %rd 65 66@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 67@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 68 69@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 70@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 71@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 72@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd 73@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 74@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd 75@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd 76@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 77@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd 78@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd 79@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd 80@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd 81@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd 82@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd 83@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 84 85@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 86@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 87 88@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 89@sfence_vm ....... ..... ..... ... ..... ....... %rs1 90 91# Formats 64: 92@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd 93 94# *** Privileged Instructions *** 95ecall 000000000000 00000 000 00000 1110011 96ebreak 000000000001 00000 000 00000 1110011 97uret 0000000 00010 00000 000 00000 1110011 98sret 0001000 00010 00000 000 00000 1110011 99mret 0011000 00010 00000 000 00000 1110011 100wfi 0001000 00101 00000 000 00000 1110011 101sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 102sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 103 104# *** RV32I Base Instruction Set *** 105lui .................... ..... 0110111 @u 106auipc .................... ..... 0010111 @u 107jal .................... ..... 1101111 @j 108jalr ............ ..... 000 ..... 1100111 @i 109beq ....... ..... ..... 000 ..... 1100011 @b 110bne ....... ..... ..... 001 ..... 1100011 @b 111blt ....... ..... ..... 100 ..... 1100011 @b 112bge ....... ..... ..... 101 ..... 1100011 @b 113bltu ....... ..... ..... 110 ..... 1100011 @b 114bgeu ....... ..... ..... 111 ..... 1100011 @b 115lb ............ ..... 000 ..... 0000011 @i 116lh ............ ..... 001 ..... 0000011 @i 117lw ............ ..... 010 ..... 0000011 @i 118lbu ............ ..... 100 ..... 0000011 @i 119lhu ............ ..... 101 ..... 0000011 @i 120sb ....... ..... ..... 000 ..... 0100011 @s 121sh ....... ..... ..... 001 ..... 0100011 @s 122sw ....... ..... ..... 010 ..... 0100011 @s 123addi ............ ..... 000 ..... 0010011 @i 124slti ............ ..... 010 ..... 0010011 @i 125sltiu ............ ..... 011 ..... 0010011 @i 126xori ............ ..... 100 ..... 0010011 @i 127ori ............ ..... 110 ..... 0010011 @i 128andi ............ ..... 111 ..... 0010011 @i 129slli 00000. ...... ..... 001 ..... 0010011 @sh 130srli 00000. ...... ..... 101 ..... 0010011 @sh 131srai 01000. ...... ..... 101 ..... 0010011 @sh 132add 0000000 ..... ..... 000 ..... 0110011 @r 133sub 0100000 ..... ..... 000 ..... 0110011 @r 134sll 0000000 ..... ..... 001 ..... 0110011 @r 135slt 0000000 ..... ..... 010 ..... 0110011 @r 136sltu 0000000 ..... ..... 011 ..... 0110011 @r 137xor 0000000 ..... ..... 100 ..... 0110011 @r 138srl 0000000 ..... ..... 101 ..... 0110011 @r 139sra 0100000 ..... ..... 101 ..... 0110011 @r 140or 0000000 ..... ..... 110 ..... 0110011 @r 141and 0000000 ..... ..... 111 ..... 0110011 @r 142fence ---- pred:4 succ:4 ----- 000 ----- 0001111 143fence_i ---- ---- ---- ----- 001 ----- 0001111 144csrrw ............ ..... 001 ..... 1110011 @csr 145csrrs ............ ..... 010 ..... 1110011 @csr 146csrrc ............ ..... 011 ..... 1110011 @csr 147csrrwi ............ ..... 101 ..... 1110011 @csr 148csrrsi ............ ..... 110 ..... 1110011 @csr 149csrrci ............ ..... 111 ..... 1110011 @csr 150 151# *** RV64I Base Instruction Set (in addition to RV32I) *** 152lwu ............ ..... 110 ..... 0000011 @i 153ld ............ ..... 011 ..... 0000011 @i 154sd ....... ..... ..... 011 ..... 0100011 @s 155addiw ............ ..... 000 ..... 0011011 @i 156slliw 0000000 ..... ..... 001 ..... 0011011 @sh5 157srliw 0000000 ..... ..... 101 ..... 0011011 @sh5 158sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5 159addw 0000000 ..... ..... 000 ..... 0111011 @r 160subw 0100000 ..... ..... 000 ..... 0111011 @r 161sllw 0000000 ..... ..... 001 ..... 0111011 @r 162srlw 0000000 ..... ..... 101 ..... 0111011 @r 163sraw 0100000 ..... ..... 101 ..... 0111011 @r 164 165# *** RV32M Standard Extension *** 166mul 0000001 ..... ..... 000 ..... 0110011 @r 167mulh 0000001 ..... ..... 001 ..... 0110011 @r 168mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 169mulhu 0000001 ..... ..... 011 ..... 0110011 @r 170div 0000001 ..... ..... 100 ..... 0110011 @r 171divu 0000001 ..... ..... 101 ..... 0110011 @r 172rem 0000001 ..... ..... 110 ..... 0110011 @r 173remu 0000001 ..... ..... 111 ..... 0110011 @r 174 175# *** RV64M Standard Extension (in addition to RV32M) *** 176mulw 0000001 ..... ..... 000 ..... 0111011 @r 177divw 0000001 ..... ..... 100 ..... 0111011 @r 178divuw 0000001 ..... ..... 101 ..... 0111011 @r 179remw 0000001 ..... ..... 110 ..... 0111011 @r 180remuw 0000001 ..... ..... 111 ..... 0111011 @r 181 182# *** RV32A Standard Extension *** 183lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 184sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 185amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 186amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 187amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 188amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 189amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 190amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 191amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 192amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 193amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 194 195# *** RV64A Standard Extension (in addition to RV32A) *** 196lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld 197sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st 198amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st 199amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st 200amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st 201amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st 202amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st 203amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st 204amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st 205amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st 206amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st 207 208# *** RV32F Standard Extension *** 209flw ............ ..... 010 ..... 0000111 @i 210fsw ....... ..... ..... 010 ..... 0100111 @s 211fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 212fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 213fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 214fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 215fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 216fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 217fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 218fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 219fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 220fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 221fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 222fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 223fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 224fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 225fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 226fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 227fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 228feq_s 1010000 ..... ..... 010 ..... 1010011 @r 229flt_s 1010000 ..... ..... 001 ..... 1010011 @r 230fle_s 1010000 ..... ..... 000 ..... 1010011 @r 231fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 232fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 233fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 234fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 235 236# *** RV64F Standard Extension (in addition to RV32F) *** 237fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm 238fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm 239fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm 240fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm 241 242# *** RV32D Standard Extension *** 243fld ............ ..... 011 ..... 0000111 @i 244fsd ....... ..... ..... 011 ..... 0100111 @s 245fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 246fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 247fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 248fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 249fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 250fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 251fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 252fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 253fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 254fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 255fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 256fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 257fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 258fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 259fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 260fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 261feq_d 1010001 ..... ..... 010 ..... 1010011 @r 262flt_d 1010001 ..... ..... 001 ..... 1010011 @r 263fle_d 1010001 ..... ..... 000 ..... 1010011 @r 264fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 265fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 266fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 267fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 268fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 269 270# *** RV64D Standard Extension (in addition to RV32D) *** 271fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm 272fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm 273fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2 274fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm 275fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm 276fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2 277 278# *** RV32H Base Instruction Set *** 279hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2 280hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2 281hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2 282hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2 283hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2 284hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2 285hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2 286hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s 287hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s 288hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s 289hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 290hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 291 292# *** RV64H Base Instruction Set *** 293hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2 294hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 295hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s 296 297# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 298# Vector unit-stride load/store insns. 299vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 300vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 301vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 302vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 303vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 304vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 305vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 306vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 307 308# Vector strided insns. 309vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 310vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 311vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 312vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 313vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 314vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 315vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 316vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 317 318# Vector ordered-indexed and unordered-indexed load insns. 319vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm 320vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm 321vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm 322vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm 323 324# Vector ordered-indexed and unordered-indexed store insns. 325vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm 326vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm 327vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm 328vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm 329 330# Vector unit-stride fault-only-first load insns. 331vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 332vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 333vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 334vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 335 336# Vector whole register insns 337vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 338vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2 339vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2 340vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2 341vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2 342vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2 343vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2 344vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2 345vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2 346vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2 347vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2 348vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2 349vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2 350vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2 351vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2 352vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2 353vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 354vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2 355vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2 356vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2 357 358# *** new major opcode OP-V *** 359vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm 360vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm 361vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm 362vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm 363vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm 364vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm 365vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm 366vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm 367vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm 368vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm 369vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm 370vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm 371vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm 372vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm 373vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm 374vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm 375vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm 376vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm 377vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm 378vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm 379vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm 380vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm 381vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm 382vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 383vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 384vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 385vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm 386vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm 387vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm 388vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 389vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 390vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm 391vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm 392vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm 393vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm 394vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm 395vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm 396vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm 397vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm 398vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm 399vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm 400vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm 401vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm 402vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm 403vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm 404vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm 405vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm 406vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm 407vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm 408vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm 409vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm 410vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm 411vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm 412vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm 413vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm 414vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm 415vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm 416vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm 417vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm 418vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm 419vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm 420vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm 421vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm 422vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm 423vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm 424vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm 425vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm 426vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm 427vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm 428vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm 429vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm 430vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm 431vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm 432vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm 433vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm 434vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm 435vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm 436vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm 437vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm 438vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm 439vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm 440vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm 441vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm 442vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm 443vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm 444vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm 445vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm 446vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm 447vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm 448vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm 449vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm 450vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm 451vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm 452vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm 453vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm 454vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm 455vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm 456vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm 457vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm 458vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm 459vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm 460vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm 461vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm 462vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm 463vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm 464vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm 465vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm 466vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm 467vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm 468vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm 469vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm 470vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm 471vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm 472vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm 473vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm 474vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm 475vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm 476vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm 477vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm 478vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm 479vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm 480vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm 481vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 482vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 483vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 484vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 485vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 486vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 487vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm 488vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm 489vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm 490vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm 491vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm 492vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm 493vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm 494vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm 495vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm 496vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm 497vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm 498vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm 499vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm 500vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm 501vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm 502vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm 503vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm 504vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm 505vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm 506vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm 507vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm 508vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm 509vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm 510vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm 511vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm 512vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm 513vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm 514vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm 515vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm 516vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm 517vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm 518vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm 519vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm 520vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm 521vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm 522vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm 523vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm 524vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm 525vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm 526vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm 527vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm 528vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm 529vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm 530vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm 531vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm 532vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm 533vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm 534vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm 535vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm 536vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm 537vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm 538vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm 539vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm 540vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm 541vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm 542vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm 543vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm 544vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm 545vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm 546vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm 547vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm 548vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm 549vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm 550vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm 551vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm 552vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm 553vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm 554vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm 555vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm 556vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm 557vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm 558vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm 559vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm 560vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm 561vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm 562vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm 563vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm 564vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm 565vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm 566vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm 567vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm 568vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm 569vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm 570vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm 571vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm 572vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm 573vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm 574vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm 575vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm 576vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm 577vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm 578vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm 579vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm 580vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm 581vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm 582vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm 583vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm 584vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm 585vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm 586vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm 587vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm 588vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm 589vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 590vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 591 592vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm 593vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm 594vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm 595vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm 596vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm 597vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm 598 599vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm 600vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm 601vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm 602vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm 603vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm 604vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm 605vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm 606 607vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm 608vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm 609vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm 610vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm 611vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm 612vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm 613vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm 614vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm 615 616vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm 617vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm 618vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm 619vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm 620vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm 621vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm 622vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm 623vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm 624vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm 625vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm 626# Vector ordered and unordered reduction sum 627vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm 628vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm 629vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm 630# Vector widening ordered and unordered float reduction sum 631vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm 632vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r 633vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r 634vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r 635vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r 636vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r 637vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r 638vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r 639vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r 640vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm 641vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm 642vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm 643vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm 644vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm 645viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm 646vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm 647vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd 648vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 649vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd 650vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 651vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm 652vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm 653vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm 654vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm 655vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm 656vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm 657vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm 658vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm 659vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm 660vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm 661vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r 662vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd 663vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd 664vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd 665vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd 666 667# Vector Integer Extension 668vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm 669vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm 670vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm 671vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm 672vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm 673vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm 674 675vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 676vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 677vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 678 679# *** RV32 Zba Standard Extension *** 680sh1add 0010000 .......... 010 ..... 0110011 @r 681sh2add 0010000 .......... 100 ..... 0110011 @r 682sh3add 0010000 .......... 110 ..... 0110011 @r 683 684# *** RV64 Zba Standard Extension (in addition to RV32 Zba) *** 685add_uw 0000100 .......... 000 ..... 0111011 @r 686sh1add_uw 0010000 .......... 010 ..... 0111011 @r 687sh2add_uw 0010000 .......... 100 ..... 0111011 @r 688sh3add_uw 0010000 .......... 110 ..... 0111011 @r 689slli_uw 00001 ............ 001 ..... 0011011 @sh 690 691# *** RV32 Zbb Standard Extension *** 692andn 0100000 .......... 111 ..... 0110011 @r 693clz 011000 000000 ..... 001 ..... 0010011 @r2 694cpop 011000 000010 ..... 001 ..... 0010011 @r2 695ctz 011000 000001 ..... 001 ..... 0010011 @r2 696max 0000101 .......... 110 ..... 0110011 @r 697maxu 0000101 .......... 111 ..... 0110011 @r 698min 0000101 .......... 100 ..... 0110011 @r 699minu 0000101 .......... 101 ..... 0110011 @r 700orc_b 001010 000111 ..... 101 ..... 0010011 @r2 701orn 0100000 .......... 110 ..... 0110011 @r 702# The encoding for rev8 differs between RV32 and RV64. 703# rev8_32 denotes the RV32 variant. 704rev8_32 011010 011000 ..... 101 ..... 0010011 @r2 705rol 0110000 .......... 001 ..... 0110011 @r 706ror 0110000 .......... 101 ..... 0110011 @r 707rori 01100 ............ 101 ..... 0010011 @sh 708sext_b 011000 000100 ..... 001 ..... 0010011 @r2 709sext_h 011000 000101 ..... 001 ..... 0010011 @r2 710xnor 0100000 .......... 100 ..... 0110011 @r 711# The encoding for zext.h differs between RV32 and RV64. 712# zext_h_32 denotes the RV32 variant. 713zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 714 715# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** 716clzw 0110000 00000 ..... 001 ..... 0011011 @r2 717ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 718cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 719# The encoding for rev8 differs between RV32 and RV64. 720# When executing on RV64, the encoding used in RV32 is an illegal 721# instruction, so we use different handler functions to differentiate. 722rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 723rolw 0110000 .......... 001 ..... 0111011 @r 724roriw 0110000 .......... 101 ..... 0011011 @sh5 725rorw 0110000 .......... 101 ..... 0111011 @r 726# The encoding for zext.h differs between RV32 and RV64. 727# When executing on RV64, the encoding used in RV32 is an illegal 728# instruction, so we use different handler functions to differentiate. 729zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 730 731# *** RV32 Zbc Standard Extension *** 732clmul 0000101 .......... 001 ..... 0110011 @r 733clmulh 0000101 .......... 011 ..... 0110011 @r 734clmulr 0000101 .......... 010 ..... 0110011 @r 735 736# *** RV32 Zbs Standard Extension *** 737bclr 0100100 .......... 001 ..... 0110011 @r 738bclri 01001. ........... 001 ..... 0010011 @sh 739bext 0100100 .......... 101 ..... 0110011 @r 740bexti 01001. ........... 101 ..... 0010011 @sh 741binv 0110100 .......... 001 ..... 0110011 @r 742binvi 01101. ........... 001 ..... 0010011 @sh 743bset 0010100 .......... 001 ..... 0110011 @r 744bseti 00101. ........... 001 ..... 0010011 @sh 745 746# *** RV32 Zfh Extension *** 747flh ............ ..... 001 ..... 0000111 @i 748fsh ....... ..... ..... 001 ..... 0100111 @s 749fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm 750fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm 751fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm 752fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm 753fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm 754fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm 755fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm 756fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm 757fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm 758fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r 759fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r 760fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r 761fmin_h 0010110 ..... ..... 000 ..... 1010011 @r 762fmax_h 0010110 ..... ..... 001 ..... 1010011 @r 763fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm 764fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm 765fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm 766fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm 767fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm 768fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm 769fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 770feq_h 1010010 ..... ..... 010 ..... 1010011 @r 771flt_h 1010010 ..... ..... 001 ..... 1010011 @r 772fle_h 1010010 ..... ..... 000 ..... 1010011 @r 773fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 774fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm 775fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm 776fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 777 778# *** RV64 Zfh Extension (in addition to RV32 Zfh) *** 779fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm 780fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm 781fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm 782fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm 783