1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24 25%sh10 20:10 26%csr 20:12 27%rm 12:3 28%nf 29:3 !function=ex_plus_1 29 30# immediates: 31%imm_i 20:s12 32%imm_s 25:s7 7:5 33%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 34%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 35%imm_u 12:s20 !function=ex_shift_12 36 37# Argument sets: 38&empty 39&b imm rs2 rs1 40&i imm rs1 rd 41&j imm rd 42&r rd rs1 rs2 43&s imm rs1 rs2 44&u imm rd 45&shift shamt rs1 rd 46&atomic aq rl rs2 rs1 rd 47&rwdvm vm wd rd rs1 rs2 48&r2nfvm vm rd rs1 nf 49&rnfvm vm rd rs1 rs2 nf 50 51# Formats 32: 52@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 53@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 54@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 55@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 56@u .................... ..... ....... &u imm=%imm_u %rd 57@j .................... ..... ....... &j imm=%imm_j %rd 58 59@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd 60@csr ............ ..... ... ..... ....... %csr %rs1 %rd 61 62@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 63@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 64 65@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 66@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 67@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 68@r2 ....... ..... ..... ... ..... ....... %rs1 %rd 69@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 70@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 71@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd 72@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd 73 74@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 75@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 76 77@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 78@sfence_vm ....... ..... ..... ... ..... ....... %rs1 79 80 81# *** Privileged Instructions *** 82ecall 000000000000 00000 000 00000 1110011 83ebreak 000000000001 00000 000 00000 1110011 84uret 0000000 00010 00000 000 00000 1110011 85sret 0001000 00010 00000 000 00000 1110011 86mret 0011000 00010 00000 000 00000 1110011 87wfi 0001000 00101 00000 000 00000 1110011 88sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 89sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 90 91# *** RV32I Base Instruction Set *** 92lui .................... ..... 0110111 @u 93auipc .................... ..... 0010111 @u 94jal .................... ..... 1101111 @j 95jalr ............ ..... 000 ..... 1100111 @i 96beq ....... ..... ..... 000 ..... 1100011 @b 97bne ....... ..... ..... 001 ..... 1100011 @b 98blt ....... ..... ..... 100 ..... 1100011 @b 99bge ....... ..... ..... 101 ..... 1100011 @b 100bltu ....... ..... ..... 110 ..... 1100011 @b 101bgeu ....... ..... ..... 111 ..... 1100011 @b 102lb ............ ..... 000 ..... 0000011 @i 103lh ............ ..... 001 ..... 0000011 @i 104lw ............ ..... 010 ..... 0000011 @i 105lbu ............ ..... 100 ..... 0000011 @i 106lhu ............ ..... 101 ..... 0000011 @i 107sb ....... ..... ..... 000 ..... 0100011 @s 108sh ....... ..... ..... 001 ..... 0100011 @s 109sw ....... ..... ..... 010 ..... 0100011 @s 110addi ............ ..... 000 ..... 0010011 @i 111slti ............ ..... 010 ..... 0010011 @i 112sltiu ............ ..... 011 ..... 0010011 @i 113xori ............ ..... 100 ..... 0010011 @i 114ori ............ ..... 110 ..... 0010011 @i 115andi ............ ..... 111 ..... 0010011 @i 116slli 00.... ...... ..... 001 ..... 0010011 @sh 117srli 00.... ...... ..... 101 ..... 0010011 @sh 118srai 01.... ...... ..... 101 ..... 0010011 @sh 119add 0000000 ..... ..... 000 ..... 0110011 @r 120sub 0100000 ..... ..... 000 ..... 0110011 @r 121sll 0000000 ..... ..... 001 ..... 0110011 @r 122slt 0000000 ..... ..... 010 ..... 0110011 @r 123sltu 0000000 ..... ..... 011 ..... 0110011 @r 124xor 0000000 ..... ..... 100 ..... 0110011 @r 125srl 0000000 ..... ..... 101 ..... 0110011 @r 126sra 0100000 ..... ..... 101 ..... 0110011 @r 127or 0000000 ..... ..... 110 ..... 0110011 @r 128and 0000000 ..... ..... 111 ..... 0110011 @r 129fence ---- pred:4 succ:4 ----- 000 ----- 0001111 130fence_i ---- ---- ---- ----- 001 ----- 0001111 131csrrw ............ ..... 001 ..... 1110011 @csr 132csrrs ............ ..... 010 ..... 1110011 @csr 133csrrc ............ ..... 011 ..... 1110011 @csr 134csrrwi ............ ..... 101 ..... 1110011 @csr 135csrrsi ............ ..... 110 ..... 1110011 @csr 136csrrci ............ ..... 111 ..... 1110011 @csr 137 138# *** RV32M Standard Extension *** 139mul 0000001 ..... ..... 000 ..... 0110011 @r 140mulh 0000001 ..... ..... 001 ..... 0110011 @r 141mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 142mulhu 0000001 ..... ..... 011 ..... 0110011 @r 143div 0000001 ..... ..... 100 ..... 0110011 @r 144divu 0000001 ..... ..... 101 ..... 0110011 @r 145rem 0000001 ..... ..... 110 ..... 0110011 @r 146remu 0000001 ..... ..... 111 ..... 0110011 @r 147 148# *** RV32A Standard Extension *** 149lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 150sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 151amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 152amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 153amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 154amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 155amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 156amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 157amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 158amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 159amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 160 161# *** RV32F Standard Extension *** 162flw ............ ..... 010 ..... 0000111 @i 163fsw ....... ..... ..... 010 ..... 0100111 @s 164fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 165fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 166fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 167fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 168fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 169fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 170fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 171fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 172fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 173fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 174fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 175fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 176fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 177fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 178fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 179fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 180fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 181feq_s 1010000 ..... ..... 010 ..... 1010011 @r 182flt_s 1010000 ..... ..... 001 ..... 1010011 @r 183fle_s 1010000 ..... ..... 000 ..... 1010011 @r 184fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 185fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 186fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 187fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 188 189# *** RV32D Standard Extension *** 190fld ............ ..... 011 ..... 0000111 @i 191fsd ....... ..... ..... 011 ..... 0100111 @s 192fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 193fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 194fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 195fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 196fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 197fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 198fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 199fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 200fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 201fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 202fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 203fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 204fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 205fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 206fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 207fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 208feq_d 1010001 ..... ..... 010 ..... 1010011 @r 209flt_d 1010001 ..... ..... 001 ..... 1010011 @r 210fle_d 1010001 ..... ..... 000 ..... 1010011 @r 211fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 212fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 213fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 214fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 215fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 216 217# *** RV32H Base Instruction Set *** 218hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 219hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 220 221# *** RV32V Extension *** 222 223# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 224vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm 225vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm 226vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm 227vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 228vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 229vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 230vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 231vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm 232vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm 233vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm 234vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 235vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 236vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 237vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 238vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 239vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 240vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 241vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 242 243vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm 244vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm 245vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm 246vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 247vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 248vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 249vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 250vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 251vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 252vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 253vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 254 255vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm 256vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm 257vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm 258vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm 259vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm 260vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm 261vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm 262# Vector ordered-indexed and unordered-indexed store insns. 263vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm 264vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm 265vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm 266vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm 267 268#*** Vector AMO operations are encoded under the standard AMO major opcode *** 269vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm 270vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm 271vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm 272vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm 273vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm 274vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm 275vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm 276vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm 277vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm 278 279# *** new major opcode OP-V *** 280vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm 281vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 282