xref: /openbmc/qemu/target/riscv/insn32.decode (revision 200dbf37)
1#
2# RISC-V translation routines for the RVXI Base Integer Instruction Set.
3#
4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
5#                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
6#
7# This program is free software; you can redistribute it and/or modify it
8# under the terms and conditions of the GNU General Public License,
9# version 2 or later, as published by the Free Software Foundation.
10#
11# This program is distributed in the hope it will be useful, but WITHOUT
12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14# more details.
15#
16# You should have received a copy of the GNU General Public License along with
17# this program.  If not, see <http://www.gnu.org/licenses/>.
18
19# Fields:
20%rs3       27:5
21%rs2       20:5
22%rs1       15:5
23%rd        7:5
24
25%sh10    20:10
26%csr    20:12
27%rm     12:3
28
29# immediates:
30%imm_i    20:s12
31%imm_s    25:s7 7:5
32%imm_b    31:s1 7:1 25:6 8:4     !function=ex_shift_1
33%imm_j    31:s1 12:8 20:1 21:10  !function=ex_shift_1
34%imm_u    12:s20                 !function=ex_shift_12
35
36# Argument sets:
37&empty
38&b    imm rs2 rs1
39&i    imm rs1 rd
40&j    imm rd
41&r    rd rs1 rs2
42&s    imm rs1 rs2
43&u    imm rd
44&shift     shamt rs1 rd
45&atomic    aq rl rs2 rs1 rd
46
47# Formats 32:
48@r       .......   ..... ..... ... ..... ....... &r                %rs2 %rs1 %rd
49@i       ............    ..... ... ..... ....... &i      imm=%imm_i     %rs1 %rd
50@b       .......   ..... ..... ... ..... ....... &b      imm=%imm_b %rs2 %rs1
51@s       .......   ..... ..... ... ..... ....... &s      imm=%imm_s %rs2 %rs1
52@u       ....................      ..... ....... &u      imm=%imm_u          %rd
53@j       ....................      ..... ....... &j      imm=%imm_j          %rd
54
55@sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh10      %rs1 %rd
56@csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
57
58@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
59@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2      %rs1 %rd
60
61@r4_rm   ..... ..  ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
62@r_rm    .......   ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
63@r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
64@r2      .......   ..... ..... ... ..... ....... %rs1 %rd
65
66@sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
67@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
68
69
70# *** Privileged Instructions ***
71ecall      000000000000     00000 000 00000 1110011
72ebreak     000000000001     00000 000 00000 1110011
73uret       0000000    00010 00000 000 00000 1110011
74sret       0001000    00010 00000 000 00000 1110011
75hret       0010000    00010 00000 000 00000 1110011
76mret       0011000    00010 00000 000 00000 1110011
77wfi        0001000    00101 00000 000 00000 1110011
78sfence_vma 0001001    ..... ..... 000 00000 1110011 @sfence_vma
79sfence_vm  0001000    00100 ..... 000 00000 1110011 @sfence_vm
80
81# *** RV32I Base Instruction Set ***
82lui      ....................       ..... 0110111 @u
83auipc    ....................       ..... 0010111 @u
84jal      ....................       ..... 1101111 @j
85jalr     ............     ..... 000 ..... 1100111 @i
86beq      ....... .....    ..... 000 ..... 1100011 @b
87bne      ....... .....    ..... 001 ..... 1100011 @b
88blt      ....... .....    ..... 100 ..... 1100011 @b
89bge      ....... .....    ..... 101 ..... 1100011 @b
90bltu     ....... .....    ..... 110 ..... 1100011 @b
91bgeu     ....... .....    ..... 111 ..... 1100011 @b
92lb       ............     ..... 000 ..... 0000011 @i
93lh       ............     ..... 001 ..... 0000011 @i
94lw       ............     ..... 010 ..... 0000011 @i
95lbu      ............     ..... 100 ..... 0000011 @i
96lhu      ............     ..... 101 ..... 0000011 @i
97sb       .......  .....   ..... 000 ..... 0100011 @s
98sh       .......  .....   ..... 001 ..... 0100011 @s
99sw       .......  .....   ..... 010 ..... 0100011 @s
100addi     ............     ..... 000 ..... 0010011 @i
101slti     ............     ..... 010 ..... 0010011 @i
102sltiu    ............     ..... 011 ..... 0010011 @i
103xori     ............     ..... 100 ..... 0010011 @i
104ori      ............     ..... 110 ..... 0010011 @i
105andi     ............     ..... 111 ..... 0010011 @i
106slli     00.... ......    ..... 001 ..... 0010011 @sh
107srli     00.... ......    ..... 101 ..... 0010011 @sh
108srai     01.... ......    ..... 101 ..... 0010011 @sh
109add      0000000 .....    ..... 000 ..... 0110011 @r
110sub      0100000 .....    ..... 000 ..... 0110011 @r
111sll      0000000 .....    ..... 001 ..... 0110011 @r
112slt      0000000 .....    ..... 010 ..... 0110011 @r
113sltu     0000000 .....    ..... 011 ..... 0110011 @r
114xor      0000000 .....    ..... 100 ..... 0110011 @r
115srl      0000000 .....    ..... 101 ..... 0110011 @r
116sra      0100000 .....    ..... 101 ..... 0110011 @r
117or       0000000 .....    ..... 110 ..... 0110011 @r
118and      0000000 .....    ..... 111 ..... 0110011 @r
119fence    ---- pred:4 succ:4 ----- 000 ----- 0001111
120fence_i  ---- ----   ----   ----- 001 ----- 0001111
121csrrw    ............     ..... 001 ..... 1110011 @csr
122csrrs    ............     ..... 010 ..... 1110011 @csr
123csrrc    ............     ..... 011 ..... 1110011 @csr
124csrrwi   ............     ..... 101 ..... 1110011 @csr
125csrrsi   ............     ..... 110 ..... 1110011 @csr
126csrrci   ............     ..... 111 ..... 1110011 @csr
127
128# *** RV32M Standard Extension ***
129mul      0000001 .....  ..... 000 ..... 0110011 @r
130mulh     0000001 .....  ..... 001 ..... 0110011 @r
131mulhsu   0000001 .....  ..... 010 ..... 0110011 @r
132mulhu    0000001 .....  ..... 011 ..... 0110011 @r
133div      0000001 .....  ..... 100 ..... 0110011 @r
134divu     0000001 .....  ..... 101 ..... 0110011 @r
135rem      0000001 .....  ..... 110 ..... 0110011 @r
136remu     0000001 .....  ..... 111 ..... 0110011 @r
137
138# *** RV32A Standard Extension ***
139lr_w       00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
140sc_w       00011 . . ..... ..... 010 ..... 0101111 @atom_st
141amoswap_w  00001 . . ..... ..... 010 ..... 0101111 @atom_st
142amoadd_w   00000 . . ..... ..... 010 ..... 0101111 @atom_st
143amoxor_w   00100 . . ..... ..... 010 ..... 0101111 @atom_st
144amoand_w   01100 . . ..... ..... 010 ..... 0101111 @atom_st
145amoor_w    01000 . . ..... ..... 010 ..... 0101111 @atom_st
146amomin_w   10000 . . ..... ..... 010 ..... 0101111 @atom_st
147amomax_w   10100 . . ..... ..... 010 ..... 0101111 @atom_st
148amominu_w  11000 . . ..... ..... 010 ..... 0101111 @atom_st
149amomaxu_w  11100 . . ..... ..... 010 ..... 0101111 @atom_st
150
151# *** RV32F Standard Extension ***
152flw        ............   ..... 010 ..... 0000111 @i
153fsw        .......  ..... ..... 010 ..... 0100111 @s
154fmadd_s    ..... 00 ..... ..... ... ..... 1000011 @r4_rm
155fmsub_s    ..... 00 ..... ..... ... ..... 1000111 @r4_rm
156fnmsub_s   ..... 00 ..... ..... ... ..... 1001011 @r4_rm
157fnmadd_s   ..... 00 ..... ..... ... ..... 1001111 @r4_rm
158fadd_s     0000000  ..... ..... ... ..... 1010011 @r_rm
159fsub_s     0000100  ..... ..... ... ..... 1010011 @r_rm
160fmul_s     0001000  ..... ..... ... ..... 1010011 @r_rm
161fdiv_s     0001100  ..... ..... ... ..... 1010011 @r_rm
162fsqrt_s    0101100  00000 ..... ... ..... 1010011 @r2_rm
163fsgnj_s    0010000  ..... ..... 000 ..... 1010011 @r
164fsgnjn_s   0010000  ..... ..... 001 ..... 1010011 @r
165fsgnjx_s   0010000  ..... ..... 010 ..... 1010011 @r
166fmin_s     0010100  ..... ..... 000 ..... 1010011 @r
167fmax_s     0010100  ..... ..... 001 ..... 1010011 @r
168fcvt_w_s   1100000  00000 ..... ... ..... 1010011 @r2_rm
169fcvt_wu_s  1100000  00001 ..... ... ..... 1010011 @r2_rm
170fmv_x_w    1110000  00000 ..... 000 ..... 1010011 @r2
171feq_s      1010000  ..... ..... 010 ..... 1010011 @r
172flt_s      1010000  ..... ..... 001 ..... 1010011 @r
173fle_s      1010000  ..... ..... 000 ..... 1010011 @r
174fclass_s   1110000  00000 ..... 001 ..... 1010011 @r2
175fcvt_s_w   1101000  00000 ..... ... ..... 1010011 @r2_rm
176fcvt_s_wu  1101000  00001 ..... ... ..... 1010011 @r2_rm
177fmv_w_x    1111000  00000 ..... 000 ..... 1010011 @r2
178
179# *** RV32D Standard Extension ***
180fld        ............   ..... 011 ..... 0000111 @i
181fsd        ....... .....  ..... 011 ..... 0100111 @s
182fmadd_d    ..... 01 ..... ..... ... ..... 1000011 @r4_rm
183fmsub_d    ..... 01 ..... ..... ... ..... 1000111 @r4_rm
184fnmsub_d   ..... 01 ..... ..... ... ..... 1001011 @r4_rm
185fnmadd_d   ..... 01 ..... ..... ... ..... 1001111 @r4_rm
186fadd_d     0000001  ..... ..... ... ..... 1010011 @r_rm
187fsub_d     0000101  ..... ..... ... ..... 1010011 @r_rm
188fmul_d     0001001  ..... ..... ... ..... 1010011 @r_rm
189fdiv_d     0001101  ..... ..... ... ..... 1010011 @r_rm
190fsqrt_d    0101101  00000 ..... ... ..... 1010011 @r2_rm
191fsgnj_d    0010001  ..... ..... 000 ..... 1010011 @r
192fsgnjn_d   0010001  ..... ..... 001 ..... 1010011 @r
193fsgnjx_d   0010001  ..... ..... 010 ..... 1010011 @r
194fmin_d     0010101  ..... ..... 000 ..... 1010011 @r
195fmax_d     0010101  ..... ..... 001 ..... 1010011 @r
196fcvt_s_d   0100000  00001 ..... ... ..... 1010011 @r2_rm
197fcvt_d_s   0100001  00000 ..... ... ..... 1010011 @r2_rm
198feq_d      1010001  ..... ..... 010 ..... 1010011 @r
199flt_d      1010001  ..... ..... 001 ..... 1010011 @r
200fle_d      1010001  ..... ..... 000 ..... 1010011 @r
201fclass_d   1110001  00000 ..... 001 ..... 1010011 @r2
202fcvt_w_d   1100001  00000 ..... ... ..... 1010011 @r2_rm
203fcvt_wu_d  1100001  00001 ..... ... ..... 1010011 @r2_rm
204fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
205fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
206