1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rs3 27:5 21%rs2 20:5 22%rs1 15:5 23%rd 7:5 24 25%sh10 20:10 26%csr 20:12 27%rm 12:3 28%nf 29:3 !function=ex_plus_1 29 30# immediates: 31%imm_i 20:s12 32%imm_s 25:s7 7:5 33%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1 34%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1 35%imm_u 12:s20 !function=ex_shift_12 36 37# Argument sets: 38&empty 39&b imm rs2 rs1 40&i imm rs1 rd 41&j imm rd 42&r rd rs1 rs2 43&s imm rs1 rs2 44&u imm rd 45&shift shamt rs1 rd 46&atomic aq rl rs2 rs1 rd 47&r2nfvm vm rd rs1 nf 48&rnfvm vm rd rs1 rs2 nf 49 50# Formats 32: 51@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 52@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd 53@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1 54@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1 55@u .................... ..... ....... &u imm=%imm_u %rd 56@j .................... ..... ....... &j imm=%imm_j %rd 57 58@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd 59@csr ............ ..... ... ..... ....... %csr %rs1 %rd 60 61@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd 62@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd 63 64@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd 65@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd 66@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd 67@r2 ....... ..... ..... ... ..... ....... %rs1 %rd 68@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd 69@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd 70@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd 71 72@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 73@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1 74 75@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1 76@sfence_vm ....... ..... ..... ... ..... ....... %rs1 77 78 79# *** Privileged Instructions *** 80ecall 000000000000 00000 000 00000 1110011 81ebreak 000000000001 00000 000 00000 1110011 82uret 0000000 00010 00000 000 00000 1110011 83sret 0001000 00010 00000 000 00000 1110011 84mret 0011000 00010 00000 000 00000 1110011 85wfi 0001000 00101 00000 000 00000 1110011 86sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma 87sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm 88 89# *** RV32I Base Instruction Set *** 90lui .................... ..... 0110111 @u 91auipc .................... ..... 0010111 @u 92jal .................... ..... 1101111 @j 93jalr ............ ..... 000 ..... 1100111 @i 94beq ....... ..... ..... 000 ..... 1100011 @b 95bne ....... ..... ..... 001 ..... 1100011 @b 96blt ....... ..... ..... 100 ..... 1100011 @b 97bge ....... ..... ..... 101 ..... 1100011 @b 98bltu ....... ..... ..... 110 ..... 1100011 @b 99bgeu ....... ..... ..... 111 ..... 1100011 @b 100lb ............ ..... 000 ..... 0000011 @i 101lh ............ ..... 001 ..... 0000011 @i 102lw ............ ..... 010 ..... 0000011 @i 103lbu ............ ..... 100 ..... 0000011 @i 104lhu ............ ..... 101 ..... 0000011 @i 105sb ....... ..... ..... 000 ..... 0100011 @s 106sh ....... ..... ..... 001 ..... 0100011 @s 107sw ....... ..... ..... 010 ..... 0100011 @s 108addi ............ ..... 000 ..... 0010011 @i 109slti ............ ..... 010 ..... 0010011 @i 110sltiu ............ ..... 011 ..... 0010011 @i 111xori ............ ..... 100 ..... 0010011 @i 112ori ............ ..... 110 ..... 0010011 @i 113andi ............ ..... 111 ..... 0010011 @i 114slli 00.... ...... ..... 001 ..... 0010011 @sh 115srli 00.... ...... ..... 101 ..... 0010011 @sh 116srai 01.... ...... ..... 101 ..... 0010011 @sh 117add 0000000 ..... ..... 000 ..... 0110011 @r 118sub 0100000 ..... ..... 000 ..... 0110011 @r 119sll 0000000 ..... ..... 001 ..... 0110011 @r 120slt 0000000 ..... ..... 010 ..... 0110011 @r 121sltu 0000000 ..... ..... 011 ..... 0110011 @r 122xor 0000000 ..... ..... 100 ..... 0110011 @r 123srl 0000000 ..... ..... 101 ..... 0110011 @r 124sra 0100000 ..... ..... 101 ..... 0110011 @r 125or 0000000 ..... ..... 110 ..... 0110011 @r 126and 0000000 ..... ..... 111 ..... 0110011 @r 127fence ---- pred:4 succ:4 ----- 000 ----- 0001111 128fence_i ---- ---- ---- ----- 001 ----- 0001111 129csrrw ............ ..... 001 ..... 1110011 @csr 130csrrs ............ ..... 010 ..... 1110011 @csr 131csrrc ............ ..... 011 ..... 1110011 @csr 132csrrwi ............ ..... 101 ..... 1110011 @csr 133csrrsi ............ ..... 110 ..... 1110011 @csr 134csrrci ............ ..... 111 ..... 1110011 @csr 135 136# *** RV32M Standard Extension *** 137mul 0000001 ..... ..... 000 ..... 0110011 @r 138mulh 0000001 ..... ..... 001 ..... 0110011 @r 139mulhsu 0000001 ..... ..... 010 ..... 0110011 @r 140mulhu 0000001 ..... ..... 011 ..... 0110011 @r 141div 0000001 ..... ..... 100 ..... 0110011 @r 142divu 0000001 ..... ..... 101 ..... 0110011 @r 143rem 0000001 ..... ..... 110 ..... 0110011 @r 144remu 0000001 ..... ..... 111 ..... 0110011 @r 145 146# *** RV32A Standard Extension *** 147lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld 148sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st 149amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st 150amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st 151amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st 152amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st 153amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st 154amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st 155amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st 156amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st 157amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st 158 159# *** RV32F Standard Extension *** 160flw ............ ..... 010 ..... 0000111 @i 161fsw ....... ..... ..... 010 ..... 0100111 @s 162fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm 163fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm 164fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm 165fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm 166fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm 167fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm 168fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm 169fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm 170fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm 171fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r 172fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r 173fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r 174fmin_s 0010100 ..... ..... 000 ..... 1010011 @r 175fmax_s 0010100 ..... ..... 001 ..... 1010011 @r 176fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm 177fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm 178fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2 179feq_s 1010000 ..... ..... 010 ..... 1010011 @r 180flt_s 1010000 ..... ..... 001 ..... 1010011 @r 181fle_s 1010000 ..... ..... 000 ..... 1010011 @r 182fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2 183fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm 184fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm 185fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2 186 187# *** RV32D Standard Extension *** 188fld ............ ..... 011 ..... 0000111 @i 189fsd ....... ..... ..... 011 ..... 0100111 @s 190fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm 191fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm 192fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm 193fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm 194fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm 195fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm 196fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm 197fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm 198fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm 199fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r 200fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r 201fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r 202fmin_d 0010101 ..... ..... 000 ..... 1010011 @r 203fmax_d 0010101 ..... ..... 001 ..... 1010011 @r 204fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm 205fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm 206feq_d 1010001 ..... ..... 010 ..... 1010011 @r 207flt_d 1010001 ..... ..... 001 ..... 1010011 @r 208fle_d 1010001 ..... ..... 000 ..... 1010011 @r 209fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2 210fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm 211fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm 212fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm 213fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm 214 215# *** RV32H Base Instruction Set *** 216hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma 217hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma 218 219# *** RV32V Extension *** 220 221# *** Vector loads and stores are encoded within LOADFP/STORE-FP *** 222vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm 223vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm 224vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm 225vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm 226vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm 227vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm 228vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm 229vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm 230vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm 231vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm 232vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm 233vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm 234vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm 235vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm 236vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm 237vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm 238vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm 239vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm 240 241vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm 242vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm 243vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm 244vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm 245vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm 246vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm 247vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm 248vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm 249vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm 250vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm 251vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm 252 253vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm 254vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm 255vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm 256vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm 257vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm 258vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm 259vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm 260# Vector ordered-indexed and unordered-indexed store insns. 261vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm 262vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm 263vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm 264vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm 265 266# *** new major opcode OP-V *** 267vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm 268vsetvl 1000000 ..... ..... 111 ..... 1010111 @r 269