1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rd 7:5 21%rs1_3 7:3 !function=ex_rvc_register 22%rs2_3 2:3 !function=ex_rvc_register 23%rs2_5 2:5 24 25# Immediates: 26%imm_ci 12:s1 2:5 27%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2 28%uimm_cl_q 10:1 5:2 11:2 !function=ex_shift_4 29%uimm_cl_d 5:2 10:3 !function=ex_shift_3 30%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2 31%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1 32%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1 33 34%shlimm_6bit 12:1 2:5 !function=ex_rvc_shiftli 35%shrimm_6bit 12:1 2:5 !function=ex_rvc_shiftri 36%uimm_6bit_lq 2:4 12:1 6:1 !function=ex_shift_4 37%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3 38%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2 39%uimm_6bit_sq 7:4 11:2 !function=ex_shift_4 40%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3 41%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2 42 43%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 44%imm_lui 12:s1 2:5 !function=ex_shift_12 45 46 47# Argument sets imported from insn32.decode: 48&empty !extern 49&r rd rs1 rs2 !extern 50&i imm rs1 rd !extern 51&s imm rs1 rs2 !extern 52&j imm rd !extern 53&b imm rs2 rs1 !extern 54&u imm rd !extern 55&shift shamt rs1 rd !extern 56 57 58# Formats 16: 59@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd 60@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd 61@cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3 62@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 63@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 64@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 65@cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3 66@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 67@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 68@cj ... ........... .. &j imm=%imm_cj 69@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0 70 71@c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd 72@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd 73@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd 74@c_sqsp ... . ..... ..... .. &s imm=%uimm_6bit_sq rs1=2 rs2=%rs2_5 75@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5 76@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5 77@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd 78@c_lui ... . ..... ..... .. &u imm=%imm_lui %rd 79@c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd 80@c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd 81 82@c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3 83@c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2 84 85@c_shift ... . .. ... ..... .. \ 86 &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shrimm_6bit 87@c_shift2 ... . .. ... ..... .. \ 88 &shift rd=%rd rs1=%rd shamt=%shlimm_6bit 89 90@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 91 92# *** RV32/64C Standard Extension (Quadrant 0) *** 93{ 94 # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. 95 illegal 000 000 000 00 --- 00 96 addi 000 ... ... .. ... 00 @c_addi4spn 97} 98{ 99 lq 001 ... ... .. ... 00 @cl_q 100 fld 001 ... ... .. ... 00 @cl_d 101} 102lw 010 ... ... .. ... 00 @cl_w 103{ 104 sq 101 ... ... .. ... 00 @cs_q 105 fsd 101 ... ... .. ... 00 @cs_d 106} 107sw 110 ... ... .. ... 00 @cs_w 108 109# *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** 110{ 111 ld 011 ... ... .. ... 00 @cl_d 112 flw 011 ... ... .. ... 00 @cl_w 113} 114{ 115 sd 111 ... ... .. ... 00 @cs_d 116 fsw 111 ... ... .. ... 00 @cs_w 117} 118 119# *** RV32/64C Standard Extension (Quadrant 1) *** 120addi 000 . ..... ..... 01 @ci 121addi 010 . ..... ..... 01 @c_li 122{ 123 illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0 124 addi 011 . 00010 ..... 01 @c_addi16sp 125 lui 011 . ..... ..... 01 @c_lui 126} 127srli 100 . 00 ... ..... 01 @c_shift 128srai 100 . 01 ... ..... 01 @c_shift 129andi 100 . 10 ... ..... 01 @c_andi 130sub 100 0 11 ... 00 ... 01 @cs_2 131xor 100 0 11 ... 01 ... 01 @cs_2 132or 100 0 11 ... 10 ... 01 @cs_2 133and 100 0 11 ... 11 ... 01 @cs_2 134jal 101 ........... 01 @cj rd=0 # C.J 135beq 110 ... ... ..... 01 @cb_z 136bne 111 ... ... ..... 01 @cb_z 137 138# *** RV64C and RV32C specific Standard Extension (Quadrant 1) *** 139{ 140 c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0 141 addiw 001 . ..... ..... 01 @ci 142 jal 001 ........... 01 @cj rd=1 # C.JAL 143} 144subw 100 1 11 ... 00 ... 01 @cs_2 145addw 100 1 11 ... 01 ... 01 @cs_2 146 147# *** RV32/64C Standard Extension (Quadrant 2) *** 148slli 000 . ..... ..... 10 @c_shift2 149{ 150 lq 001 ... ... .. ... 10 @c_lqsp 151 fld 001 . ..... ..... 10 @c_ldsp 152} 153{ 154 illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 155 lw 010 . ..... ..... 10 @c_lwsp 156} 157{ 158 illegal 100 0 00000 00000 10 # c.jr, RES rs1=0 159 jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR 160 addi 100 0 ..... ..... 10 @c_mv 161} 162{ 163 ebreak 100 1 00000 00000 10 164 jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR 165 add 100 1 ..... ..... 10 @cr 166} 167{ 168 sq 101 ... ... .. ... 10 @c_sqsp 169 fsd 101 ...... ..... 10 @c_sdsp 170} 171sw 110 . ..... ..... 10 @c_swsp 172 173# *** RV32C and RV64C specific Standard Extension (Quadrant 2) *** 174{ 175 c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0 176 ld 011 . ..... ..... 10 @c_ldsp 177 flw 011 . ..... ..... 10 @c_lwsp 178} 179{ 180 sd 111 . ..... ..... 10 @c_sdsp 181 fsw 111 . ..... ..... 10 @c_swsp 182} 183