1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rd 7:5 21%rs1_3 7:3 !function=ex_rvc_register 22%rs2_3 2:3 !function=ex_rvc_register 23%rs2_5 2:5 24 25# Immediates: 26%imm_ci 12:s1 2:5 27%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2 28%uimm_cl_d 5:2 10:3 !function=ex_shift_3 29%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2 30%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1 31%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1 32 33%shimm_6bit 12:1 2:5 !function=ex_rvc_shifti 34%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3 35%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2 36%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3 37%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2 38 39%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 40%imm_lui 12:s1 2:5 !function=ex_shift_12 41 42 43# Argument sets imported from insn32.decode: 44&empty !extern 45&r rd rs1 rs2 !extern 46&i imm rs1 rd !extern 47&s imm rs1 rs2 !extern 48&j imm rd !extern 49&b imm rs2 rs1 !extern 50&u imm rd !extern 51&shift shamt rs1 rd !extern 52 53# Argument sets: 54&cl rs1 rd 55&cl_dw uimm rs1 rd 56&ciw nzuimm rd 57&cs rs1 rs2 58&cs_dw uimm rs1 rs2 59&cb imm rs1 60&cr rd rs2 61&c_shift shamt rd 62 63&c_ld uimm rd 64&c_sd uimm rs2 65 66&caddi16sp_lui imm_lui imm_addi16sp rd 67&cflwsp_ldsp uimm_flwsp uimm_ldsp rd 68&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2 69 70# Formats 16: 71@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd 72@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd 73@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3 74@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 75@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 76@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3 77@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3 78@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 79@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 80@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 81@cj ... ........... .. &j imm=%imm_cj 82@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0 83 84@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd 85@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd 86@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5 87@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5 88@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd 89 90@c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd 91@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \ 92 uimm_ldsp=%uimm_6bit_ld %rd 93@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \ 94 uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5 95 96@c_shift ... . .. ... ..... .. \ 97 &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit 98@c_shift2 ... . .. ... ..... .. \ 99 &shift rd=%rd rs1=%rd shamt=%shimm_6bit 100 101@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 102 103# *** RV64C Standard Extension (Quadrant 0) *** 104c_addi4spn 000 ........ ... 00 @ciw 105fld 001 ... ... .. ... 00 @cl_d 106lw 010 ... ... .. ... 00 @cl_w 107c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually 108fsd 101 ... ... .. ... 00 @cs_d 109sw 110 ... ... .. ... 00 @cs_w 110c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually 111 112# *** RV64C Standard Extension (Quadrant 1) *** 113addi 000 . ..... ..... 01 @ci 114c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually 115addi 010 . ..... ..... 01 @c_li 116c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI 117srli 100 . 00 ... ..... 01 @c_shift 118srai 100 . 01 ... ..... 01 @c_shift 119andi 100 . 10 ... ..... 01 @c_andi 120sub 100 0 11 ... 00 ... 01 @cs_2 121xor 100 0 11 ... 01 ... 01 @cs_2 122or 100 0 11 ... 10 ... 01 @cs_2 123and 100 0 11 ... 11 ... 01 @cs_2 124c_subw 100 1 11 ... 00 ... 01 @cs_2 125c_addw 100 1 11 ... 01 ... 01 @cs_2 126jal 101 ........... 01 @cj rd=0 # C.J 127beq 110 ... ... ..... 01 @cb_z 128bne 111 ... ... ..... 01 @cb_z 129 130# *** RV64C Standard Extension (Quadrant 2) *** 131slli 000 . ..... ..... 10 @c_shift2 132fld 001 . ..... ..... 10 @c_ldsp 133lw 010 . ..... ..... 10 @c_lwsp 134c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32 135c_jr_mv 100 0 ..... ..... 10 @cr 136c_ebreak_jalr_add 100 1 ..... ..... 10 @cr 137fsd 101 ...... ..... 10 @c_sdsp 138sw 110 . ..... ..... 10 @c_swsp 139c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32 140