1# 2# RISC-V translation routines for the RVXI Base Integer Instruction Set. 3# 4# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de 5# Bastian Koppelmann, kbastian@mail.uni-paderborn.de 6# 7# This program is free software; you can redistribute it and/or modify it 8# under the terms and conditions of the GNU General Public License, 9# version 2 or later, as published by the Free Software Foundation. 10# 11# This program is distributed in the hope it will be useful, but WITHOUT 12# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14# more details. 15# 16# You should have received a copy of the GNU General Public License along with 17# this program. If not, see <http://www.gnu.org/licenses/>. 18 19# Fields: 20%rd 7:5 21%rs1_3 7:3 !function=ex_rvc_register 22%rs2_3 2:3 !function=ex_rvc_register 23%rs2_5 2:5 24 25# Immediates: 26%imm_ci 12:s1 2:5 27%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2 28%uimm_cl_d 5:2 10:3 !function=ex_shift_3 29%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2 30%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1 31%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1 32 33%shimm_6bit 12:1 2:5 !function=ex_rvc_shifti 34%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3 35%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2 36%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3 37%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2 38 39%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 40%imm_lui 12:s1 2:5 !function=ex_shift_12 41 42 43# Argument sets imported from insn32.decode: 44&empty !extern 45&r rd rs1 rs2 !extern 46&i imm rs1 rd !extern 47&s imm rs1 rs2 !extern 48&j imm rd !extern 49&b imm rs2 rs1 !extern 50&u imm rd !extern 51&shift shamt rs1 rd !extern 52 53 54# Formats 16: 55@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd 56@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd 57@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3 58@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3 59@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 60@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3 61@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3 62@cj ... ........... .. &j imm=%imm_cj 63@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0 64 65@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd 66@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd 67@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5 68@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5 69@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd 70@c_lui ... . ..... ..... .. &u imm=%imm_lui %rd 71@c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd 72@c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd 73 74@c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3 75@c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2 76 77@c_shift ... . .. ... ..... .. \ 78 &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit 79@c_shift2 ... . .. ... ..... .. \ 80 &shift rd=%rd rs1=%rd shamt=%shimm_6bit 81 82@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 83 84# *** RV32/64C Standard Extension (Quadrant 0) *** 85{ 86 # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. 87 illegal 000 000 000 00 --- 00 88 addi 000 ... ... .. ... 00 @c_addi4spn 89} 90fld 001 ... ... .. ... 00 @cl_d 91lw 010 ... ... .. ... 00 @cl_w 92fsd 101 ... ... .. ... 00 @cs_d 93sw 110 ... ... .. ... 00 @cs_w 94 95# *** RV32/64C Standard Extension (Quadrant 1) *** 96addi 000 . ..... ..... 01 @ci 97addi 010 . ..... ..... 01 @c_li 98{ 99 illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0 100 addi 011 . 00010 ..... 01 @c_addi16sp 101 lui 011 . ..... ..... 01 @c_lui 102} 103srli 100 . 00 ... ..... 01 @c_shift 104srai 100 . 01 ... ..... 01 @c_shift 105andi 100 . 10 ... ..... 01 @c_andi 106sub 100 0 11 ... 00 ... 01 @cs_2 107xor 100 0 11 ... 01 ... 01 @cs_2 108or 100 0 11 ... 10 ... 01 @cs_2 109and 100 0 11 ... 11 ... 01 @cs_2 110jal 101 ........... 01 @cj rd=0 # C.J 111beq 110 ... ... ..... 01 @cb_z 112bne 111 ... ... ..... 01 @cb_z 113 114# *** RV32/64C Standard Extension (Quadrant 2) *** 115slli 000 . ..... ..... 10 @c_shift2 116fld 001 . ..... ..... 10 @c_ldsp 117{ 118 illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 119 lw 010 . ..... ..... 10 @c_lwsp 120} 121{ 122 illegal 100 0 00000 00000 10 # c.jr, RES rs1=0 123 jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR 124 addi 100 0 ..... ..... 10 @c_mv 125} 126{ 127 ebreak 100 1 00000 00000 10 128 jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR 129 add 100 1 ..... ..... 10 @cr 130} 131fsd 101 ...... ..... 10 @c_sdsp 132sw 110 . ..... ..... 10 @c_swsp 133