1 /* 2 * RISC-V GDB Server Stub 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "exec/gdbstub.h" 21 #include "cpu.h" 22 23 struct TypeSize { 24 const char *gdb_type; 25 const char *id; 26 int size; 27 const char suffix; 28 }; 29 30 static const struct TypeSize vec_lanes[] = { 31 /* quads */ 32 { "uint128", "quads", 128, 'q' }, 33 /* 64 bit */ 34 { "uint64", "longs", 64, 'l' }, 35 /* 32 bit */ 36 { "uint32", "words", 32, 'w' }, 37 /* 16 bit */ 38 { "uint16", "shorts", 16, 's' }, 39 /* 40 * TODO: currently there is no reliable way of telling 41 * if the remote gdb actually understands ieee_half so 42 * we don't expose it in the target description for now. 43 * { "ieee_half", 16, 'h', 'f' }, 44 */ 45 /* bytes */ 46 { "uint8", "bytes", 8, 'b' }, 47 }; 48 49 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 50 { 51 RISCVCPU *cpu = RISCV_CPU(cs); 52 CPURISCVState *env = &cpu->env; 53 54 if (n < 32) { 55 return gdb_get_regl(mem_buf, env->gpr[n]); 56 } else if (n == 32) { 57 return gdb_get_regl(mem_buf, env->pc); 58 } 59 return 0; 60 } 61 62 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 63 { 64 RISCVCPU *cpu = RISCV_CPU(cs); 65 CPURISCVState *env = &cpu->env; 66 67 if (n == 0) { 68 /* discard writes to x0 */ 69 return sizeof(target_ulong); 70 } else if (n < 32) { 71 env->gpr[n] = ldtul_p(mem_buf); 72 return sizeof(target_ulong); 73 } else if (n == 32) { 74 env->pc = ldtul_p(mem_buf); 75 return sizeof(target_ulong); 76 } 77 return 0; 78 } 79 80 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) 81 { 82 if (n < 32) { 83 if (env->misa_ext & RVD) { 84 return gdb_get_reg64(buf, env->fpr[n]); 85 } 86 if (env->misa_ext & RVF) { 87 return gdb_get_reg32(buf, env->fpr[n]); 88 } 89 /* there is hole between ft11 and fflags in fpu.xml */ 90 } else if (n < 36 && n > 32) { 91 target_ulong val = 0; 92 int result; 93 /* 94 * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP 95 * register 33, so we recalculate the map index. 96 * This also works for CSR_FRM and CSR_FCSR. 97 */ 98 result = riscv_csrrw_debug(env, n - 32, &val, 99 0, 0); 100 if (result == RISCV_EXCP_NONE) { 101 return gdb_get_regl(buf, val); 102 } 103 } 104 return 0; 105 } 106 107 static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) 108 { 109 if (n < 32) { 110 env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ 111 return sizeof(uint64_t); 112 /* there is hole between ft11 and fflags in fpu.xml */ 113 } else if (n < 36 && n > 32) { 114 target_ulong val = ldtul_p(mem_buf); 115 int result; 116 /* 117 * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP 118 * register 33, so we recalculate the map index. 119 * This also works for CSR_FRM and CSR_FCSR. 120 */ 121 result = riscv_csrrw_debug(env, n - 32, NULL, 122 val, -1); 123 if (result == RISCV_EXCP_NONE) { 124 return sizeof(target_ulong); 125 } 126 } 127 return 0; 128 } 129 130 /* 131 * Convert register index number passed by GDB to the correspond 132 * vector CSR number. Vector CSRs are defined after vector registers 133 * in dynamic generated riscv-vector.xml, thus the starting register index 134 * of vector CSRs is 32. 135 * Return 0 if register index number is out of range. 136 */ 137 static int riscv_gdb_vector_csrno(int num_regs) 138 { 139 /* 140 * The order of vector CSRs in the switch case 141 * should match with the order defined in csr_ops[]. 142 */ 143 switch (num_regs) { 144 case 32: 145 return CSR_VSTART; 146 case 33: 147 return CSR_VXSAT; 148 case 34: 149 return CSR_VXRM; 150 case 35: 151 return CSR_VCSR; 152 case 36: 153 return CSR_VL; 154 case 37: 155 return CSR_VTYPE; 156 case 38: 157 return CSR_VLENB; 158 default: 159 /* Unknown register. */ 160 return 0; 161 } 162 } 163 164 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) 165 { 166 uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; 167 if (n < 32) { 168 int i; 169 int cnt = 0; 170 for (i = 0; i < vlenb; i += 8) { 171 cnt += gdb_get_reg64(buf, 172 env->vreg[(n * vlenb + i) / 8]); 173 } 174 return cnt; 175 } 176 177 int csrno = riscv_gdb_vector_csrno(n); 178 179 if (!csrno) { 180 return 0; 181 } 182 183 target_ulong val = 0; 184 int result = riscv_csrrw_debug(env, csrno, &val, 0, 0); 185 186 if (result == 0) { 187 return gdb_get_regl(buf, val); 188 } 189 190 return 0; 191 } 192 193 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) 194 { 195 uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; 196 if (n < 32) { 197 int i; 198 for (i = 0; i < vlenb; i += 8) { 199 env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); 200 } 201 return vlenb; 202 } 203 204 int csrno = riscv_gdb_vector_csrno(n); 205 206 if (!csrno) { 207 return 0; 208 } 209 210 target_ulong val = ldtul_p(mem_buf); 211 int result = riscv_csrrw_debug(env, csrno, NULL, val, -1); 212 213 if (result == 0) { 214 return sizeof(target_ulong); 215 } 216 217 return 0; 218 } 219 220 static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) 221 { 222 if (n < CSR_TABLE_SIZE) { 223 target_ulong val = 0; 224 int result; 225 226 result = riscv_csrrw_debug(env, n, &val, 0, 0); 227 if (result == RISCV_EXCP_NONE) { 228 return gdb_get_regl(buf, val); 229 } 230 } 231 return 0; 232 } 233 234 static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) 235 { 236 if (n < CSR_TABLE_SIZE) { 237 target_ulong val = ldtul_p(mem_buf); 238 int result; 239 240 result = riscv_csrrw_debug(env, n, NULL, val, -1); 241 if (result == RISCV_EXCP_NONE) { 242 return sizeof(target_ulong); 243 } 244 } 245 return 0; 246 } 247 248 static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) 249 { 250 if (n == 0) { 251 #ifdef CONFIG_USER_ONLY 252 return gdb_get_regl(buf, 0); 253 #else 254 return gdb_get_regl(buf, cs->priv); 255 #endif 256 } 257 return 0; 258 } 259 260 static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) 261 { 262 if (n == 0) { 263 #ifndef CONFIG_USER_ONLY 264 cs->priv = ldtul_p(mem_buf) & 0x3; 265 if (cs->priv == PRV_H) { 266 cs->priv = PRV_S; 267 } 268 #endif 269 return sizeof(target_ulong); 270 } 271 return 0; 272 } 273 274 static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) 275 { 276 RISCVCPU *cpu = RISCV_CPU(cs); 277 CPURISCVState *env = &cpu->env; 278 GString *s = g_string_new(NULL); 279 riscv_csr_predicate_fn predicate; 280 int bitsize = 16 << env->misa_mxl_max; 281 int i; 282 283 g_string_printf(s, "<?xml version=\"1.0\"?>"); 284 g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"); 285 g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">"); 286 287 for (i = 0; i < CSR_TABLE_SIZE; i++) { 288 predicate = csr_ops[i].predicate; 289 if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) { 290 if (csr_ops[i].name) { 291 g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name); 292 } else { 293 g_string_append_printf(s, "<reg name=\"csr%03x\"", i); 294 } 295 g_string_append_printf(s, " bitsize=\"%d\"", bitsize); 296 g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i); 297 } 298 } 299 300 g_string_append_printf(s, "</feature>"); 301 302 cpu->dyn_csr_xml = g_string_free(s, false); 303 return CSR_TABLE_SIZE; 304 } 305 306 static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) 307 { 308 RISCVCPU *cpu = RISCV_CPU(cs); 309 GString *s = g_string_new(NULL); 310 g_autoptr(GString) ts = g_string_new(""); 311 int reg_width = cpu->cfg.vlen; 312 int num_regs = 0; 313 int i; 314 315 g_string_printf(s, "<?xml version=\"1.0\"?>"); 316 g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); 317 g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.vector\">"); 318 319 /* First define types and totals in a whole VL */ 320 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 321 int count = reg_width / vec_lanes[i].size; 322 g_string_printf(ts, "%s", vec_lanes[i].id); 323 g_string_append_printf(s, 324 "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", 325 ts->str, vec_lanes[i].gdb_type, count); 326 } 327 328 /* Define unions */ 329 g_string_append_printf(s, "<union id=\"riscv_vector\">"); 330 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 331 g_string_append_printf(s, "<field name=\"%c\" type=\"%s\"/>", 332 vec_lanes[i].suffix, 333 vec_lanes[i].id); 334 } 335 g_string_append(s, "</union>"); 336 337 /* Define vector registers */ 338 for (i = 0; i < 32; i++) { 339 g_string_append_printf(s, 340 "<reg name=\"v%d\" bitsize=\"%d\"" 341 " regnum=\"%d\" group=\"vector\"" 342 " type=\"riscv_vector\"/>", 343 i, reg_width, base_reg++); 344 num_regs++; 345 } 346 347 /* Define vector CSRs */ 348 const char *vector_csrs[7] = { 349 "vstart", "vxsat", "vxrm", "vcsr", 350 "vl", "vtype", "vlenb" 351 }; 352 353 for (i = 0; i < 7; i++) { 354 g_string_append_printf(s, 355 "<reg name=\"%s\" bitsize=\"%d\"" 356 " regnum=\"%d\" group=\"vector\"" 357 " type=\"int\"/>", 358 vector_csrs[i], TARGET_LONG_BITS, base_reg++); 359 num_regs++; 360 } 361 362 g_string_append_printf(s, "</feature>"); 363 364 cpu->dyn_vreg_xml = g_string_free(s, false); 365 return num_regs; 366 } 367 368 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 369 { 370 RISCVCPU *cpu = RISCV_CPU(cs); 371 CPURISCVState *env = &cpu->env; 372 if (env->misa_ext & RVD) { 373 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 374 36, "riscv-64bit-fpu.xml", 0); 375 } else if (env->misa_ext & RVF) { 376 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 377 36, "riscv-32bit-fpu.xml", 0); 378 } 379 if (env->misa_ext & RVV) { 380 gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, 381 ricsv_gen_dynamic_vector_xml(cs, 382 cs->gdb_num_regs), 383 "riscv-vector.xml", 0); 384 } 385 #if defined(TARGET_RISCV32) 386 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 387 1, "riscv-32bit-virtual.xml", 0); 388 #elif defined(TARGET_RISCV64) 389 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 390 1, "riscv-64bit-virtual.xml", 0); 391 #endif 392 393 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 394 riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs), 395 "riscv-csr.xml", 0); 396 } 397