1 /* 2 * RISC-V GDB Server Stub 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "exec/gdbstub.h" 21 #include "gdbstub/helpers.h" 22 #include "cpu.h" 23 24 struct TypeSize { 25 const char *gdb_type; 26 const char *id; 27 int size; 28 const char suffix; 29 }; 30 31 static const struct TypeSize vec_lanes[] = { 32 /* quads */ 33 { "uint128", "quads", 128, 'q' }, 34 /* 64 bit */ 35 { "uint64", "longs", 64, 'l' }, 36 /* 32 bit */ 37 { "uint32", "words", 32, 'w' }, 38 /* 16 bit */ 39 { "uint16", "shorts", 16, 's' }, 40 /* 41 * TODO: currently there is no reliable way of telling 42 * if the remote gdb actually understands ieee_half so 43 * we don't expose it in the target description for now. 44 * { "ieee_half", 16, 'h', 'f' }, 45 */ 46 /* bytes */ 47 { "uint8", "bytes", 8, 'b' }, 48 }; 49 50 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 51 { 52 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 53 RISCVCPU *cpu = RISCV_CPU(cs); 54 CPURISCVState *env = &cpu->env; 55 target_ulong tmp; 56 57 if (n < 32) { 58 tmp = env->gpr[n]; 59 } else if (n == 32) { 60 tmp = env->pc; 61 } else { 62 return 0; 63 } 64 65 switch (mcc->misa_mxl_max) { 66 case MXL_RV32: 67 return gdb_get_reg32(mem_buf, tmp); 68 case MXL_RV64: 69 case MXL_RV128: 70 return gdb_get_reg64(mem_buf, tmp); 71 default: 72 g_assert_not_reached(); 73 } 74 return 0; 75 } 76 77 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 78 { 79 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 80 RISCVCPU *cpu = RISCV_CPU(cs); 81 CPURISCVState *env = &cpu->env; 82 int length = 0; 83 target_ulong tmp; 84 85 switch (mcc->misa_mxl_max) { 86 case MXL_RV32: 87 tmp = (int32_t)ldl_p(mem_buf); 88 length = 4; 89 break; 90 case MXL_RV64: 91 case MXL_RV128: 92 if (env->xl < MXL_RV64) { 93 tmp = (int32_t)ldq_p(mem_buf); 94 } else { 95 tmp = ldq_p(mem_buf); 96 } 97 length = 8; 98 break; 99 default: 100 g_assert_not_reached(); 101 } 102 if (n > 0 && n < 32) { 103 env->gpr[n] = tmp; 104 } else if (n == 32) { 105 env->pc = tmp; 106 } 107 108 return length; 109 } 110 111 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) 112 { 113 if (n < 32) { 114 if (env->misa_ext & RVD) { 115 return gdb_get_reg64(buf, env->fpr[n]); 116 } 117 if (env->misa_ext & RVF) { 118 return gdb_get_reg32(buf, env->fpr[n]); 119 } 120 } 121 return 0; 122 } 123 124 static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) 125 { 126 if (n < 32) { 127 env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ 128 return sizeof(uint64_t); 129 } 130 return 0; 131 } 132 133 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) 134 { 135 uint16_t vlenb = riscv_cpu_cfg(env)->vlenb; 136 if (n < 32) { 137 int i; 138 int cnt = 0; 139 for (i = 0; i < vlenb; i += 8) { 140 cnt += gdb_get_reg64(buf, 141 env->vreg[(n * vlenb + i) / 8]); 142 } 143 return cnt; 144 } 145 146 return 0; 147 } 148 149 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) 150 { 151 uint16_t vlenb = riscv_cpu_cfg(env)->vlenb; 152 if (n < 32) { 153 int i; 154 for (i = 0; i < vlenb; i += 8) { 155 env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); 156 } 157 return vlenb; 158 } 159 160 return 0; 161 } 162 163 static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) 164 { 165 if (n < CSR_TABLE_SIZE) { 166 target_ulong val = 0; 167 int result; 168 169 result = riscv_csrrw_debug(env, n, &val, 0, 0); 170 if (result == RISCV_EXCP_NONE) { 171 return gdb_get_regl(buf, val); 172 } 173 } 174 return 0; 175 } 176 177 static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) 178 { 179 if (n < CSR_TABLE_SIZE) { 180 target_ulong val = ldtul_p(mem_buf); 181 int result; 182 183 result = riscv_csrrw_debug(env, n, NULL, val, -1); 184 if (result == RISCV_EXCP_NONE) { 185 return sizeof(target_ulong); 186 } 187 } 188 return 0; 189 } 190 191 static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) 192 { 193 if (n == 0) { 194 #ifdef CONFIG_USER_ONLY 195 return gdb_get_regl(buf, 0); 196 #else 197 return gdb_get_regl(buf, cs->priv); 198 #endif 199 } 200 return 0; 201 } 202 203 static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) 204 { 205 if (n == 0) { 206 #ifndef CONFIG_USER_ONLY 207 cs->priv = ldtul_p(mem_buf) & 0x3; 208 if (cs->priv == PRV_RESERVED) { 209 cs->priv = PRV_S; 210 } 211 #endif 212 return sizeof(target_ulong); 213 } 214 return 0; 215 } 216 217 static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg) 218 { 219 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 220 RISCVCPU *cpu = RISCV_CPU(cs); 221 CPURISCVState *env = &cpu->env; 222 GDBFeatureBuilder builder; 223 riscv_csr_predicate_fn predicate; 224 int bitsize = riscv_cpu_max_xlen(mcc); 225 const char *name; 226 int i; 227 228 #if !defined(CONFIG_USER_ONLY) 229 env->debugger = true; 230 #endif 231 232 /* Until gdb knows about 128-bit registers */ 233 if (bitsize > 64) { 234 bitsize = 64; 235 } 236 237 gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature, 238 "org.gnu.gdb.riscv.csr", "riscv-csr.xml", 239 base_reg); 240 241 for (i = 0; i < CSR_TABLE_SIZE; i++) { 242 if (env->priv_ver < csr_ops[i].min_priv_ver) { 243 continue; 244 } 245 predicate = csr_ops[i].predicate; 246 if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) { 247 g_autofree char *dynamic_name = NULL; 248 name = csr_ops[i].name; 249 if (!name) { 250 dynamic_name = g_strdup_printf("csr%03x", i); 251 name = dynamic_name; 252 } 253 254 gdb_feature_builder_append_reg(&builder, name, bitsize, i, 255 "int", NULL); 256 } 257 } 258 259 gdb_feature_builder_end(&builder); 260 261 #if !defined(CONFIG_USER_ONLY) 262 env->debugger = false; 263 #endif 264 265 return &cpu->dyn_csr_feature; 266 } 267 268 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg) 269 { 270 RISCVCPU *cpu = RISCV_CPU(cs); 271 int reg_width = cpu->cfg.vlenb; 272 GDBFeatureBuilder builder; 273 int i; 274 275 gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature, 276 "org.gnu.gdb.riscv.vector", "riscv-vector.xml", 277 base_reg); 278 279 /* First define types and totals in a whole VL */ 280 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 281 int count = reg_width / vec_lanes[i].size; 282 gdb_feature_builder_append_tag( 283 &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", 284 vec_lanes[i].id, vec_lanes[i].gdb_type, count); 285 } 286 287 /* Define unions */ 288 gdb_feature_builder_append_tag(&builder, "<union id=\"riscv_vector\">"); 289 for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { 290 gdb_feature_builder_append_tag(&builder, 291 "<field name=\"%c\" type=\"%s\"/>", 292 vec_lanes[i].suffix, vec_lanes[i].id); 293 } 294 gdb_feature_builder_append_tag(&builder, "</union>"); 295 296 /* Define vector registers */ 297 for (i = 0; i < 32; i++) { 298 gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i), 299 reg_width, i, "riscv_vector", "vector"); 300 } 301 302 gdb_feature_builder_end(&builder); 303 304 return &cpu->dyn_vreg_feature; 305 } 306 307 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) 308 { 309 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 310 RISCVCPU *cpu = RISCV_CPU(cs); 311 CPURISCVState *env = &cpu->env; 312 if (env->misa_ext & RVD) { 313 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 314 32, "riscv-64bit-fpu.xml", 0); 315 } else if (env->misa_ext & RVF) { 316 gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 317 32, "riscv-32bit-fpu.xml", 0); 318 } 319 if (env->misa_ext & RVV) { 320 gdb_register_coprocessor(cs, riscv_gdb_get_vector, 321 riscv_gdb_set_vector, 322 ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs, 323 "riscv-vector.xml", 0); 324 } 325 switch (mcc->misa_mxl_max) { 326 case MXL_RV32: 327 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, 328 riscv_gdb_set_virtual, 329 1, "riscv-32bit-virtual.xml", 0); 330 break; 331 case MXL_RV64: 332 case MXL_RV128: 333 gdb_register_coprocessor(cs, riscv_gdb_get_virtual, 334 riscv_gdb_set_virtual, 335 1, "riscv-64bit-virtual.xml", 0); 336 break; 337 default: 338 g_assert_not_reached(); 339 } 340 341 if (cpu->cfg.ext_zicsr) { 342 gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 343 riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs, 344 "riscv-csr.xml", 0); 345 } 346 } 347