1 /* 2 * QEMU RISC-V Native Debug Support 3 * 4 * Copyright (c) 2022 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2 or later, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef RISCV_DEBUG_H 23 #define RISCV_DEBUG_H 24 25 #define RV_MAX_TRIGGERS 2 26 27 /* register index of tdata CSRs */ 28 enum { 29 TDATA1 = 0, 30 TDATA2, 31 TDATA3, 32 TDATA_NUM 33 }; 34 35 typedef enum { 36 TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */ 37 TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */ 38 TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */ 39 TRIGGER_TYPE_INT = 4, /* interrupt trigger */ 40 TRIGGER_TYPE_EXCP = 5, /* exception trigger */ 41 TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */ 42 TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */ 43 TRIGGER_TYPE_UNAVAIL = 15, /* trigger exists, but unavailable */ 44 TRIGGER_TYPE_NUM 45 } trigger_type_t; 46 47 typedef struct { 48 target_ulong mcontrol; 49 target_ulong maddress; 50 struct CPUBreakpoint *bp; 51 struct CPUWatchpoint *wp; 52 } type2_trigger_t; 53 54 /* tdata1 field masks */ 55 56 #define RV32_TYPE(t) ((uint32_t)(t) << 28) 57 #define RV32_TYPE_MASK (0xf << 28) 58 #define RV32_DMODE BIT(27) 59 #define RV32_DATA_MASK 0x7ffffff 60 #define RV64_TYPE(t) ((uint64_t)(t) << 60) 61 #define RV64_TYPE_MASK (0xfULL << 60) 62 #define RV64_DMODE BIT_ULL(59) 63 #define RV64_DATA_MASK 0x7ffffffffffffff 64 65 /* mcontrol field masks */ 66 67 #define TYPE2_LOAD BIT(0) 68 #define TYPE2_STORE BIT(1) 69 #define TYPE2_EXEC BIT(2) 70 #define TYPE2_U BIT(3) 71 #define TYPE2_S BIT(4) 72 #define TYPE2_M BIT(6) 73 #define TYPE2_MATCH (0xf << 7) 74 #define TYPE2_CHAIN BIT(11) 75 #define TYPE2_ACTION (0xf << 12) 76 #define TYPE2_SIZELO (0x3 << 16) 77 #define TYPE2_TIMING BIT(18) 78 #define TYPE2_SELECT BIT(19) 79 #define TYPE2_HIT BIT(20) 80 #define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ 81 82 /* access size */ 83 enum { 84 SIZE_ANY = 0, 85 SIZE_1B, 86 SIZE_2B, 87 SIZE_4B, 88 SIZE_6B, 89 SIZE_8B, 90 SIZE_10B, 91 SIZE_12B, 92 SIZE_14B, 93 SIZE_16B, 94 SIZE_NUM = 16 95 }; 96 97 bool tdata_available(CPURISCVState *env, int tdata_index); 98 99 target_ulong tselect_csr_read(CPURISCVState *env); 100 void tselect_csr_write(CPURISCVState *env, target_ulong val); 101 102 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); 103 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); 104 105 void riscv_cpu_debug_excp_handler(CPUState *cs); 106 bool riscv_cpu_debug_check_breakpoint(CPUState *cs); 107 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 108 109 void riscv_trigger_init(CPURISCVState *env); 110 111 #endif /* RISCV_DEBUG_H */ 112