1 /* 2 * QEMU RISC-V Native Debug Support 3 * 4 * Copyright (c) 2022 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This provides the native debug support via the Trigger Module, as defined 10 * in the RISC-V Debug Specification: 11 * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/log.h" 28 #include "qapi/error.h" 29 #include "cpu.h" 30 #include "trace.h" 31 #include "exec/exec-all.h" 32 #include "exec/helper-proto.h" 33 #include "system/cpu-timers.h" 34 35 /* 36 * The following M-mode trigger CSRs are implemented: 37 * 38 * - tselect 39 * - tdata1 40 * - tdata2 41 * - tdata3 42 * - tinfo 43 * 44 * The following triggers are initialized by default: 45 * 46 * Index | Type | tdata mapping | Description 47 * ------+------+------------------------+------------ 48 * 0 | 2 | tdata1, tdata2 | Address / Data Match 49 * 1 | 2 | tdata1, tdata2 | Address / Data Match 50 */ 51 52 /* tdata availability of a trigger */ 53 typedef bool tdata_avail[TDATA_NUM]; 54 55 static tdata_avail tdata_mapping[TRIGGER_TYPE_NUM] = { 56 [TRIGGER_TYPE_NO_EXIST] = { false, false, false }, 57 [TRIGGER_TYPE_AD_MATCH] = { true, true, true }, 58 [TRIGGER_TYPE_INST_CNT] = { true, false, true }, 59 [TRIGGER_TYPE_INT] = { true, true, true }, 60 [TRIGGER_TYPE_EXCP] = { true, true, true }, 61 [TRIGGER_TYPE_AD_MATCH6] = { true, true, true }, 62 [TRIGGER_TYPE_EXT_SRC] = { true, false, false }, 63 [TRIGGER_TYPE_UNAVAIL] = { true, true, true } 64 }; 65 66 /* only breakpoint size 1/2/4/8 supported */ 67 static int access_size[SIZE_NUM] = { 68 [SIZE_ANY] = 0, 69 [SIZE_1B] = 1, 70 [SIZE_2B] = 2, 71 [SIZE_4B] = 4, 72 [SIZE_6B] = -1, 73 [SIZE_8B] = 8, 74 [6 ... 15] = -1, 75 }; 76 77 static inline target_ulong extract_trigger_type(CPURISCVState *env, 78 target_ulong tdata1) 79 { 80 switch (riscv_cpu_mxl(env)) { 81 case MXL_RV32: 82 return extract32(tdata1, 28, 4); 83 case MXL_RV64: 84 case MXL_RV128: 85 return extract64(tdata1, 60, 4); 86 default: 87 g_assert_not_reached(); 88 } 89 } 90 91 static inline target_ulong get_trigger_type(CPURISCVState *env, 92 target_ulong trigger_index) 93 { 94 return extract_trigger_type(env, env->tdata1[trigger_index]); 95 } 96 97 static trigger_action_t get_trigger_action(CPURISCVState *env, 98 target_ulong trigger_index) 99 { 100 target_ulong tdata1 = env->tdata1[trigger_index]; 101 int trigger_type = get_trigger_type(env, trigger_index); 102 trigger_action_t action = DBG_ACTION_NONE; 103 104 switch (trigger_type) { 105 case TRIGGER_TYPE_AD_MATCH: 106 action = (tdata1 & TYPE2_ACTION) >> 12; 107 break; 108 case TRIGGER_TYPE_AD_MATCH6: 109 action = (tdata1 & TYPE6_ACTION) >> 12; 110 break; 111 case TRIGGER_TYPE_INST_CNT: 112 case TRIGGER_TYPE_INT: 113 case TRIGGER_TYPE_EXCP: 114 case TRIGGER_TYPE_EXT_SRC: 115 qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", 116 trigger_type); 117 break; 118 case TRIGGER_TYPE_NO_EXIST: 119 case TRIGGER_TYPE_UNAVAIL: 120 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n", 121 trigger_type); 122 break; 123 default: 124 g_assert_not_reached(); 125 } 126 127 return action; 128 } 129 130 static inline target_ulong build_tdata1(CPURISCVState *env, 131 trigger_type_t type, 132 bool dmode, target_ulong data) 133 { 134 target_ulong tdata1; 135 136 switch (riscv_cpu_mxl(env)) { 137 case MXL_RV32: 138 tdata1 = RV32_TYPE(type) | 139 (dmode ? RV32_DMODE : 0) | 140 (data & RV32_DATA_MASK); 141 break; 142 case MXL_RV64: 143 case MXL_RV128: 144 tdata1 = RV64_TYPE(type) | 145 (dmode ? RV64_DMODE : 0) | 146 (data & RV64_DATA_MASK); 147 break; 148 default: 149 g_assert_not_reached(); 150 } 151 152 return tdata1; 153 } 154 155 bool tdata_available(CPURISCVState *env, int tdata_index) 156 { 157 int trigger_type = get_trigger_type(env, env->trigger_cur); 158 159 if (unlikely(tdata_index >= TDATA_NUM)) { 160 return false; 161 } 162 163 return tdata_mapping[trigger_type][tdata_index]; 164 } 165 166 target_ulong tselect_csr_read(CPURISCVState *env) 167 { 168 return env->trigger_cur; 169 } 170 171 void tselect_csr_write(CPURISCVState *env, target_ulong val) 172 { 173 if (val < RV_MAX_TRIGGERS) { 174 env->trigger_cur = val; 175 } 176 } 177 178 static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, 179 trigger_type_t t) 180 { 181 uint32_t type, dmode; 182 target_ulong tdata1; 183 184 switch (riscv_cpu_mxl(env)) { 185 case MXL_RV32: 186 type = extract32(val, 28, 4); 187 dmode = extract32(val, 27, 1); 188 tdata1 = RV32_TYPE(t); 189 break; 190 case MXL_RV64: 191 case MXL_RV128: 192 type = extract64(val, 60, 4); 193 dmode = extract64(val, 59, 1); 194 tdata1 = RV64_TYPE(t); 195 break; 196 default: 197 g_assert_not_reached(); 198 } 199 200 if (type != t) { 201 qemu_log_mask(LOG_GUEST_ERROR, 202 "ignoring type write to tdata1 register\n"); 203 } 204 205 if (dmode != 0) { 206 qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n"); 207 } 208 209 return tdata1; 210 } 211 212 static inline void warn_always_zero_bit(target_ulong val, target_ulong mask, 213 const char *msg) 214 { 215 if (val & mask) { 216 qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg); 217 } 218 } 219 220 static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3) 221 { 222 target_ulong mhvalue, mhselect; 223 target_ulong mhselect_new; 224 target_ulong textra; 225 const uint32_t mhselect_no_rvh[8] = { 0, 0, 0, 0, 4, 4, 4, 4 }; 226 227 switch (riscv_cpu_mxl(env)) { 228 case MXL_RV32: 229 mhvalue = get_field(tdata3, TEXTRA32_MHVALUE); 230 mhselect = get_field(tdata3, TEXTRA32_MHSELECT); 231 /* Validate unimplemented (always zero) bits */ 232 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SBYTEMASK, 233 "sbytemask"); 234 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SVALUE, 235 "svalue"); 236 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SSELECT, 237 "sselect"); 238 break; 239 case MXL_RV64: 240 case MXL_RV128: 241 mhvalue = get_field(tdata3, TEXTRA64_MHVALUE); 242 mhselect = get_field(tdata3, TEXTRA64_MHSELECT); 243 /* Validate unimplemented (always zero) bits */ 244 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SBYTEMASK, 245 "sbytemask"); 246 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SVALUE, 247 "svalue"); 248 warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SSELECT, 249 "sselect"); 250 break; 251 default: 252 g_assert_not_reached(); 253 } 254 255 /* Validate mhselect. */ 256 mhselect_new = mhselect_no_rvh[mhselect]; 257 if (mhselect != mhselect_new) { 258 qemu_log_mask(LOG_UNIMP, "mhselect only supports 0 or 4 for now\n"); 259 } 260 261 /* Write legal values into textra */ 262 textra = 0; 263 switch (riscv_cpu_mxl(env)) { 264 case MXL_RV32: 265 textra = set_field(textra, TEXTRA32_MHVALUE, mhvalue); 266 textra = set_field(textra, TEXTRA32_MHSELECT, mhselect_new); 267 break; 268 case MXL_RV64: 269 case MXL_RV128: 270 textra = set_field(textra, TEXTRA64_MHVALUE, mhvalue); 271 textra = set_field(textra, TEXTRA64_MHSELECT, mhselect_new); 272 break; 273 default: 274 g_assert_not_reached(); 275 } 276 277 return textra; 278 } 279 280 static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index) 281 { 282 trigger_action_t action = get_trigger_action(env, trigger_index); 283 284 switch (action) { 285 case DBG_ACTION_NONE: 286 break; 287 case DBG_ACTION_BP: 288 riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); 289 break; 290 case DBG_ACTION_DBG_MODE: 291 case DBG_ACTION_TRACE0: 292 case DBG_ACTION_TRACE1: 293 case DBG_ACTION_TRACE2: 294 case DBG_ACTION_TRACE3: 295 case DBG_ACTION_EXT_DBG0: 296 case DBG_ACTION_EXT_DBG1: 297 qemu_log_mask(LOG_UNIMP, "action: %d is not supported\n", action); 298 break; 299 default: 300 g_assert_not_reached(); 301 } 302 } 303 304 /* 305 * Check the privilege level of specific trigger matches CPU's current privilege 306 * level. 307 */ 308 static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type, 309 int trigger_index) 310 { 311 target_ulong ctrl = env->tdata1[trigger_index]; 312 313 switch (type) { 314 case TRIGGER_TYPE_AD_MATCH: 315 /* type 2 trigger cannot be fired in VU/VS mode */ 316 if (env->virt_enabled) { 317 return false; 318 } 319 /* check U/S/M bit against current privilege level */ 320 if ((ctrl >> 3) & BIT(env->priv)) { 321 return true; 322 } 323 break; 324 case TRIGGER_TYPE_AD_MATCH6: 325 if (env->virt_enabled) { 326 /* check VU/VS bit against current privilege level */ 327 if ((ctrl >> 23) & BIT(env->priv)) { 328 return true; 329 } 330 } else { 331 /* check U/S/M bit against current privilege level */ 332 if ((ctrl >> 3) & BIT(env->priv)) { 333 return true; 334 } 335 } 336 break; 337 case TRIGGER_TYPE_INST_CNT: 338 if (env->virt_enabled) { 339 /* check VU/VS bit against current privilege level */ 340 if ((ctrl >> 25) & BIT(env->priv)) { 341 return true; 342 } 343 } else { 344 /* check U/S/M bit against current privilege level */ 345 if ((ctrl >> 6) & BIT(env->priv)) { 346 return true; 347 } 348 } 349 break; 350 case TRIGGER_TYPE_INT: 351 case TRIGGER_TYPE_EXCP: 352 case TRIGGER_TYPE_EXT_SRC: 353 qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", type); 354 break; 355 case TRIGGER_TYPE_NO_EXIST: 356 case TRIGGER_TYPE_UNAVAIL: 357 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exist\n", 358 type); 359 break; 360 default: 361 g_assert_not_reached(); 362 } 363 364 return false; 365 } 366 367 static bool trigger_textra_match(CPURISCVState *env, trigger_type_t type, 368 int trigger_index) 369 { 370 target_ulong textra = env->tdata3[trigger_index]; 371 target_ulong mhvalue, mhselect; 372 373 if (type < TRIGGER_TYPE_AD_MATCH || type > TRIGGER_TYPE_AD_MATCH6) { 374 /* textra checking is only applicable when type is 2, 3, 4, 5, or 6 */ 375 return true; 376 } 377 378 switch (riscv_cpu_mxl(env)) { 379 case MXL_RV32: 380 mhvalue = get_field(textra, TEXTRA32_MHVALUE); 381 mhselect = get_field(textra, TEXTRA32_MHSELECT); 382 break; 383 case MXL_RV64: 384 case MXL_RV128: 385 mhvalue = get_field(textra, TEXTRA64_MHVALUE); 386 mhselect = get_field(textra, TEXTRA64_MHSELECT); 387 break; 388 default: 389 g_assert_not_reached(); 390 } 391 392 /* Check mhvalue and mhselect. */ 393 switch (mhselect) { 394 case MHSELECT_IGNORE: 395 break; 396 case MHSELECT_MCONTEXT: 397 /* Match if the low bits of mcontext/hcontext equal mhvalue. */ 398 if (mhvalue != env->mcontext) { 399 return false; 400 } 401 break; 402 default: 403 break; 404 } 405 406 return true; 407 } 408 409 /* Common matching conditions for all types of the triggers. */ 410 static bool trigger_common_match(CPURISCVState *env, trigger_type_t type, 411 int trigger_index) 412 { 413 return trigger_priv_match(env, type, trigger_index) && 414 trigger_textra_match(env, type, trigger_index); 415 } 416 417 /* type 2 trigger */ 418 419 static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl) 420 { 421 uint32_t sizelo, sizehi = 0; 422 423 if (riscv_cpu_mxl(env) == MXL_RV64) { 424 sizehi = extract32(ctrl, 21, 2); 425 } 426 sizelo = extract32(ctrl, 16, 2); 427 return (sizehi << 2) | sizelo; 428 } 429 430 static inline bool type2_breakpoint_enabled(target_ulong ctrl) 431 { 432 bool mode = !!(ctrl & (TYPE2_U | TYPE2_S | TYPE2_M)); 433 bool rwx = !!(ctrl & (TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); 434 435 return mode && rwx; 436 } 437 438 static target_ulong type2_mcontrol_validate(CPURISCVState *env, 439 target_ulong ctrl) 440 { 441 target_ulong val; 442 uint32_t size; 443 444 /* validate the generic part first */ 445 val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH); 446 447 /* validate unimplemented (always zero) bits */ 448 warn_always_zero_bit(ctrl, TYPE2_MATCH, "match"); 449 warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain"); 450 warn_always_zero_bit(ctrl, TYPE2_ACTION, "action"); 451 warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing"); 452 warn_always_zero_bit(ctrl, TYPE2_SELECT, "select"); 453 warn_always_zero_bit(ctrl, TYPE2_HIT, "hit"); 454 455 /* validate size encoding */ 456 size = type2_breakpoint_size(env, ctrl); 457 if (access_size[size] == -1) { 458 qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " 459 "SIZE_ANY\n", size); 460 } else { 461 val |= (ctrl & TYPE2_SIZELO); 462 if (riscv_cpu_mxl(env) == MXL_RV64) { 463 val |= (ctrl & TYPE2_SIZEHI); 464 } 465 } 466 467 /* keep the mode and attribute bits */ 468 val |= (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M | 469 TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); 470 471 return val; 472 } 473 474 static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) 475 { 476 target_ulong ctrl = env->tdata1[index]; 477 target_ulong addr = env->tdata2[index]; 478 bool enabled = type2_breakpoint_enabled(ctrl); 479 CPUState *cs = env_cpu(env); 480 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 481 uint32_t size, def_size; 482 483 if (!enabled) { 484 return; 485 } 486 487 if (ctrl & TYPE2_EXEC) { 488 cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]); 489 } 490 491 if (ctrl & TYPE2_LOAD) { 492 flags |= BP_MEM_READ; 493 } 494 if (ctrl & TYPE2_STORE) { 495 flags |= BP_MEM_WRITE; 496 } 497 498 if (flags & BP_MEM_ACCESS) { 499 size = type2_breakpoint_size(env, ctrl); 500 if (size != 0) { 501 cpu_watchpoint_insert(cs, addr, size, flags, 502 &env->cpu_watchpoint[index]); 503 } else { 504 def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4; 505 506 cpu_watchpoint_insert(cs, addr, def_size, flags, 507 &env->cpu_watchpoint[index]); 508 } 509 } 510 } 511 512 static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index) 513 { 514 CPUState *cs = env_cpu(env); 515 516 if (env->cpu_breakpoint[index]) { 517 cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]); 518 env->cpu_breakpoint[index] = NULL; 519 } 520 521 if (env->cpu_watchpoint[index]) { 522 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); 523 env->cpu_watchpoint[index] = NULL; 524 } 525 } 526 527 static void type2_reg_write(CPURISCVState *env, target_ulong index, 528 int tdata_index, target_ulong val) 529 { 530 target_ulong new_val; 531 532 switch (tdata_index) { 533 case TDATA1: 534 new_val = type2_mcontrol_validate(env, val); 535 if (new_val != env->tdata1[index]) { 536 env->tdata1[index] = new_val; 537 type2_breakpoint_remove(env, index); 538 type2_breakpoint_insert(env, index); 539 } 540 break; 541 case TDATA2: 542 if (val != env->tdata2[index]) { 543 env->tdata2[index] = val; 544 type2_breakpoint_remove(env, index); 545 type2_breakpoint_insert(env, index); 546 } 547 break; 548 case TDATA3: 549 env->tdata3[index] = textra_validate(env, val); 550 break; 551 default: 552 g_assert_not_reached(); 553 } 554 } 555 556 /* type 6 trigger */ 557 558 static inline bool type6_breakpoint_enabled(target_ulong ctrl) 559 { 560 bool mode = !!(ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M)); 561 bool rwx = !!(ctrl & (TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC)); 562 563 return mode && rwx; 564 } 565 566 static target_ulong type6_mcontrol6_validate(CPURISCVState *env, 567 target_ulong ctrl) 568 { 569 target_ulong val; 570 uint32_t size; 571 572 /* validate the generic part first */ 573 val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6); 574 575 /* validate unimplemented (always zero) bits */ 576 warn_always_zero_bit(ctrl, TYPE6_MATCH, "match"); 577 warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain"); 578 warn_always_zero_bit(ctrl, TYPE6_ACTION, "action"); 579 warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing"); 580 warn_always_zero_bit(ctrl, TYPE6_SELECT, "select"); 581 warn_always_zero_bit(ctrl, TYPE6_HIT, "hit"); 582 583 /* validate size encoding */ 584 size = extract32(ctrl, 16, 4); 585 if (access_size[size] == -1) { 586 qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " 587 "SIZE_ANY\n", size); 588 } else { 589 val |= (ctrl & TYPE6_SIZE); 590 } 591 592 /* keep the mode and attribute bits */ 593 val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M | 594 TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC)); 595 596 return val; 597 } 598 599 static void type6_breakpoint_insert(CPURISCVState *env, target_ulong index) 600 { 601 target_ulong ctrl = env->tdata1[index]; 602 target_ulong addr = env->tdata2[index]; 603 bool enabled = type6_breakpoint_enabled(ctrl); 604 CPUState *cs = env_cpu(env); 605 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; 606 uint32_t size; 607 608 if (!enabled) { 609 return; 610 } 611 612 if (ctrl & TYPE6_EXEC) { 613 cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]); 614 } 615 616 if (ctrl & TYPE6_LOAD) { 617 flags |= BP_MEM_READ; 618 } 619 620 if (ctrl & TYPE6_STORE) { 621 flags |= BP_MEM_WRITE; 622 } 623 624 if (flags & BP_MEM_ACCESS) { 625 size = extract32(ctrl, 16, 4); 626 if (size != 0) { 627 cpu_watchpoint_insert(cs, addr, size, flags, 628 &env->cpu_watchpoint[index]); 629 } else { 630 cpu_watchpoint_insert(cs, addr, 8, flags, 631 &env->cpu_watchpoint[index]); 632 } 633 } 634 } 635 636 static void type6_breakpoint_remove(CPURISCVState *env, target_ulong index) 637 { 638 type2_breakpoint_remove(env, index); 639 } 640 641 static void type6_reg_write(CPURISCVState *env, target_ulong index, 642 int tdata_index, target_ulong val) 643 { 644 target_ulong new_val; 645 646 switch (tdata_index) { 647 case TDATA1: 648 new_val = type6_mcontrol6_validate(env, val); 649 if (new_val != env->tdata1[index]) { 650 env->tdata1[index] = new_val; 651 type6_breakpoint_remove(env, index); 652 type6_breakpoint_insert(env, index); 653 } 654 break; 655 case TDATA2: 656 if (val != env->tdata2[index]) { 657 env->tdata2[index] = val; 658 type6_breakpoint_remove(env, index); 659 type6_breakpoint_insert(env, index); 660 } 661 break; 662 case TDATA3: 663 env->tdata3[index] = textra_validate(env, val); 664 break; 665 default: 666 g_assert_not_reached(); 667 } 668 } 669 670 /* icount trigger type */ 671 static inline int 672 itrigger_get_count(CPURISCVState *env, int index) 673 { 674 return get_field(env->tdata1[index], ITRIGGER_COUNT); 675 } 676 677 static inline void 678 itrigger_set_count(CPURISCVState *env, int index, int value) 679 { 680 env->tdata1[index] = set_field(env->tdata1[index], 681 ITRIGGER_COUNT, value); 682 } 683 684 static bool check_itrigger_priv(CPURISCVState *env, int index) 685 { 686 target_ulong tdata1 = env->tdata1[index]; 687 if (env->virt_enabled) { 688 /* check VU/VS bit against current privilege level */ 689 return (get_field(tdata1, ITRIGGER_VS) == env->priv) || 690 (get_field(tdata1, ITRIGGER_VU) == env->priv); 691 } else { 692 /* check U/S/M bit against current privilege level */ 693 return (get_field(tdata1, ITRIGGER_M) == env->priv) || 694 (get_field(tdata1, ITRIGGER_S) == env->priv) || 695 (get_field(tdata1, ITRIGGER_U) == env->priv); 696 } 697 } 698 699 bool riscv_itrigger_enabled(CPURISCVState *env) 700 { 701 int count; 702 for (int i = 0; i < RV_MAX_TRIGGERS; i++) { 703 if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) { 704 continue; 705 } 706 if (check_itrigger_priv(env, i)) { 707 continue; 708 } 709 count = itrigger_get_count(env, i); 710 if (!count) { 711 continue; 712 } 713 return true; 714 } 715 716 return false; 717 } 718 719 void helper_itrigger_match(CPURISCVState *env) 720 { 721 int count; 722 for (int i = 0; i < RV_MAX_TRIGGERS; i++) { 723 if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) { 724 continue; 725 } 726 if (!trigger_common_match(env, TRIGGER_TYPE_INST_CNT, i)) { 727 continue; 728 } 729 count = itrigger_get_count(env, i); 730 if (!count) { 731 continue; 732 } 733 itrigger_set_count(env, i, count--); 734 if (!count) { 735 env->itrigger_enabled = riscv_itrigger_enabled(env); 736 do_trigger_action(env, i); 737 } 738 } 739 } 740 741 static void riscv_itrigger_update_count(CPURISCVState *env) 742 { 743 int count, executed; 744 /* 745 * Record last icount, so that we can evaluate the executed instructions 746 * since last privilege mode change or timer expire. 747 */ 748 int64_t last_icount = env->last_icount, current_icount; 749 current_icount = env->last_icount = icount_get_raw(); 750 751 for (int i = 0; i < RV_MAX_TRIGGERS; i++) { 752 if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) { 753 continue; 754 } 755 count = itrigger_get_count(env, i); 756 if (!count) { 757 continue; 758 } 759 /* 760 * Only when privilege is changed or itrigger timer expires, 761 * the count field in itrigger tdata1 register is updated. 762 * And the count field in itrigger only contains remaining value. 763 */ 764 if (check_itrigger_priv(env, i)) { 765 /* 766 * If itrigger enabled in this privilege mode, the number of 767 * executed instructions since last privilege change 768 * should be reduced from current itrigger count. 769 */ 770 executed = current_icount - last_icount; 771 itrigger_set_count(env, i, count - executed); 772 if (count == executed) { 773 do_trigger_action(env, i); 774 } 775 } else { 776 /* 777 * If itrigger is not enabled in this privilege mode, 778 * the number of executed instructions will be discard and 779 * the count field in itrigger will not change. 780 */ 781 timer_mod(env->itrigger_timer[i], 782 current_icount + count); 783 } 784 } 785 } 786 787 static void riscv_itrigger_timer_cb(void *opaque) 788 { 789 riscv_itrigger_update_count((CPURISCVState *)opaque); 790 } 791 792 void riscv_itrigger_update_priv(CPURISCVState *env) 793 { 794 riscv_itrigger_update_count(env); 795 } 796 797 static target_ulong itrigger_validate(CPURISCVState *env, 798 target_ulong ctrl) 799 { 800 target_ulong val; 801 802 /* validate the generic part first */ 803 val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT); 804 805 /* validate unimplemented (always zero) bits */ 806 warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action"); 807 warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit"); 808 warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending"); 809 810 /* keep the mode and attribute bits */ 811 val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S | 812 ITRIGGER_M | ITRIGGER_COUNT); 813 814 return val; 815 } 816 817 static void itrigger_reg_write(CPURISCVState *env, target_ulong index, 818 int tdata_index, target_ulong val) 819 { 820 target_ulong new_val; 821 822 switch (tdata_index) { 823 case TDATA1: 824 /* set timer for icount */ 825 new_val = itrigger_validate(env, val); 826 if (new_val != env->tdata1[index]) { 827 env->tdata1[index] = new_val; 828 if (icount_enabled()) { 829 env->last_icount = icount_get_raw(); 830 /* set the count to timer */ 831 timer_mod(env->itrigger_timer[index], 832 env->last_icount + itrigger_get_count(env, index)); 833 } else { 834 env->itrigger_enabled = riscv_itrigger_enabled(env); 835 } 836 } 837 break; 838 case TDATA2: 839 qemu_log_mask(LOG_UNIMP, 840 "tdata2 is not supported for icount trigger\n"); 841 break; 842 case TDATA3: 843 env->tdata3[index] = textra_validate(env, val); 844 break; 845 default: 846 g_assert_not_reached(); 847 } 848 } 849 850 static int itrigger_get_adjust_count(CPURISCVState *env) 851 { 852 int count = itrigger_get_count(env, env->trigger_cur), executed; 853 if ((count != 0) && check_itrigger_priv(env, env->trigger_cur)) { 854 executed = icount_get_raw() - env->last_icount; 855 count += executed; 856 } 857 return count; 858 } 859 860 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) 861 { 862 int trigger_type; 863 switch (tdata_index) { 864 case TDATA1: 865 trigger_type = extract_trigger_type(env, 866 env->tdata1[env->trigger_cur]); 867 if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) { 868 return deposit64(env->tdata1[env->trigger_cur], 10, 14, 869 itrigger_get_adjust_count(env)); 870 } 871 return env->tdata1[env->trigger_cur]; 872 case TDATA2: 873 return env->tdata2[env->trigger_cur]; 874 case TDATA3: 875 return env->tdata3[env->trigger_cur]; 876 default: 877 g_assert_not_reached(); 878 } 879 } 880 881 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) 882 { 883 int trigger_type; 884 885 if (tdata_index == TDATA1) { 886 trigger_type = extract_trigger_type(env, val); 887 } else { 888 trigger_type = get_trigger_type(env, env->trigger_cur); 889 } 890 891 switch (trigger_type) { 892 case TRIGGER_TYPE_AD_MATCH: 893 type2_reg_write(env, env->trigger_cur, tdata_index, val); 894 break; 895 case TRIGGER_TYPE_AD_MATCH6: 896 type6_reg_write(env, env->trigger_cur, tdata_index, val); 897 break; 898 case TRIGGER_TYPE_INST_CNT: 899 itrigger_reg_write(env, env->trigger_cur, tdata_index, val); 900 break; 901 case TRIGGER_TYPE_INT: 902 case TRIGGER_TYPE_EXCP: 903 case TRIGGER_TYPE_EXT_SRC: 904 qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", 905 trigger_type); 906 break; 907 case TRIGGER_TYPE_NO_EXIST: 908 case TRIGGER_TYPE_UNAVAIL: 909 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n", 910 trigger_type); 911 break; 912 default: 913 g_assert_not_reached(); 914 } 915 } 916 917 target_ulong tinfo_csr_read(CPURISCVState *env) 918 { 919 /* assume all triggers support the same types of triggers */ 920 return BIT(TRIGGER_TYPE_AD_MATCH) | 921 BIT(TRIGGER_TYPE_AD_MATCH6); 922 } 923 924 void riscv_cpu_debug_excp_handler(CPUState *cs) 925 { 926 RISCVCPU *cpu = RISCV_CPU(cs); 927 CPURISCVState *env = &cpu->env; 928 929 if (cs->watchpoint_hit) { 930 if (cs->watchpoint_hit->flags & BP_CPU) { 931 do_trigger_action(env, DBG_ACTION_BP); 932 } 933 } else { 934 if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { 935 do_trigger_action(env, DBG_ACTION_BP); 936 } 937 } 938 } 939 940 bool riscv_cpu_debug_check_breakpoint(CPUState *cs) 941 { 942 RISCVCPU *cpu = RISCV_CPU(cs); 943 CPURISCVState *env = &cpu->env; 944 CPUBreakpoint *bp; 945 target_ulong ctrl; 946 target_ulong pc; 947 int trigger_type; 948 int i; 949 950 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { 951 for (i = 0; i < RV_MAX_TRIGGERS; i++) { 952 trigger_type = get_trigger_type(env, i); 953 954 if (!trigger_common_match(env, trigger_type, i)) { 955 continue; 956 } 957 958 switch (trigger_type) { 959 case TRIGGER_TYPE_AD_MATCH: 960 ctrl = env->tdata1[i]; 961 pc = env->tdata2[i]; 962 963 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) { 964 env->badaddr = pc; 965 return true; 966 } 967 break; 968 case TRIGGER_TYPE_AD_MATCH6: 969 ctrl = env->tdata1[i]; 970 pc = env->tdata2[i]; 971 972 if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) { 973 env->badaddr = pc; 974 return true; 975 } 976 break; 977 default: 978 /* other trigger types are not supported or irrelevant */ 979 break; 980 } 981 } 982 } 983 984 return false; 985 } 986 987 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) 988 { 989 RISCVCPU *cpu = RISCV_CPU(cs); 990 CPURISCVState *env = &cpu->env; 991 target_ulong ctrl; 992 target_ulong addr; 993 int trigger_type; 994 int flags; 995 int i; 996 997 for (i = 0; i < RV_MAX_TRIGGERS; i++) { 998 trigger_type = get_trigger_type(env, i); 999 1000 if (!trigger_common_match(env, trigger_type, i)) { 1001 continue; 1002 } 1003 1004 switch (trigger_type) { 1005 case TRIGGER_TYPE_AD_MATCH: 1006 ctrl = env->tdata1[i]; 1007 addr = env->tdata2[i]; 1008 flags = 0; 1009 1010 if (ctrl & TYPE2_LOAD) { 1011 flags |= BP_MEM_READ; 1012 } 1013 if (ctrl & TYPE2_STORE) { 1014 flags |= BP_MEM_WRITE; 1015 } 1016 1017 if ((wp->flags & flags) && (wp->vaddr == addr)) { 1018 return true; 1019 } 1020 break; 1021 case TRIGGER_TYPE_AD_MATCH6: 1022 ctrl = env->tdata1[i]; 1023 addr = env->tdata2[i]; 1024 flags = 0; 1025 1026 if (ctrl & TYPE6_LOAD) { 1027 flags |= BP_MEM_READ; 1028 } 1029 if (ctrl & TYPE6_STORE) { 1030 flags |= BP_MEM_WRITE; 1031 } 1032 1033 if ((wp->flags & flags) && (wp->vaddr == addr)) { 1034 return true; 1035 } 1036 break; 1037 default: 1038 /* other trigger types are not supported */ 1039 break; 1040 } 1041 } 1042 1043 return false; 1044 } 1045 1046 void riscv_trigger_realize(CPURISCVState *env) 1047 { 1048 int i; 1049 1050 for (i = 0; i < RV_MAX_TRIGGERS; i++) { 1051 env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1052 riscv_itrigger_timer_cb, env); 1053 } 1054 } 1055 1056 void riscv_trigger_reset_hold(CPURISCVState *env) 1057 { 1058 target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); 1059 int i; 1060 1061 /* init to type 2 triggers */ 1062 for (i = 0; i < RV_MAX_TRIGGERS; i++) { 1063 /* 1064 * type = TRIGGER_TYPE_AD_MATCH 1065 * dmode = 0 (both debug and M-mode can write tdata) 1066 * maskmax = 0 (unimplemented, always 0) 1067 * sizehi = 0 (match against any size, RV64 only) 1068 * hit = 0 (unimplemented, always 0) 1069 * select = 0 (always 0, perform match on address) 1070 * timing = 0 (always 0, trigger before instruction) 1071 * sizelo = 0 (match against any size) 1072 * action = 0 (always 0, raise a breakpoint exception) 1073 * chain = 0 (unimplemented, always 0) 1074 * match = 0 (always 0, when any compare value equals tdata2) 1075 */ 1076 env->tdata1[i] = tdata1; 1077 env->tdata2[i] = 0; 1078 env->tdata3[i] = 0; 1079 env->cpu_breakpoint[i] = NULL; 1080 env->cpu_watchpoint[i] = NULL; 1081 timer_del(env->itrigger_timer[i]); 1082 } 1083 1084 env->mcontext = 0; 1085 } 1086