1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table */ 27 static riscv_csr_operations csr_ops[]; 28 29 /* CSR function table constants */ 30 enum { 31 CSR_TABLE_SIZE = 0x1000 32 }; 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 static int fs(CPURISCVState *env, int csrno) 47 { 48 #if !defined(CONFIG_USER_ONLY) 49 if (!(env->mstatus & MSTATUS_FS)) { 50 return -1; 51 } 52 #endif 53 return 0; 54 } 55 56 static int ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 target_ulong ctr_en = env->priv == PRV_U ? env->scounteren : 60 env->priv == PRV_S ? env->mcounteren : -1U; 61 if (!(ctr_en & (1 << (csrno & 31)))) { 62 return -1; 63 } 64 #endif 65 return 0; 66 } 67 68 #if !defined(CONFIG_USER_ONLY) 69 static int any(CPURISCVState *env, int csrno) 70 { 71 return 0; 72 } 73 74 static int smode(CPURISCVState *env, int csrno) 75 { 76 return -!riscv_has_ext(env, RVS); 77 } 78 79 static int pmp(CPURISCVState *env, int csrno) 80 { 81 return -!riscv_feature(env, RISCV_FEATURE_PMP); 82 } 83 #endif 84 85 /* User Floating-Point CSRs */ 86 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 87 { 88 #if !defined(CONFIG_USER_ONLY) 89 if (!(env->mstatus & MSTATUS_FS)) { 90 return -1; 91 } 92 #endif 93 *val = riscv_cpu_get_fflags(env); 94 return 0; 95 } 96 97 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 98 { 99 #if !defined(CONFIG_USER_ONLY) 100 if (!(env->mstatus & MSTATUS_FS)) { 101 return -1; 102 } 103 env->mstatus |= MSTATUS_FS; 104 #endif 105 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 106 return 0; 107 } 108 109 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 110 { 111 #if !defined(CONFIG_USER_ONLY) 112 if (!(env->mstatus & MSTATUS_FS)) { 113 return -1; 114 } 115 #endif 116 *val = env->frm; 117 return 0; 118 } 119 120 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 121 { 122 #if !defined(CONFIG_USER_ONLY) 123 if (!(env->mstatus & MSTATUS_FS)) { 124 return -1; 125 } 126 env->mstatus |= MSTATUS_FS; 127 #endif 128 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 129 return 0; 130 } 131 132 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 133 { 134 #if !defined(CONFIG_USER_ONLY) 135 if (!(env->mstatus & MSTATUS_FS)) { 136 return -1; 137 } 138 #endif 139 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 140 | (env->frm << FSR_RD_SHIFT); 141 return 0; 142 } 143 144 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 145 { 146 #if !defined(CONFIG_USER_ONLY) 147 if (!(env->mstatus & MSTATUS_FS)) { 148 return -1; 149 } 150 env->mstatus |= MSTATUS_FS; 151 #endif 152 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 153 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 154 return 0; 155 } 156 157 /* User Timers and Counters */ 158 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 159 { 160 #if !defined(CONFIG_USER_ONLY) 161 if (use_icount) { 162 *val = cpu_get_icount(); 163 } else { 164 *val = cpu_get_host_ticks(); 165 } 166 #else 167 *val = cpu_get_host_ticks(); 168 #endif 169 return 0; 170 } 171 172 #if defined(TARGET_RISCV32) 173 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 174 { 175 #if !defined(CONFIG_USER_ONLY) 176 if (use_icount) { 177 *val = cpu_get_icount() >> 32; 178 } else { 179 *val = cpu_get_host_ticks() >> 32; 180 } 181 #else 182 *val = cpu_get_host_ticks() >> 32; 183 #endif 184 return 0; 185 } 186 #endif /* TARGET_RISCV32 */ 187 188 #if defined(CONFIG_USER_ONLY) 189 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 190 { 191 *val = cpu_get_host_ticks(); 192 return 0; 193 } 194 195 #if defined(TARGET_RISCV32) 196 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 197 { 198 *val = cpu_get_host_ticks() >> 32; 199 return 0; 200 } 201 #endif 202 203 #else /* CONFIG_USER_ONLY */ 204 205 /* Machine constants */ 206 207 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 208 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 209 210 static const target_ulong delegable_ints = S_MODE_INTERRUPTS; 211 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS; 212 static const target_ulong delegable_excps = 213 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 214 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 215 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 216 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 217 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 218 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 219 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 220 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 221 (1ULL << (RISCV_EXCP_U_ECALL)) | 222 (1ULL << (RISCV_EXCP_S_ECALL)) | 223 (1ULL << (RISCV_EXCP_H_ECALL)) | 224 (1ULL << (RISCV_EXCP_M_ECALL)) | 225 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 226 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 227 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)); 228 static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | 229 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 230 SSTATUS_SUM | SSTATUS_SD; 231 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 232 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 233 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 234 235 #if defined(TARGET_RISCV32) 236 static const char valid_vm_1_09[16] = { 237 [VM_1_09_MBARE] = 1, 238 [VM_1_09_SV32] = 1, 239 }; 240 static const char valid_vm_1_10[16] = { 241 [VM_1_10_MBARE] = 1, 242 [VM_1_10_SV32] = 1 243 }; 244 #elif defined(TARGET_RISCV64) 245 static const char valid_vm_1_09[16] = { 246 [VM_1_09_MBARE] = 1, 247 [VM_1_09_SV39] = 1, 248 [VM_1_09_SV48] = 1, 249 }; 250 static const char valid_vm_1_10[16] = { 251 [VM_1_10_MBARE] = 1, 252 [VM_1_10_SV39] = 1, 253 [VM_1_10_SV48] = 1, 254 [VM_1_10_SV57] = 1 255 }; 256 #endif /* CONFIG_USER_ONLY */ 257 258 /* Machine Information Registers */ 259 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 260 { 261 return *val = 0; 262 } 263 264 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 265 { 266 *val = env->mhartid; 267 return 0; 268 } 269 270 /* Machine Trap Setup */ 271 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 272 { 273 *val = env->mstatus; 274 return 0; 275 } 276 277 static int validate_vm(CPURISCVState *env, target_ulong vm) 278 { 279 return (env->priv_ver >= PRIV_VERSION_1_10_0) ? 280 valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; 281 } 282 283 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 284 { 285 target_ulong mstatus = env->mstatus; 286 target_ulong mask = 0; 287 target_ulong mpp = get_field(val, MSTATUS_MPP); 288 289 /* flush tlb on mstatus fields that affect VM */ 290 if (env->priv_ver <= PRIV_VERSION_1_09_1) { 291 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 292 MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { 293 tlb_flush(CPU(riscv_env_get_cpu(env))); 294 } 295 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 296 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 297 MSTATUS_MPP | MSTATUS_MXR | 298 (validate_vm(env, get_field(val, MSTATUS_VM)) ? 299 MSTATUS_VM : 0); 300 } 301 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 302 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 303 MSTATUS_MPRV | MSTATUS_SUM)) { 304 tlb_flush(CPU(riscv_env_get_cpu(env))); 305 } 306 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 307 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 308 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 309 MSTATUS_TW; 310 } 311 312 /* silenty discard mstatus.mpp writes for unsupported modes */ 313 if (mpp == PRV_H || 314 (!riscv_has_ext(env, RVS) && mpp == PRV_S) || 315 (!riscv_has_ext(env, RVU) && mpp == PRV_U)) { 316 mask &= ~MSTATUS_MPP; 317 } 318 319 mstatus = (mstatus & ~mask) | (val & mask); 320 321 int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 322 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 323 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 324 env->mstatus = mstatus; 325 326 return 0; 327 } 328 329 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 330 { 331 *val = env->misa; 332 return 0; 333 } 334 335 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 336 { 337 *val = env->medeleg; 338 return 0; 339 } 340 341 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 342 { 343 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 344 return 0; 345 } 346 347 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 348 { 349 *val = env->mideleg; 350 return 0; 351 } 352 353 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 354 { 355 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 356 return 0; 357 } 358 359 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 360 { 361 *val = env->mie; 362 return 0; 363 } 364 365 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 366 { 367 env->mie = (env->mie & ~all_ints) | (val & all_ints); 368 return 0; 369 } 370 371 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 372 { 373 *val = env->mtvec; 374 return 0; 375 } 376 377 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 378 { 379 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 380 if ((val & 3) == 0) { 381 env->mtvec = val >> 2 << 2; 382 } else { 383 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported"); 384 } 385 return 0; 386 } 387 388 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 389 { 390 if (env->priv_ver < PRIV_VERSION_1_10_0) { 391 return -1; 392 } 393 *val = env->mcounteren; 394 return 0; 395 } 396 397 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 398 { 399 if (env->priv_ver < PRIV_VERSION_1_10_0) { 400 return -1; 401 } 402 env->mcounteren = val; 403 return 0; 404 } 405 406 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) 407 { 408 if (env->priv_ver > PRIV_VERSION_1_09_1) { 409 return -1; 410 } 411 *val = env->mcounteren; 412 return 0; 413 } 414 415 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) 416 { 417 if (env->priv_ver > PRIV_VERSION_1_09_1) { 418 return -1; 419 } 420 env->mcounteren = val; 421 return 0; 422 } 423 424 static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) 425 { 426 if (env->priv_ver > PRIV_VERSION_1_09_1) { 427 return -1; 428 } 429 *val = env->scounteren; 430 return 0; 431 } 432 433 static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) 434 { 435 if (env->priv_ver > PRIV_VERSION_1_09_1) { 436 return -1; 437 } 438 env->scounteren = val; 439 return 0; 440 } 441 442 /* Machine Trap Handling */ 443 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 444 { 445 *val = env->mscratch; 446 return 0; 447 } 448 449 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 450 { 451 env->mscratch = val; 452 return 0; 453 } 454 455 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 456 { 457 *val = env->mepc; 458 return 0; 459 } 460 461 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 462 { 463 env->mepc = val; 464 return 0; 465 } 466 467 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 468 { 469 *val = env->mcause; 470 return 0; 471 } 472 473 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 474 { 475 env->mcause = val; 476 return 0; 477 } 478 479 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 480 { 481 *val = env->mbadaddr; 482 return 0; 483 } 484 485 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) 486 { 487 env->mbadaddr = val; 488 return 0; 489 } 490 491 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 492 target_ulong new_value, target_ulong write_mask) 493 { 494 RISCVCPU *cpu = riscv_env_get_cpu(env); 495 target_ulong mask = write_mask & delegable_ints; 496 uint32_t old_mip; 497 498 /* We can't allow the supervisor to control SEIP as this would allow the 499 * supervisor to clear a pending external interrupt which will result in 500 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be 501 * hardware controlled when a PLIC is attached. This should be an option 502 * for CPUs with software-delegated Supervisor External Interrupts. */ 503 mask &= ~MIP_SEIP; 504 505 if (mask) { 506 qemu_mutex_lock_iothread(); 507 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 508 qemu_mutex_unlock_iothread(); 509 } else { 510 old_mip = atomic_read(&env->mip); 511 } 512 513 if (ret_value) { 514 *ret_value = old_mip; 515 } 516 517 return 0; 518 } 519 520 /* Supervisor Trap Setup */ 521 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 522 { 523 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 524 sstatus_v1_10_mask : sstatus_v1_9_mask); 525 *val = env->mstatus & mask; 526 return 0; 527 } 528 529 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 530 { 531 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 532 sstatus_v1_10_mask : sstatus_v1_9_mask); 533 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 534 return write_mstatus(env, CSR_MSTATUS, newval); 535 } 536 537 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 538 { 539 *val = env->mie & env->mideleg; 540 return 0; 541 } 542 543 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 544 { 545 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg); 546 return write_mie(env, CSR_MIE, newval); 547 } 548 549 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 550 { 551 *val = env->stvec; 552 return 0; 553 } 554 555 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 556 { 557 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 558 if ((val & 3) == 0) { 559 env->stvec = val >> 2 << 2; 560 } else { 561 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported"); 562 } 563 return 0; 564 } 565 566 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 567 { 568 if (env->priv_ver < PRIV_VERSION_1_10_0) { 569 return -1; 570 } 571 *val = env->scounteren; 572 return 0; 573 } 574 575 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 576 { 577 if (env->priv_ver < PRIV_VERSION_1_10_0) { 578 return -1; 579 } 580 env->scounteren = val; 581 return 0; 582 } 583 584 /* Supervisor Trap Handling */ 585 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 586 { 587 *val = env->sscratch; 588 return 0; 589 } 590 591 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 592 { 593 env->sscratch = val; 594 return 0; 595 } 596 597 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 598 { 599 *val = env->sepc; 600 return 0; 601 } 602 603 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 604 { 605 env->sepc = val; 606 return 0; 607 } 608 609 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 610 { 611 *val = env->scause; 612 return 0; 613 } 614 615 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 616 { 617 env->scause = val; 618 return 0; 619 } 620 621 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 622 { 623 *val = env->sbadaddr; 624 return 0; 625 } 626 627 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 628 { 629 env->sbadaddr = val; 630 return 0; 631 } 632 633 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 634 target_ulong new_value, target_ulong write_mask) 635 { 636 return rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 637 write_mask & env->mideleg); 638 } 639 640 /* Supervisor Protection and Translation */ 641 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 642 { 643 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 644 *val = 0; 645 } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { 646 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 647 return -1; 648 } else { 649 *val = env->satp; 650 } 651 } else { 652 *val = env->sptbr; 653 } 654 return 0; 655 } 656 657 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 658 { 659 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 660 return 0; 661 } 662 if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { 663 tlb_flush(CPU(riscv_env_get_cpu(env))); 664 env->sptbr = val & (((target_ulong) 665 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); 666 } 667 if (env->priv_ver >= PRIV_VERSION_1_10_0 && 668 validate_vm(env, get_field(val, SATP_MODE)) && 669 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 670 { 671 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 672 return -1; 673 } else { 674 tlb_flush(CPU(riscv_env_get_cpu(env))); 675 env->satp = val; 676 } 677 } 678 return 0; 679 } 680 681 /* Physical Memory Protection */ 682 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 683 { 684 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 685 return 0; 686 } 687 688 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 689 { 690 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 691 return 0; 692 } 693 694 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 695 { 696 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 697 return 0; 698 } 699 700 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 701 { 702 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 703 return 0; 704 } 705 706 #endif 707 708 /* 709 * riscv_csrrw - read and/or update control and status register 710 * 711 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 712 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 713 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 714 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 715 */ 716 717 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 718 target_ulong new_value, target_ulong write_mask) 719 { 720 int ret; 721 target_ulong old_value; 722 723 /* check privileges and return -1 if check fails */ 724 #if !defined(CONFIG_USER_ONLY) 725 int csr_priv = get_field(csrno, 0x300); 726 int read_only = get_field(csrno, 0xC00) == 3; 727 if ((write_mask && read_only) || (env->priv < csr_priv)) { 728 return -1; 729 } 730 #endif 731 732 /* check predicate */ 733 if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { 734 return -1; 735 } 736 737 /* execute combined read/write operation if it exists */ 738 if (csr_ops[csrno].op) { 739 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 740 } 741 742 /* if no accessor exists then return failure */ 743 if (!csr_ops[csrno].read) { 744 return -1; 745 } 746 747 /* read old value */ 748 ret = csr_ops[csrno].read(env, csrno, &old_value); 749 if (ret < 0) { 750 return ret; 751 } 752 753 /* write value if writable and write mask set, otherwise drop writes */ 754 if (write_mask) { 755 new_value = (old_value & ~write_mask) | (new_value & write_mask); 756 if (csr_ops[csrno].write) { 757 ret = csr_ops[csrno].write(env, csrno, new_value); 758 if (ret < 0) { 759 return ret; 760 } 761 } 762 } 763 764 /* return old value */ 765 if (ret_value) { 766 *ret_value = old_value; 767 } 768 769 return 0; 770 } 771 772 /* Control and Status Register function table */ 773 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 774 /* User Floating-Point CSRs */ 775 [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, 776 [CSR_FRM] = { fs, read_frm, write_frm }, 777 [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, 778 779 /* User Timers and Counters */ 780 [CSR_CYCLE] = { ctr, read_instret }, 781 [CSR_INSTRET] = { ctr, read_instret }, 782 #if defined(TARGET_RISCV32) 783 [CSR_CYCLEH] = { ctr, read_instreth }, 784 [CSR_INSTRETH] = { ctr, read_instreth }, 785 #endif 786 787 /* User-level time CSRs are only available in linux-user 788 * In privileged mode, the monitor emulates these CSRs */ 789 #if defined(CONFIG_USER_ONLY) 790 [CSR_TIME] = { ctr, read_time }, 791 #if defined(TARGET_RISCV32) 792 [CSR_TIMEH] = { ctr, read_timeh }, 793 #endif 794 #endif 795 796 #if !defined(CONFIG_USER_ONLY) 797 /* Machine Timers and Counters */ 798 [CSR_MCYCLE] = { any, read_instret }, 799 [CSR_MINSTRET] = { any, read_instret }, 800 #if defined(TARGET_RISCV32) 801 [CSR_MCYCLEH] = { any, read_instreth }, 802 [CSR_MINSTRETH] = { any, read_instreth }, 803 #endif 804 805 /* Machine Information Registers */ 806 [CSR_MVENDORID] = { any, read_zero }, 807 [CSR_MARCHID] = { any, read_zero }, 808 [CSR_MIMPID] = { any, read_zero }, 809 [CSR_MHARTID] = { any, read_mhartid }, 810 811 /* Machine Trap Setup */ 812 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, 813 [CSR_MISA] = { any, read_misa }, 814 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, 815 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, 816 [CSR_MIE] = { any, read_mie, write_mie }, 817 [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, 818 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, 819 820 /* Legacy Counter Setup (priv v1.9.1) */ 821 [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, 822 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, 823 824 /* Machine Trap Handling */ 825 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, 826 [CSR_MEPC] = { any, read_mepc, write_mepc }, 827 [CSR_MCAUSE] = { any, read_mcause, write_mcause }, 828 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, 829 [CSR_MIP] = { any, NULL, NULL, rmw_mip }, 830 831 /* Supervisor Trap Setup */ 832 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, 833 [CSR_SIE] = { smode, read_sie, write_sie }, 834 [CSR_STVEC] = { smode, read_stvec, write_stvec }, 835 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, 836 837 /* Supervisor Trap Handling */ 838 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, 839 [CSR_SEPC] = { smode, read_sepc, write_sepc }, 840 [CSR_SCAUSE] = { smode, read_scause, write_scause }, 841 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, 842 [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, 843 844 /* Supervisor Protection and Translation */ 845 [CSR_SATP] = { smode, read_satp, write_satp }, 846 847 /* Physical Memory Protection */ 848 [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, 849 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, 850 851 /* Performance Counters */ 852 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, 853 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, 854 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, 855 #if defined(TARGET_RISCV32) 856 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, 857 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, 858 #endif 859 #endif /* !CONFIG_USER_ONLY */ 860 }; 861