1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "tcg/tcg-cpu.h" 25 #include "pmu.h" 26 #include "time_helper.h" 27 #include "exec/exec-all.h" 28 #include "exec/tb-flush.h" 29 #include "sysemu/cpu-timers.h" 30 #include "qemu/guest-random.h" 31 #include "qapi/error.h" 32 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 #if !defined(CONFIG_USER_ONLY) 47 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) 48 { 49 bool virt = env->virt_enabled; 50 51 if (env->priv == PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { 52 return RISCV_EXCP_NONE; 53 } 54 55 if (!(env->mstateen[index] & bit)) { 56 return RISCV_EXCP_ILLEGAL_INST; 57 } 58 59 if (virt) { 60 if (!(env->hstateen[index] & bit)) { 61 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 62 } 63 64 if (env->priv == PRV_U && !(env->sstateen[index] & bit)) { 65 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 66 } 67 } 68 69 if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { 70 if (!(env->sstateen[index] & bit)) { 71 return RISCV_EXCP_ILLEGAL_INST; 72 } 73 } 74 75 return RISCV_EXCP_NONE; 76 } 77 #endif 78 79 static RISCVException fs(CPURISCVState *env, int csrno) 80 { 81 #if !defined(CONFIG_USER_ONLY) 82 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 83 !riscv_cpu_cfg(env)->ext_zfinx) { 84 return RISCV_EXCP_ILLEGAL_INST; 85 } 86 87 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 88 return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); 89 } 90 #endif 91 return RISCV_EXCP_NONE; 92 } 93 94 static RISCVException vs(CPURISCVState *env, int csrno) 95 { 96 if (riscv_cpu_cfg(env)->ext_zve32f) { 97 #if !defined(CONFIG_USER_ONLY) 98 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 99 return RISCV_EXCP_ILLEGAL_INST; 100 } 101 #endif 102 return RISCV_EXCP_NONE; 103 } 104 return RISCV_EXCP_ILLEGAL_INST; 105 } 106 107 static RISCVException ctr(CPURISCVState *env, int csrno) 108 { 109 #if !defined(CONFIG_USER_ONLY) 110 RISCVCPU *cpu = env_archcpu(env); 111 int ctr_index; 112 target_ulong ctr_mask; 113 int base_csrno = CSR_CYCLE; 114 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; 115 116 if (rv32 && csrno >= CSR_CYCLEH) { 117 /* Offset for RV32 hpmcounternh counters */ 118 base_csrno += 0x80; 119 } 120 ctr_index = csrno - base_csrno; 121 ctr_mask = BIT(ctr_index); 122 123 if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || 124 (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) { 125 if (!riscv_cpu_cfg(env)->ext_zicntr) { 126 return RISCV_EXCP_ILLEGAL_INST; 127 } 128 129 goto skip_ext_pmu_check; 130 } 131 132 if (!(cpu->pmu_avail_ctrs & ctr_mask)) { 133 /* No counter is enabled in PMU or the counter is out of range */ 134 return RISCV_EXCP_ILLEGAL_INST; 135 } 136 137 skip_ext_pmu_check: 138 139 if (env->debugger) { 140 return RISCV_EXCP_NONE; 141 } 142 143 if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) { 144 return RISCV_EXCP_ILLEGAL_INST; 145 } 146 147 if (env->virt_enabled) { 148 if (!get_field(env->hcounteren, ctr_mask) || 149 (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) { 150 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 151 } 152 } 153 154 if (riscv_has_ext(env, RVS) && env->priv == PRV_U && 155 !get_field(env->scounteren, ctr_mask)) { 156 return RISCV_EXCP_ILLEGAL_INST; 157 } 158 159 #endif 160 return RISCV_EXCP_NONE; 161 } 162 163 static RISCVException ctr32(CPURISCVState *env, int csrno) 164 { 165 if (riscv_cpu_mxl(env) != MXL_RV32) { 166 return RISCV_EXCP_ILLEGAL_INST; 167 } 168 169 return ctr(env, csrno); 170 } 171 172 static RISCVException zcmt(CPURISCVState *env, int csrno) 173 { 174 if (!riscv_cpu_cfg(env)->ext_zcmt) { 175 return RISCV_EXCP_ILLEGAL_INST; 176 } 177 178 #if !defined(CONFIG_USER_ONLY) 179 RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); 180 if (ret != RISCV_EXCP_NONE) { 181 return ret; 182 } 183 #endif 184 185 return RISCV_EXCP_NONE; 186 } 187 188 #if !defined(CONFIG_USER_ONLY) 189 static RISCVException mctr(CPURISCVState *env, int csrno) 190 { 191 RISCVCPU *cpu = env_archcpu(env); 192 uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs; 193 int ctr_index; 194 int base_csrno = CSR_MHPMCOUNTER3; 195 196 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { 197 /* Offset for RV32 mhpmcounternh counters */ 198 csrno -= 0x80; 199 } 200 201 g_assert(csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31); 202 203 ctr_index = csrno - base_csrno; 204 if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) { 205 /* The PMU is not enabled or counter is out of range */ 206 return RISCV_EXCP_ILLEGAL_INST; 207 } 208 209 return RISCV_EXCP_NONE; 210 } 211 212 static RISCVException mctr32(CPURISCVState *env, int csrno) 213 { 214 if (riscv_cpu_mxl(env) != MXL_RV32) { 215 return RISCV_EXCP_ILLEGAL_INST; 216 } 217 218 return mctr(env, csrno); 219 } 220 221 static RISCVException sscofpmf(CPURISCVState *env, int csrno) 222 { 223 if (!riscv_cpu_cfg(env)->ext_sscofpmf) { 224 return RISCV_EXCP_ILLEGAL_INST; 225 } 226 227 return RISCV_EXCP_NONE; 228 } 229 230 static RISCVException any(CPURISCVState *env, int csrno) 231 { 232 return RISCV_EXCP_NONE; 233 } 234 235 static RISCVException any32(CPURISCVState *env, int csrno) 236 { 237 if (riscv_cpu_mxl(env) != MXL_RV32) { 238 return RISCV_EXCP_ILLEGAL_INST; 239 } 240 241 return any(env, csrno); 242 243 } 244 245 static RISCVException aia_any(CPURISCVState *env, int csrno) 246 { 247 if (!riscv_cpu_cfg(env)->ext_smaia) { 248 return RISCV_EXCP_ILLEGAL_INST; 249 } 250 251 return any(env, csrno); 252 } 253 254 static RISCVException aia_any32(CPURISCVState *env, int csrno) 255 { 256 if (!riscv_cpu_cfg(env)->ext_smaia) { 257 return RISCV_EXCP_ILLEGAL_INST; 258 } 259 260 return any32(env, csrno); 261 } 262 263 static RISCVException smode(CPURISCVState *env, int csrno) 264 { 265 if (riscv_has_ext(env, RVS)) { 266 return RISCV_EXCP_NONE; 267 } 268 269 return RISCV_EXCP_ILLEGAL_INST; 270 } 271 272 static RISCVException smode32(CPURISCVState *env, int csrno) 273 { 274 if (riscv_cpu_mxl(env) != MXL_RV32) { 275 return RISCV_EXCP_ILLEGAL_INST; 276 } 277 278 return smode(env, csrno); 279 } 280 281 static RISCVException aia_smode(CPURISCVState *env, int csrno) 282 { 283 if (!riscv_cpu_cfg(env)->ext_ssaia) { 284 return RISCV_EXCP_ILLEGAL_INST; 285 } 286 287 return smode(env, csrno); 288 } 289 290 static RISCVException aia_smode32(CPURISCVState *env, int csrno) 291 { 292 if (!riscv_cpu_cfg(env)->ext_ssaia) { 293 return RISCV_EXCP_ILLEGAL_INST; 294 } 295 296 return smode32(env, csrno); 297 } 298 299 static RISCVException hmode(CPURISCVState *env, int csrno) 300 { 301 if (riscv_has_ext(env, RVH)) { 302 return RISCV_EXCP_NONE; 303 } 304 305 return RISCV_EXCP_ILLEGAL_INST; 306 } 307 308 static RISCVException hmode32(CPURISCVState *env, int csrno) 309 { 310 if (riscv_cpu_mxl(env) != MXL_RV32) { 311 return RISCV_EXCP_ILLEGAL_INST; 312 } 313 314 return hmode(env, csrno); 315 316 } 317 318 static RISCVException umode(CPURISCVState *env, int csrno) 319 { 320 if (riscv_has_ext(env, RVU)) { 321 return RISCV_EXCP_NONE; 322 } 323 324 return RISCV_EXCP_ILLEGAL_INST; 325 } 326 327 static RISCVException umode32(CPURISCVState *env, int csrno) 328 { 329 if (riscv_cpu_mxl(env) != MXL_RV32) { 330 return RISCV_EXCP_ILLEGAL_INST; 331 } 332 333 return umode(env, csrno); 334 } 335 336 static RISCVException mstateen(CPURISCVState *env, int csrno) 337 { 338 if (!riscv_cpu_cfg(env)->ext_smstateen) { 339 return RISCV_EXCP_ILLEGAL_INST; 340 } 341 342 return any(env, csrno); 343 } 344 345 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) 346 { 347 if (!riscv_cpu_cfg(env)->ext_smstateen) { 348 return RISCV_EXCP_ILLEGAL_INST; 349 } 350 351 RISCVException ret = hmode(env, csrno); 352 if (ret != RISCV_EXCP_NONE) { 353 return ret; 354 } 355 356 if (env->debugger) { 357 return RISCV_EXCP_NONE; 358 } 359 360 if (env->priv < PRV_M) { 361 if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { 362 return RISCV_EXCP_ILLEGAL_INST; 363 } 364 } 365 366 return RISCV_EXCP_NONE; 367 } 368 369 static RISCVException hstateen(CPURISCVState *env, int csrno) 370 { 371 return hstateen_pred(env, csrno, CSR_HSTATEEN0); 372 } 373 374 static RISCVException hstateenh(CPURISCVState *env, int csrno) 375 { 376 return hstateen_pred(env, csrno, CSR_HSTATEEN0H); 377 } 378 379 static RISCVException sstateen(CPURISCVState *env, int csrno) 380 { 381 bool virt = env->virt_enabled; 382 int index = csrno - CSR_SSTATEEN0; 383 384 if (!riscv_cpu_cfg(env)->ext_smstateen) { 385 return RISCV_EXCP_ILLEGAL_INST; 386 } 387 388 RISCVException ret = smode(env, csrno); 389 if (ret != RISCV_EXCP_NONE) { 390 return ret; 391 } 392 393 if (env->debugger) { 394 return RISCV_EXCP_NONE; 395 } 396 397 if (env->priv < PRV_M) { 398 if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { 399 return RISCV_EXCP_ILLEGAL_INST; 400 } 401 402 if (virt) { 403 if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { 404 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 405 } 406 } 407 } 408 409 return RISCV_EXCP_NONE; 410 } 411 412 static RISCVException sstc(CPURISCVState *env, int csrno) 413 { 414 bool hmode_check = false; 415 416 if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { 417 return RISCV_EXCP_ILLEGAL_INST; 418 } 419 420 if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) { 421 hmode_check = true; 422 } 423 424 RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno); 425 if (ret != RISCV_EXCP_NONE) { 426 return ret; 427 } 428 429 if (env->debugger) { 430 return RISCV_EXCP_NONE; 431 } 432 433 if (env->priv == PRV_M) { 434 return RISCV_EXCP_NONE; 435 } 436 437 /* 438 * No need of separate function for rv32 as menvcfg stores both menvcfg 439 * menvcfgh for RV32. 440 */ 441 if (!(get_field(env->mcounteren, COUNTEREN_TM) && 442 get_field(env->menvcfg, MENVCFG_STCE))) { 443 return RISCV_EXCP_ILLEGAL_INST; 444 } 445 446 if (env->virt_enabled) { 447 if (!(get_field(env->hcounteren, COUNTEREN_TM) && 448 get_field(env->henvcfg, HENVCFG_STCE))) { 449 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 450 } 451 } 452 453 return RISCV_EXCP_NONE; 454 } 455 456 static RISCVException sstc_32(CPURISCVState *env, int csrno) 457 { 458 if (riscv_cpu_mxl(env) != MXL_RV32) { 459 return RISCV_EXCP_ILLEGAL_INST; 460 } 461 462 return sstc(env, csrno); 463 } 464 465 static RISCVException satp(CPURISCVState *env, int csrno) 466 { 467 if (env->priv == PRV_S && !env->virt_enabled && 468 get_field(env->mstatus, MSTATUS_TVM)) { 469 return RISCV_EXCP_ILLEGAL_INST; 470 } 471 if (env->priv == PRV_S && env->virt_enabled && 472 get_field(env->hstatus, HSTATUS_VTVM)) { 473 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 474 } 475 476 return smode(env, csrno); 477 } 478 479 static RISCVException hgatp(CPURISCVState *env, int csrno) 480 { 481 if (env->priv == PRV_S && !env->virt_enabled && 482 get_field(env->mstatus, MSTATUS_TVM)) { 483 return RISCV_EXCP_ILLEGAL_INST; 484 } 485 486 return hmode(env, csrno); 487 } 488 489 /* Checks if PointerMasking registers could be accessed */ 490 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 491 { 492 /* Check if j-ext is present */ 493 if (riscv_has_ext(env, RVJ)) { 494 return RISCV_EXCP_NONE; 495 } 496 return RISCV_EXCP_ILLEGAL_INST; 497 } 498 499 static RISCVException aia_hmode(CPURISCVState *env, int csrno) 500 { 501 if (!riscv_cpu_cfg(env)->ext_ssaia) { 502 return RISCV_EXCP_ILLEGAL_INST; 503 } 504 505 return hmode(env, csrno); 506 } 507 508 static RISCVException aia_hmode32(CPURISCVState *env, int csrno) 509 { 510 if (!riscv_cpu_cfg(env)->ext_ssaia) { 511 return RISCV_EXCP_ILLEGAL_INST; 512 } 513 514 return hmode32(env, csrno); 515 } 516 517 static RISCVException pmp(CPURISCVState *env, int csrno) 518 { 519 if (riscv_cpu_cfg(env)->pmp) { 520 if (csrno <= CSR_PMPCFG3) { 521 uint32_t reg_index = csrno - CSR_PMPCFG0; 522 523 /* TODO: RV128 restriction check */ 524 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 525 return RISCV_EXCP_ILLEGAL_INST; 526 } 527 } 528 529 return RISCV_EXCP_NONE; 530 } 531 532 return RISCV_EXCP_ILLEGAL_INST; 533 } 534 535 static RISCVException have_mseccfg(CPURISCVState *env, int csrno) 536 { 537 if (riscv_cpu_cfg(env)->ext_smepmp) { 538 return RISCV_EXCP_NONE; 539 } 540 if (riscv_cpu_cfg(env)->ext_zkr) { 541 return RISCV_EXCP_NONE; 542 } 543 544 return RISCV_EXCP_ILLEGAL_INST; 545 } 546 547 static RISCVException debug(CPURISCVState *env, int csrno) 548 { 549 if (riscv_cpu_cfg(env)->debug) { 550 return RISCV_EXCP_NONE; 551 } 552 553 return RISCV_EXCP_ILLEGAL_INST; 554 } 555 #endif 556 557 static RISCVException seed(CPURISCVState *env, int csrno) 558 { 559 if (!riscv_cpu_cfg(env)->ext_zkr) { 560 return RISCV_EXCP_ILLEGAL_INST; 561 } 562 563 #if !defined(CONFIG_USER_ONLY) 564 if (env->debugger) { 565 return RISCV_EXCP_NONE; 566 } 567 568 /* 569 * With a CSR read-write instruction: 570 * 1) The seed CSR is always available in machine mode as normal. 571 * 2) Attempted access to seed from virtual modes VS and VU always raises 572 * an exception(virtual instruction exception only if mseccfg.sseed=1). 573 * 3) Without the corresponding access control bit set to 1, any attempted 574 * access to seed from U, S or HS modes will raise an illegal instruction 575 * exception. 576 */ 577 if (env->priv == PRV_M) { 578 return RISCV_EXCP_NONE; 579 } else if (env->virt_enabled) { 580 if (env->mseccfg & MSECCFG_SSEED) { 581 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 582 } else { 583 return RISCV_EXCP_ILLEGAL_INST; 584 } 585 } else { 586 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { 587 return RISCV_EXCP_NONE; 588 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { 589 return RISCV_EXCP_NONE; 590 } else { 591 return RISCV_EXCP_ILLEGAL_INST; 592 } 593 } 594 #else 595 return RISCV_EXCP_NONE; 596 #endif 597 } 598 599 /* User Floating-Point CSRs */ 600 static RISCVException read_fflags(CPURISCVState *env, int csrno, 601 target_ulong *val) 602 { 603 *val = riscv_cpu_get_fflags(env); 604 return RISCV_EXCP_NONE; 605 } 606 607 static RISCVException write_fflags(CPURISCVState *env, int csrno, 608 target_ulong val) 609 { 610 #if !defined(CONFIG_USER_ONLY) 611 if (riscv_has_ext(env, RVF)) { 612 env->mstatus |= MSTATUS_FS; 613 } 614 #endif 615 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 616 return RISCV_EXCP_NONE; 617 } 618 619 static RISCVException read_frm(CPURISCVState *env, int csrno, 620 target_ulong *val) 621 { 622 *val = env->frm; 623 return RISCV_EXCP_NONE; 624 } 625 626 static RISCVException write_frm(CPURISCVState *env, int csrno, 627 target_ulong val) 628 { 629 #if !defined(CONFIG_USER_ONLY) 630 if (riscv_has_ext(env, RVF)) { 631 env->mstatus |= MSTATUS_FS; 632 } 633 #endif 634 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 635 return RISCV_EXCP_NONE; 636 } 637 638 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 639 target_ulong *val) 640 { 641 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 642 | (env->frm << FSR_RD_SHIFT); 643 return RISCV_EXCP_NONE; 644 } 645 646 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 647 target_ulong val) 648 { 649 #if !defined(CONFIG_USER_ONLY) 650 if (riscv_has_ext(env, RVF)) { 651 env->mstatus |= MSTATUS_FS; 652 } 653 #endif 654 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 655 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 656 return RISCV_EXCP_NONE; 657 } 658 659 static RISCVException read_vtype(CPURISCVState *env, int csrno, 660 target_ulong *val) 661 { 662 uint64_t vill; 663 switch (env->xl) { 664 case MXL_RV32: 665 vill = (uint32_t)env->vill << 31; 666 break; 667 case MXL_RV64: 668 vill = (uint64_t)env->vill << 63; 669 break; 670 default: 671 g_assert_not_reached(); 672 } 673 *val = (target_ulong)vill | env->vtype; 674 return RISCV_EXCP_NONE; 675 } 676 677 static RISCVException read_vl(CPURISCVState *env, int csrno, 678 target_ulong *val) 679 { 680 *val = env->vl; 681 return RISCV_EXCP_NONE; 682 } 683 684 static RISCVException read_vlenb(CPURISCVState *env, int csrno, 685 target_ulong *val) 686 { 687 *val = riscv_cpu_cfg(env)->vlenb; 688 return RISCV_EXCP_NONE; 689 } 690 691 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 692 target_ulong *val) 693 { 694 *val = env->vxrm; 695 return RISCV_EXCP_NONE; 696 } 697 698 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 699 target_ulong val) 700 { 701 #if !defined(CONFIG_USER_ONLY) 702 env->mstatus |= MSTATUS_VS; 703 #endif 704 env->vxrm = val; 705 return RISCV_EXCP_NONE; 706 } 707 708 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 709 target_ulong *val) 710 { 711 *val = env->vxsat; 712 return RISCV_EXCP_NONE; 713 } 714 715 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 716 target_ulong val) 717 { 718 #if !defined(CONFIG_USER_ONLY) 719 env->mstatus |= MSTATUS_VS; 720 #endif 721 env->vxsat = val; 722 return RISCV_EXCP_NONE; 723 } 724 725 static RISCVException read_vstart(CPURISCVState *env, int csrno, 726 target_ulong *val) 727 { 728 *val = env->vstart; 729 return RISCV_EXCP_NONE; 730 } 731 732 static RISCVException write_vstart(CPURISCVState *env, int csrno, 733 target_ulong val) 734 { 735 #if !defined(CONFIG_USER_ONLY) 736 env->mstatus |= MSTATUS_VS; 737 #endif 738 /* 739 * The vstart CSR is defined to have only enough writable bits 740 * to hold the largest element index, i.e. lg2(VLEN) bits. 741 */ 742 env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3)); 743 return RISCV_EXCP_NONE; 744 } 745 746 static RISCVException read_vcsr(CPURISCVState *env, int csrno, 747 target_ulong *val) 748 { 749 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 750 return RISCV_EXCP_NONE; 751 } 752 753 static RISCVException write_vcsr(CPURISCVState *env, int csrno, 754 target_ulong val) 755 { 756 #if !defined(CONFIG_USER_ONLY) 757 env->mstatus |= MSTATUS_VS; 758 #endif 759 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 760 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 761 return RISCV_EXCP_NONE; 762 } 763 764 /* User Timers and Counters */ 765 static target_ulong get_ticks(bool shift) 766 { 767 int64_t val; 768 target_ulong result; 769 770 #if !defined(CONFIG_USER_ONLY) 771 if (icount_enabled()) { 772 val = icount_get(); 773 } else { 774 val = cpu_get_host_ticks(); 775 } 776 #else 777 val = cpu_get_host_ticks(); 778 #endif 779 780 if (shift) { 781 result = val >> 32; 782 } else { 783 result = val; 784 } 785 786 return result; 787 } 788 789 #if defined(CONFIG_USER_ONLY) 790 static RISCVException read_time(CPURISCVState *env, int csrno, 791 target_ulong *val) 792 { 793 *val = cpu_get_host_ticks(); 794 return RISCV_EXCP_NONE; 795 } 796 797 static RISCVException read_timeh(CPURISCVState *env, int csrno, 798 target_ulong *val) 799 { 800 *val = cpu_get_host_ticks() >> 32; 801 return RISCV_EXCP_NONE; 802 } 803 804 static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, 805 target_ulong *val) 806 { 807 *val = get_ticks(false); 808 return RISCV_EXCP_NONE; 809 } 810 811 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, 812 target_ulong *val) 813 { 814 *val = get_ticks(true); 815 return RISCV_EXCP_NONE; 816 } 817 818 #else /* CONFIG_USER_ONLY */ 819 820 static RISCVException read_mhpmevent(CPURISCVState *env, int csrno, 821 target_ulong *val) 822 { 823 int evt_index = csrno - CSR_MCOUNTINHIBIT; 824 825 *val = env->mhpmevent_val[evt_index]; 826 827 return RISCV_EXCP_NONE; 828 } 829 830 static RISCVException write_mhpmevent(CPURISCVState *env, int csrno, 831 target_ulong val) 832 { 833 int evt_index = csrno - CSR_MCOUNTINHIBIT; 834 uint64_t mhpmevt_val = val; 835 836 env->mhpmevent_val[evt_index] = val; 837 838 if (riscv_cpu_mxl(env) == MXL_RV32) { 839 mhpmevt_val = mhpmevt_val | 840 ((uint64_t)env->mhpmeventh_val[evt_index] << 32); 841 } 842 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); 843 844 return RISCV_EXCP_NONE; 845 } 846 847 static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno, 848 target_ulong *val) 849 { 850 int evt_index = csrno - CSR_MHPMEVENT3H + 3; 851 852 *val = env->mhpmeventh_val[evt_index]; 853 854 return RISCV_EXCP_NONE; 855 } 856 857 static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno, 858 target_ulong val) 859 { 860 int evt_index = csrno - CSR_MHPMEVENT3H + 3; 861 uint64_t mhpmevth_val = val; 862 uint64_t mhpmevt_val = env->mhpmevent_val[evt_index]; 863 864 mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32); 865 env->mhpmeventh_val[evt_index] = val; 866 867 riscv_pmu_update_event_map(env, mhpmevt_val, evt_index); 868 869 return RISCV_EXCP_NONE; 870 } 871 872 static RISCVException write_mhpmcounter(CPURISCVState *env, int csrno, 873 target_ulong val) 874 { 875 int ctr_idx = csrno - CSR_MCYCLE; 876 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 877 uint64_t mhpmctr_val = val; 878 879 counter->mhpmcounter_val = val; 880 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 881 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 882 counter->mhpmcounter_prev = get_ticks(false); 883 if (ctr_idx > 2) { 884 if (riscv_cpu_mxl(env) == MXL_RV32) { 885 mhpmctr_val = mhpmctr_val | 886 ((uint64_t)counter->mhpmcounterh_val << 32); 887 } 888 riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); 889 } 890 } else { 891 /* Other counters can keep incrementing from the given value */ 892 counter->mhpmcounter_prev = val; 893 } 894 895 return RISCV_EXCP_NONE; 896 } 897 898 static RISCVException write_mhpmcounterh(CPURISCVState *env, int csrno, 899 target_ulong val) 900 { 901 int ctr_idx = csrno - CSR_MCYCLEH; 902 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 903 uint64_t mhpmctr_val = counter->mhpmcounter_val; 904 uint64_t mhpmctrh_val = val; 905 906 counter->mhpmcounterh_val = val; 907 mhpmctr_val = mhpmctr_val | (mhpmctrh_val << 32); 908 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 909 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 910 counter->mhpmcounterh_prev = get_ticks(true); 911 if (ctr_idx > 2) { 912 riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); 913 } 914 } else { 915 counter->mhpmcounterh_prev = val; 916 } 917 918 return RISCV_EXCP_NONE; 919 } 920 921 static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val, 922 bool upper_half, uint32_t ctr_idx) 923 { 924 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; 925 target_ulong ctr_prev = upper_half ? counter->mhpmcounterh_prev : 926 counter->mhpmcounter_prev; 927 target_ulong ctr_val = upper_half ? counter->mhpmcounterh_val : 928 counter->mhpmcounter_val; 929 930 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { 931 /* 932 * Counter should not increment if inhibit bit is set. We can't really 933 * stop the icount counting. Just return the counter value written by 934 * the supervisor to indicate that counter was not incremented. 935 */ 936 if (!counter->started) { 937 *val = ctr_val; 938 return RISCV_EXCP_NONE; 939 } else { 940 /* Mark that the counter has been stopped */ 941 counter->started = false; 942 } 943 } 944 945 /* 946 * The kernel computes the perf delta by subtracting the current value from 947 * the value it initialized previously (ctr_val). 948 */ 949 if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || 950 riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { 951 *val = get_ticks(upper_half) - ctr_prev + ctr_val; 952 } else { 953 *val = ctr_val; 954 } 955 956 return RISCV_EXCP_NONE; 957 } 958 959 static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, 960 target_ulong *val) 961 { 962 uint16_t ctr_index; 963 964 if (csrno >= CSR_MCYCLE && csrno <= CSR_MHPMCOUNTER31) { 965 ctr_index = csrno - CSR_MCYCLE; 966 } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) { 967 ctr_index = csrno - CSR_CYCLE; 968 } else { 969 return RISCV_EXCP_ILLEGAL_INST; 970 } 971 972 return riscv_pmu_read_ctr(env, val, false, ctr_index); 973 } 974 975 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, 976 target_ulong *val) 977 { 978 uint16_t ctr_index; 979 980 if (csrno >= CSR_MCYCLEH && csrno <= CSR_MHPMCOUNTER31H) { 981 ctr_index = csrno - CSR_MCYCLEH; 982 } else if (csrno >= CSR_CYCLEH && csrno <= CSR_HPMCOUNTER31H) { 983 ctr_index = csrno - CSR_CYCLEH; 984 } else { 985 return RISCV_EXCP_ILLEGAL_INST; 986 } 987 988 return riscv_pmu_read_ctr(env, val, true, ctr_index); 989 } 990 991 static RISCVException read_scountovf(CPURISCVState *env, int csrno, 992 target_ulong *val) 993 { 994 int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT; 995 int i; 996 *val = 0; 997 target_ulong *mhpm_evt_val; 998 uint64_t of_bit_mask; 999 1000 if (riscv_cpu_mxl(env) == MXL_RV32) { 1001 mhpm_evt_val = env->mhpmeventh_val; 1002 of_bit_mask = MHPMEVENTH_BIT_OF; 1003 } else { 1004 mhpm_evt_val = env->mhpmevent_val; 1005 of_bit_mask = MHPMEVENT_BIT_OF; 1006 } 1007 1008 for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) { 1009 if ((get_field(env->mcounteren, BIT(i))) && 1010 (mhpm_evt_val[i] & of_bit_mask)) { 1011 *val |= BIT(i); 1012 } 1013 } 1014 1015 return RISCV_EXCP_NONE; 1016 } 1017 1018 static RISCVException read_time(CPURISCVState *env, int csrno, 1019 target_ulong *val) 1020 { 1021 uint64_t delta = env->virt_enabled ? env->htimedelta : 0; 1022 1023 if (!env->rdtime_fn) { 1024 return RISCV_EXCP_ILLEGAL_INST; 1025 } 1026 1027 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 1028 return RISCV_EXCP_NONE; 1029 } 1030 1031 static RISCVException read_timeh(CPURISCVState *env, int csrno, 1032 target_ulong *val) 1033 { 1034 uint64_t delta = env->virt_enabled ? env->htimedelta : 0; 1035 1036 if (!env->rdtime_fn) { 1037 return RISCV_EXCP_ILLEGAL_INST; 1038 } 1039 1040 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 1041 return RISCV_EXCP_NONE; 1042 } 1043 1044 static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, 1045 target_ulong *val) 1046 { 1047 *val = env->vstimecmp; 1048 1049 return RISCV_EXCP_NONE; 1050 } 1051 1052 static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, 1053 target_ulong *val) 1054 { 1055 *val = env->vstimecmp >> 32; 1056 1057 return RISCV_EXCP_NONE; 1058 } 1059 1060 static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, 1061 target_ulong val) 1062 { 1063 if (riscv_cpu_mxl(env) == MXL_RV32) { 1064 env->vstimecmp = deposit64(env->vstimecmp, 0, 32, (uint64_t)val); 1065 } else { 1066 env->vstimecmp = val; 1067 } 1068 1069 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 1070 env->htimedelta, MIP_VSTIP); 1071 1072 return RISCV_EXCP_NONE; 1073 } 1074 1075 static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, 1076 target_ulong val) 1077 { 1078 env->vstimecmp = deposit64(env->vstimecmp, 32, 32, (uint64_t)val); 1079 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 1080 env->htimedelta, MIP_VSTIP); 1081 1082 return RISCV_EXCP_NONE; 1083 } 1084 1085 static RISCVException read_stimecmp(CPURISCVState *env, int csrno, 1086 target_ulong *val) 1087 { 1088 if (env->virt_enabled) { 1089 *val = env->vstimecmp; 1090 } else { 1091 *val = env->stimecmp; 1092 } 1093 1094 return RISCV_EXCP_NONE; 1095 } 1096 1097 static RISCVException read_stimecmph(CPURISCVState *env, int csrno, 1098 target_ulong *val) 1099 { 1100 if (env->virt_enabled) { 1101 *val = env->vstimecmp >> 32; 1102 } else { 1103 *val = env->stimecmp >> 32; 1104 } 1105 1106 return RISCV_EXCP_NONE; 1107 } 1108 1109 static RISCVException write_stimecmp(CPURISCVState *env, int csrno, 1110 target_ulong val) 1111 { 1112 if (env->virt_enabled) { 1113 if (env->hvictl & HVICTL_VTI) { 1114 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1115 } 1116 return write_vstimecmp(env, csrno, val); 1117 } 1118 1119 if (riscv_cpu_mxl(env) == MXL_RV32) { 1120 env->stimecmp = deposit64(env->stimecmp, 0, 32, (uint64_t)val); 1121 } else { 1122 env->stimecmp = val; 1123 } 1124 1125 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); 1126 1127 return RISCV_EXCP_NONE; 1128 } 1129 1130 static RISCVException write_stimecmph(CPURISCVState *env, int csrno, 1131 target_ulong val) 1132 { 1133 if (env->virt_enabled) { 1134 if (env->hvictl & HVICTL_VTI) { 1135 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1136 } 1137 return write_vstimecmph(env, csrno, val); 1138 } 1139 1140 env->stimecmp = deposit64(env->stimecmp, 32, 32, (uint64_t)val); 1141 riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP); 1142 1143 return RISCV_EXCP_NONE; 1144 } 1145 1146 #define VSTOPI_NUM_SRCS 5 1147 1148 #define LOCAL_INTERRUPTS (~0x1FFF) 1149 1150 static const uint64_t delegable_ints = 1151 S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; 1152 static const uint64_t vs_delegable_ints = 1153 (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; 1154 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 1155 HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; 1156 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 1157 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 1158 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 1159 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 1160 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 1161 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 1162 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 1163 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 1164 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 1165 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 1166 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 1167 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 1168 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 1169 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 1170 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 1171 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 1172 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 1173 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 1174 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 1175 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 1176 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 1177 (1ULL << (RISCV_EXCP_VS_ECALL)) | 1178 (1ULL << (RISCV_EXCP_M_ECALL)) | 1179 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 1180 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 1181 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 1182 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 1183 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 1184 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 1185 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 1186 1187 /* 1188 * Spec allows for bits 13:63 to be either read-only or writable. 1189 * So far we have interrupt LCOFIP in that region which is writable. 1190 * 1191 * Also, spec allows to inject virtual interrupts in this region even 1192 * without any hardware interrupts for that interrupt number. 1193 * 1194 * For now interrupt in 13:63 region are all kept writable. 13 being 1195 * LCOFIP and 14:63 being virtual only. Change this in future if we 1196 * introduce more interrupts that are not writable. 1197 */ 1198 1199 /* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. */ 1200 static const target_ulong mvip_writable_mask = MIP_SSIP | MIP_STIP | MIP_SEIP | 1201 LOCAL_INTERRUPTS; 1202 static const target_ulong mvien_writable_mask = MIP_SSIP | MIP_SEIP | 1203 LOCAL_INTERRUPTS; 1204 1205 static const target_ulong sip_writable_mask = SIP_SSIP | LOCAL_INTERRUPTS; 1206 static const target_ulong hip_writable_mask = MIP_VSSIP; 1207 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | 1208 MIP_VSEIP | LOCAL_INTERRUPTS; 1209 static const target_ulong hvien_writable_mask = LOCAL_INTERRUPTS; 1210 1211 static const target_ulong vsip_writable_mask = MIP_VSSIP | LOCAL_INTERRUPTS; 1212 1213 const bool valid_vm_1_10_32[16] = { 1214 [VM_1_10_MBARE] = true, 1215 [VM_1_10_SV32] = true 1216 }; 1217 1218 const bool valid_vm_1_10_64[16] = { 1219 [VM_1_10_MBARE] = true, 1220 [VM_1_10_SV39] = true, 1221 [VM_1_10_SV48] = true, 1222 [VM_1_10_SV57] = true 1223 }; 1224 1225 /* Machine Information Registers */ 1226 static RISCVException read_zero(CPURISCVState *env, int csrno, 1227 target_ulong *val) 1228 { 1229 *val = 0; 1230 return RISCV_EXCP_NONE; 1231 } 1232 1233 static RISCVException write_ignore(CPURISCVState *env, int csrno, 1234 target_ulong val) 1235 { 1236 return RISCV_EXCP_NONE; 1237 } 1238 1239 static RISCVException read_mvendorid(CPURISCVState *env, int csrno, 1240 target_ulong *val) 1241 { 1242 *val = riscv_cpu_cfg(env)->mvendorid; 1243 return RISCV_EXCP_NONE; 1244 } 1245 1246 static RISCVException read_marchid(CPURISCVState *env, int csrno, 1247 target_ulong *val) 1248 { 1249 *val = riscv_cpu_cfg(env)->marchid; 1250 return RISCV_EXCP_NONE; 1251 } 1252 1253 static RISCVException read_mimpid(CPURISCVState *env, int csrno, 1254 target_ulong *val) 1255 { 1256 *val = riscv_cpu_cfg(env)->mimpid; 1257 return RISCV_EXCP_NONE; 1258 } 1259 1260 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 1261 target_ulong *val) 1262 { 1263 *val = env->mhartid; 1264 return RISCV_EXCP_NONE; 1265 } 1266 1267 /* Machine Trap Setup */ 1268 1269 /* We do not store SD explicitly, only compute it on demand. */ 1270 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 1271 { 1272 if ((status & MSTATUS_FS) == MSTATUS_FS || 1273 (status & MSTATUS_VS) == MSTATUS_VS || 1274 (status & MSTATUS_XS) == MSTATUS_XS) { 1275 switch (xl) { 1276 case MXL_RV32: 1277 return status | MSTATUS32_SD; 1278 case MXL_RV64: 1279 return status | MSTATUS64_SD; 1280 case MXL_RV128: 1281 return MSTATUSH128_SD; 1282 default: 1283 g_assert_not_reached(); 1284 } 1285 } 1286 return status; 1287 } 1288 1289 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 1290 target_ulong *val) 1291 { 1292 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 1293 return RISCV_EXCP_NONE; 1294 } 1295 1296 static bool validate_vm(CPURISCVState *env, target_ulong vm) 1297 { 1298 return (vm & 0xf) <= 1299 satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map); 1300 } 1301 1302 static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp, 1303 target_ulong val) 1304 { 1305 bool valid = false; 1306 target_ulong new_mpp = get_field(val, MSTATUS_MPP); 1307 1308 switch (new_mpp) { 1309 case PRV_M: 1310 valid = true; 1311 break; 1312 case PRV_S: 1313 valid = riscv_has_ext(env, RVS); 1314 break; 1315 case PRV_U: 1316 valid = riscv_has_ext(env, RVU); 1317 break; 1318 } 1319 1320 /* Remain field unchanged if new_mpp value is invalid */ 1321 if (!valid) { 1322 val = set_field(val, MSTATUS_MPP, old_mpp); 1323 } 1324 1325 return val; 1326 } 1327 1328 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 1329 target_ulong val) 1330 { 1331 uint64_t mstatus = env->mstatus; 1332 uint64_t mask = 0; 1333 RISCVMXL xl = riscv_cpu_mxl(env); 1334 1335 /* 1336 * MPP field have been made WARL since priv version 1.11. However, 1337 * legalization for it will not break any software running on 1.10. 1338 */ 1339 val = legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); 1340 1341 /* flush tlb on mstatus fields that affect VM */ 1342 if ((val ^ mstatus) & MSTATUS_MXR) { 1343 tlb_flush(env_cpu(env)); 1344 } 1345 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 1346 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 1347 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 1348 MSTATUS_TW; 1349 1350 if (riscv_has_ext(env, RVF)) { 1351 mask |= MSTATUS_FS; 1352 } 1353 if (riscv_has_ext(env, RVV)) { 1354 mask |= MSTATUS_VS; 1355 } 1356 1357 if (xl != MXL_RV32 || env->debugger) { 1358 if (riscv_has_ext(env, RVH)) { 1359 mask |= MSTATUS_MPV | MSTATUS_GVA; 1360 } 1361 if ((val & MSTATUS64_UXL) != 0) { 1362 mask |= MSTATUS64_UXL; 1363 } 1364 } 1365 1366 mstatus = (mstatus & ~mask) | (val & mask); 1367 1368 env->mstatus = mstatus; 1369 1370 /* 1371 * Except in debug mode, UXL/SXL can only be modified by higher 1372 * privilege mode. So xl will not be changed in normal mode. 1373 */ 1374 if (env->debugger) { 1375 env->xl = cpu_recompute_xl(env); 1376 } 1377 1378 riscv_cpu_update_mask(env); 1379 return RISCV_EXCP_NONE; 1380 } 1381 1382 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 1383 target_ulong *val) 1384 { 1385 *val = env->mstatus >> 32; 1386 return RISCV_EXCP_NONE; 1387 } 1388 1389 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 1390 target_ulong val) 1391 { 1392 uint64_t valh = (uint64_t)val << 32; 1393 uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; 1394 1395 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 1396 1397 return RISCV_EXCP_NONE; 1398 } 1399 1400 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 1401 Int128 *val) 1402 { 1403 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, 1404 env->mstatus)); 1405 return RISCV_EXCP_NONE; 1406 } 1407 1408 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 1409 Int128 *val) 1410 { 1411 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 1412 return RISCV_EXCP_NONE; 1413 } 1414 1415 static RISCVException read_misa(CPURISCVState *env, int csrno, 1416 target_ulong *val) 1417 { 1418 target_ulong misa; 1419 1420 switch (env->misa_mxl) { 1421 case MXL_RV32: 1422 misa = (target_ulong)MXL_RV32 << 30; 1423 break; 1424 #ifdef TARGET_RISCV64 1425 case MXL_RV64: 1426 misa = (target_ulong)MXL_RV64 << 62; 1427 break; 1428 #endif 1429 default: 1430 g_assert_not_reached(); 1431 } 1432 1433 *val = misa | env->misa_ext; 1434 return RISCV_EXCP_NONE; 1435 } 1436 1437 static RISCVException write_misa(CPURISCVState *env, int csrno, 1438 target_ulong val) 1439 { 1440 RISCVCPU *cpu = env_archcpu(env); 1441 uint32_t orig_misa_ext = env->misa_ext; 1442 Error *local_err = NULL; 1443 1444 if (!riscv_cpu_cfg(env)->misa_w) { 1445 /* drop write to misa */ 1446 return RISCV_EXCP_NONE; 1447 } 1448 1449 /* Mask extensions that are not supported by this hart */ 1450 val &= env->misa_ext_mask; 1451 1452 /* 1453 * Suppress 'C' if next instruction is not aligned 1454 * TODO: this should check next_pc 1455 */ 1456 if ((val & RVC) && (GETPC() & ~3) != 0) { 1457 val &= ~RVC; 1458 } 1459 1460 /* Disable RVG if any of its dependencies are disabled */ 1461 if (!(val & RVI && val & RVM && val & RVA && 1462 val & RVF && val & RVD)) { 1463 val &= ~RVG; 1464 } 1465 1466 /* If nothing changed, do nothing. */ 1467 if (val == env->misa_ext) { 1468 return RISCV_EXCP_NONE; 1469 } 1470 1471 env->misa_ext = val; 1472 riscv_cpu_validate_set_extensions(cpu, &local_err); 1473 if (local_err != NULL) { 1474 /* Rollback on validation error */ 1475 qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value " 1476 "0x%x, keeping existing MISA ext 0x%x\n", 1477 env->misa_ext, orig_misa_ext); 1478 1479 env->misa_ext = orig_misa_ext; 1480 1481 return RISCV_EXCP_NONE; 1482 } 1483 1484 if (!(env->misa_ext & RVF)) { 1485 env->mstatus &= ~MSTATUS_FS; 1486 } 1487 1488 /* flush translation cache */ 1489 tb_flush(env_cpu(env)); 1490 env->xl = riscv_cpu_mxl(env); 1491 return RISCV_EXCP_NONE; 1492 } 1493 1494 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 1495 target_ulong *val) 1496 { 1497 *val = env->medeleg; 1498 return RISCV_EXCP_NONE; 1499 } 1500 1501 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 1502 target_ulong val) 1503 { 1504 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 1505 return RISCV_EXCP_NONE; 1506 } 1507 1508 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 1509 uint64_t *ret_val, 1510 uint64_t new_val, uint64_t wr_mask) 1511 { 1512 uint64_t mask = wr_mask & delegable_ints; 1513 1514 if (ret_val) { 1515 *ret_val = env->mideleg; 1516 } 1517 1518 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 1519 1520 if (riscv_has_ext(env, RVH)) { 1521 env->mideleg |= HS_MODE_INTERRUPTS; 1522 } 1523 1524 return RISCV_EXCP_NONE; 1525 } 1526 1527 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 1528 target_ulong *ret_val, 1529 target_ulong new_val, target_ulong wr_mask) 1530 { 1531 uint64_t rval; 1532 RISCVException ret; 1533 1534 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 1535 if (ret_val) { 1536 *ret_val = rval; 1537 } 1538 1539 return ret; 1540 } 1541 1542 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 1543 target_ulong *ret_val, 1544 target_ulong new_val, 1545 target_ulong wr_mask) 1546 { 1547 uint64_t rval; 1548 RISCVException ret; 1549 1550 ret = rmw_mideleg64(env, csrno, &rval, 1551 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1552 if (ret_val) { 1553 *ret_val = rval >> 32; 1554 } 1555 1556 return ret; 1557 } 1558 1559 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 1560 uint64_t *ret_val, 1561 uint64_t new_val, uint64_t wr_mask) 1562 { 1563 uint64_t mask = wr_mask & all_ints; 1564 1565 if (ret_val) { 1566 *ret_val = env->mie; 1567 } 1568 1569 env->mie = (env->mie & ~mask) | (new_val & mask); 1570 1571 if (!riscv_has_ext(env, RVH)) { 1572 env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS); 1573 } 1574 1575 return RISCV_EXCP_NONE; 1576 } 1577 1578 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 1579 target_ulong *ret_val, 1580 target_ulong new_val, target_ulong wr_mask) 1581 { 1582 uint64_t rval; 1583 RISCVException ret; 1584 1585 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 1586 if (ret_val) { 1587 *ret_val = rval; 1588 } 1589 1590 return ret; 1591 } 1592 1593 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 1594 target_ulong *ret_val, 1595 target_ulong new_val, target_ulong wr_mask) 1596 { 1597 uint64_t rval; 1598 RISCVException ret; 1599 1600 ret = rmw_mie64(env, csrno, &rval, 1601 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1602 if (ret_val) { 1603 *ret_val = rval >> 32; 1604 } 1605 1606 return ret; 1607 } 1608 1609 static RISCVException rmw_mvien64(CPURISCVState *env, int csrno, 1610 uint64_t *ret_val, 1611 uint64_t new_val, uint64_t wr_mask) 1612 { 1613 uint64_t mask = wr_mask & mvien_writable_mask; 1614 1615 if (ret_val) { 1616 *ret_val = env->mvien; 1617 } 1618 1619 env->mvien = (env->mvien & ~mask) | (new_val & mask); 1620 1621 return RISCV_EXCP_NONE; 1622 } 1623 1624 static RISCVException rmw_mvien(CPURISCVState *env, int csrno, 1625 target_ulong *ret_val, 1626 target_ulong new_val, target_ulong wr_mask) 1627 { 1628 uint64_t rval; 1629 RISCVException ret; 1630 1631 ret = rmw_mvien64(env, csrno, &rval, new_val, wr_mask); 1632 if (ret_val) { 1633 *ret_val = rval; 1634 } 1635 1636 return ret; 1637 } 1638 1639 static RISCVException rmw_mvienh(CPURISCVState *env, int csrno, 1640 target_ulong *ret_val, 1641 target_ulong new_val, target_ulong wr_mask) 1642 { 1643 uint64_t rval; 1644 RISCVException ret; 1645 1646 ret = rmw_mvien64(env, csrno, &rval, 1647 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1648 if (ret_val) { 1649 *ret_val = rval >> 32; 1650 } 1651 1652 return ret; 1653 } 1654 1655 static RISCVException read_mtopi(CPURISCVState *env, int csrno, 1656 target_ulong *val) 1657 { 1658 int irq; 1659 uint8_t iprio; 1660 1661 irq = riscv_cpu_mirq_pending(env); 1662 if (irq <= 0 || irq > 63) { 1663 *val = 0; 1664 } else { 1665 iprio = env->miprio[irq]; 1666 if (!iprio) { 1667 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 1668 iprio = IPRIO_MMAXIPRIO; 1669 } 1670 } 1671 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 1672 *val |= iprio; 1673 } 1674 1675 return RISCV_EXCP_NONE; 1676 } 1677 1678 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 1679 { 1680 if (!env->virt_enabled) { 1681 return csrno; 1682 } 1683 1684 switch (csrno) { 1685 case CSR_SISELECT: 1686 return CSR_VSISELECT; 1687 case CSR_SIREG: 1688 return CSR_VSIREG; 1689 case CSR_STOPEI: 1690 return CSR_VSTOPEI; 1691 default: 1692 return csrno; 1693 }; 1694 } 1695 1696 static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, 1697 target_ulong *val, target_ulong new_val, 1698 target_ulong wr_mask) 1699 { 1700 target_ulong *iselect; 1701 1702 /* Translate CSR number for VS-mode */ 1703 csrno = aia_xlate_vs_csrno(env, csrno); 1704 1705 /* Find the iselect CSR based on CSR number */ 1706 switch (csrno) { 1707 case CSR_MISELECT: 1708 iselect = &env->miselect; 1709 break; 1710 case CSR_SISELECT: 1711 iselect = &env->siselect; 1712 break; 1713 case CSR_VSISELECT: 1714 iselect = &env->vsiselect; 1715 break; 1716 default: 1717 return RISCV_EXCP_ILLEGAL_INST; 1718 }; 1719 1720 if (val) { 1721 *val = *iselect; 1722 } 1723 1724 wr_mask &= ISELECT_MASK; 1725 if (wr_mask) { 1726 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1727 } 1728 1729 return RISCV_EXCP_NONE; 1730 } 1731 1732 static int rmw_iprio(target_ulong xlen, 1733 target_ulong iselect, uint8_t *iprio, 1734 target_ulong *val, target_ulong new_val, 1735 target_ulong wr_mask, int ext_irq_no) 1736 { 1737 int i, firq, nirqs; 1738 target_ulong old_val; 1739 1740 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1741 return -EINVAL; 1742 } 1743 if (xlen != 32 && iselect & 0x1) { 1744 return -EINVAL; 1745 } 1746 1747 nirqs = 4 * (xlen / 32); 1748 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1749 1750 old_val = 0; 1751 for (i = 0; i < nirqs; i++) { 1752 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1753 } 1754 1755 if (val) { 1756 *val = old_val; 1757 } 1758 1759 if (wr_mask) { 1760 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1761 for (i = 0; i < nirqs; i++) { 1762 /* 1763 * M-level and S-level external IRQ priority always read-only 1764 * zero. This means default priority order is always preferred 1765 * for M-level and S-level external IRQs. 1766 */ 1767 if ((firq + i) == ext_irq_no) { 1768 continue; 1769 } 1770 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1771 } 1772 } 1773 1774 return 0; 1775 } 1776 1777 static RISCVException rmw_xireg(CPURISCVState *env, int csrno, 1778 target_ulong *val, target_ulong new_val, 1779 target_ulong wr_mask) 1780 { 1781 bool virt, isel_reserved; 1782 uint8_t *iprio; 1783 int ret = -EINVAL; 1784 target_ulong priv, isel, vgein; 1785 1786 /* Translate CSR number for VS-mode */ 1787 csrno = aia_xlate_vs_csrno(env, csrno); 1788 1789 /* Decode register details from CSR number */ 1790 virt = false; 1791 isel_reserved = false; 1792 switch (csrno) { 1793 case CSR_MIREG: 1794 iprio = env->miprio; 1795 isel = env->miselect; 1796 priv = PRV_M; 1797 break; 1798 case CSR_SIREG: 1799 if (env->priv == PRV_S && env->mvien & MIP_SEIP && 1800 env->siselect >= ISELECT_IMSIC_EIDELIVERY && 1801 env->siselect <= ISELECT_IMSIC_EIE63) { 1802 goto done; 1803 } 1804 iprio = env->siprio; 1805 isel = env->siselect; 1806 priv = PRV_S; 1807 break; 1808 case CSR_VSIREG: 1809 iprio = env->hviprio; 1810 isel = env->vsiselect; 1811 priv = PRV_S; 1812 virt = true; 1813 break; 1814 default: 1815 goto done; 1816 }; 1817 1818 /* Find the selected guest interrupt file */ 1819 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1820 1821 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1822 /* Local interrupt priority registers not available for VS-mode */ 1823 if (!virt) { 1824 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1825 isel, iprio, val, new_val, wr_mask, 1826 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1827 } 1828 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1829 /* IMSIC registers only available when machine implements it. */ 1830 if (env->aia_ireg_rmw_fn[priv]) { 1831 /* Selected guest interrupt file should not be zero */ 1832 if (virt && (!vgein || env->geilen < vgein)) { 1833 goto done; 1834 } 1835 /* Call machine specific IMSIC register emulation */ 1836 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1837 AIA_MAKE_IREG(isel, priv, virt, vgein, 1838 riscv_cpu_mxl_bits(env)), 1839 val, new_val, wr_mask); 1840 } 1841 } else { 1842 isel_reserved = true; 1843 } 1844 1845 done: 1846 if (ret) { 1847 return (env->virt_enabled && virt && !isel_reserved) ? 1848 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1849 } 1850 return RISCV_EXCP_NONE; 1851 } 1852 1853 static RISCVException rmw_xtopei(CPURISCVState *env, int csrno, 1854 target_ulong *val, target_ulong new_val, 1855 target_ulong wr_mask) 1856 { 1857 bool virt; 1858 int ret = -EINVAL; 1859 target_ulong priv, vgein; 1860 1861 /* Translate CSR number for VS-mode */ 1862 csrno = aia_xlate_vs_csrno(env, csrno); 1863 1864 /* Decode register details from CSR number */ 1865 virt = false; 1866 switch (csrno) { 1867 case CSR_MTOPEI: 1868 priv = PRV_M; 1869 break; 1870 case CSR_STOPEI: 1871 if (env->mvien & MIP_SEIP && env->priv == PRV_S) { 1872 goto done; 1873 } 1874 priv = PRV_S; 1875 break; 1876 case CSR_VSTOPEI: 1877 priv = PRV_S; 1878 virt = true; 1879 break; 1880 default: 1881 goto done; 1882 }; 1883 1884 /* IMSIC CSRs only available when machine implements IMSIC. */ 1885 if (!env->aia_ireg_rmw_fn[priv]) { 1886 goto done; 1887 } 1888 1889 /* Find the selected guest interrupt file */ 1890 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1891 1892 /* Selected guest interrupt file should be valid */ 1893 if (virt && (!vgein || env->geilen < vgein)) { 1894 goto done; 1895 } 1896 1897 /* Call machine specific IMSIC register emulation for TOPEI */ 1898 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1899 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1900 riscv_cpu_mxl_bits(env)), 1901 val, new_val, wr_mask); 1902 1903 done: 1904 if (ret) { 1905 return (env->virt_enabled && virt) ? 1906 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1907 } 1908 return RISCV_EXCP_NONE; 1909 } 1910 1911 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1912 target_ulong *val) 1913 { 1914 *val = env->mtvec; 1915 return RISCV_EXCP_NONE; 1916 } 1917 1918 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1919 target_ulong val) 1920 { 1921 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1922 if ((val & 3) < 2) { 1923 env->mtvec = val; 1924 } else { 1925 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1926 } 1927 return RISCV_EXCP_NONE; 1928 } 1929 1930 static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, 1931 target_ulong *val) 1932 { 1933 *val = env->mcountinhibit; 1934 return RISCV_EXCP_NONE; 1935 } 1936 1937 static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, 1938 target_ulong val) 1939 { 1940 int cidx; 1941 PMUCTRState *counter; 1942 RISCVCPU *cpu = env_archcpu(env); 1943 1944 /* WARL register - disable unavailable counters; TM bit is always 0 */ 1945 env->mcountinhibit = 1946 val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR); 1947 1948 /* Check if any other counter is also monitoring cycles/instructions */ 1949 for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { 1950 if (!get_field(env->mcountinhibit, BIT(cidx))) { 1951 counter = &env->pmu_ctrs[cidx]; 1952 counter->started = true; 1953 } 1954 } 1955 1956 return RISCV_EXCP_NONE; 1957 } 1958 1959 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1960 target_ulong *val) 1961 { 1962 *val = env->mcounteren; 1963 return RISCV_EXCP_NONE; 1964 } 1965 1966 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1967 target_ulong val) 1968 { 1969 RISCVCPU *cpu = env_archcpu(env); 1970 1971 /* WARL register - disable unavailable counters */ 1972 env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM | 1973 COUNTEREN_IR); 1974 return RISCV_EXCP_NONE; 1975 } 1976 1977 /* Machine Trap Handling */ 1978 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1979 Int128 *val) 1980 { 1981 *val = int128_make128(env->mscratch, env->mscratchh); 1982 return RISCV_EXCP_NONE; 1983 } 1984 1985 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1986 Int128 val) 1987 { 1988 env->mscratch = int128_getlo(val); 1989 env->mscratchh = int128_gethi(val); 1990 return RISCV_EXCP_NONE; 1991 } 1992 1993 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1994 target_ulong *val) 1995 { 1996 *val = env->mscratch; 1997 return RISCV_EXCP_NONE; 1998 } 1999 2000 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 2001 target_ulong val) 2002 { 2003 env->mscratch = val; 2004 return RISCV_EXCP_NONE; 2005 } 2006 2007 static RISCVException read_mepc(CPURISCVState *env, int csrno, 2008 target_ulong *val) 2009 { 2010 *val = env->mepc; 2011 return RISCV_EXCP_NONE; 2012 } 2013 2014 static RISCVException write_mepc(CPURISCVState *env, int csrno, 2015 target_ulong val) 2016 { 2017 env->mepc = val; 2018 return RISCV_EXCP_NONE; 2019 } 2020 2021 static RISCVException read_mcause(CPURISCVState *env, int csrno, 2022 target_ulong *val) 2023 { 2024 *val = env->mcause; 2025 return RISCV_EXCP_NONE; 2026 } 2027 2028 static RISCVException write_mcause(CPURISCVState *env, int csrno, 2029 target_ulong val) 2030 { 2031 env->mcause = val; 2032 return RISCV_EXCP_NONE; 2033 } 2034 2035 static RISCVException read_mtval(CPURISCVState *env, int csrno, 2036 target_ulong *val) 2037 { 2038 *val = env->mtval; 2039 return RISCV_EXCP_NONE; 2040 } 2041 2042 static RISCVException write_mtval(CPURISCVState *env, int csrno, 2043 target_ulong val) 2044 { 2045 env->mtval = val; 2046 return RISCV_EXCP_NONE; 2047 } 2048 2049 /* Execution environment configuration setup */ 2050 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 2051 target_ulong *val) 2052 { 2053 *val = env->menvcfg; 2054 return RISCV_EXCP_NONE; 2055 } 2056 2057 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 2058 target_ulong val) 2059 { 2060 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); 2061 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 2062 2063 if (riscv_cpu_mxl(env) == MXL_RV64) { 2064 mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | 2065 (cfg->ext_sstc ? MENVCFG_STCE : 0) | 2066 (cfg->ext_svadu ? MENVCFG_ADUE : 0); 2067 } 2068 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 2069 2070 return RISCV_EXCP_NONE; 2071 } 2072 2073 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 2074 target_ulong *val) 2075 { 2076 *val = env->menvcfg >> 32; 2077 return RISCV_EXCP_NONE; 2078 } 2079 2080 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 2081 target_ulong val) 2082 { 2083 const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); 2084 uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | 2085 (cfg->ext_sstc ? MENVCFG_STCE : 0) | 2086 (cfg->ext_svadu ? MENVCFG_ADUE : 0); 2087 uint64_t valh = (uint64_t)val << 32; 2088 2089 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 2090 2091 return RISCV_EXCP_NONE; 2092 } 2093 2094 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 2095 target_ulong *val) 2096 { 2097 RISCVException ret; 2098 2099 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2100 if (ret != RISCV_EXCP_NONE) { 2101 return ret; 2102 } 2103 2104 *val = env->senvcfg; 2105 return RISCV_EXCP_NONE; 2106 } 2107 2108 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 2109 target_ulong val) 2110 { 2111 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 2112 RISCVException ret; 2113 2114 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2115 if (ret != RISCV_EXCP_NONE) { 2116 return ret; 2117 } 2118 2119 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 2120 return RISCV_EXCP_NONE; 2121 } 2122 2123 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 2124 target_ulong *val) 2125 { 2126 RISCVException ret; 2127 2128 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2129 if (ret != RISCV_EXCP_NONE) { 2130 return ret; 2131 } 2132 2133 /* 2134 * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0 2135 * henvcfg.stce is read_only 0 when menvcfg.stce = 0 2136 * henvcfg.hade is read_only 0 when menvcfg.hade = 0 2137 */ 2138 *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | 2139 env->menvcfg); 2140 return RISCV_EXCP_NONE; 2141 } 2142 2143 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 2144 target_ulong val) 2145 { 2146 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 2147 RISCVException ret; 2148 2149 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2150 if (ret != RISCV_EXCP_NONE) { 2151 return ret; 2152 } 2153 2154 if (riscv_cpu_mxl(env) == MXL_RV64) { 2155 mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); 2156 } 2157 2158 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 2159 2160 return RISCV_EXCP_NONE; 2161 } 2162 2163 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 2164 target_ulong *val) 2165 { 2166 RISCVException ret; 2167 2168 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2169 if (ret != RISCV_EXCP_NONE) { 2170 return ret; 2171 } 2172 2173 *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | 2174 env->menvcfg)) >> 32; 2175 return RISCV_EXCP_NONE; 2176 } 2177 2178 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 2179 target_ulong val) 2180 { 2181 uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | 2182 HENVCFG_ADUE); 2183 uint64_t valh = (uint64_t)val << 32; 2184 RISCVException ret; 2185 2186 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); 2187 if (ret != RISCV_EXCP_NONE) { 2188 return ret; 2189 } 2190 2191 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 2192 return RISCV_EXCP_NONE; 2193 } 2194 2195 static RISCVException read_mstateen(CPURISCVState *env, int csrno, 2196 target_ulong *val) 2197 { 2198 *val = env->mstateen[csrno - CSR_MSTATEEN0]; 2199 2200 return RISCV_EXCP_NONE; 2201 } 2202 2203 static RISCVException write_mstateen(CPURISCVState *env, int csrno, 2204 uint64_t wr_mask, target_ulong new_val) 2205 { 2206 uint64_t *reg; 2207 2208 reg = &env->mstateen[csrno - CSR_MSTATEEN0]; 2209 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); 2210 2211 return RISCV_EXCP_NONE; 2212 } 2213 2214 static RISCVException write_mstateen0(CPURISCVState *env, int csrno, 2215 target_ulong new_val) 2216 { 2217 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2218 if (!riscv_has_ext(env, RVF)) { 2219 wr_mask |= SMSTATEEN0_FCSR; 2220 } 2221 2222 return write_mstateen(env, csrno, wr_mask, new_val); 2223 } 2224 2225 static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno, 2226 target_ulong new_val) 2227 { 2228 return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); 2229 } 2230 2231 static RISCVException read_mstateenh(CPURISCVState *env, int csrno, 2232 target_ulong *val) 2233 { 2234 *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; 2235 2236 return RISCV_EXCP_NONE; 2237 } 2238 2239 static RISCVException write_mstateenh(CPURISCVState *env, int csrno, 2240 uint64_t wr_mask, target_ulong new_val) 2241 { 2242 uint64_t *reg, val; 2243 2244 reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; 2245 val = (uint64_t)new_val << 32; 2246 val |= *reg & 0xFFFFFFFF; 2247 *reg = (*reg & ~wr_mask) | (val & wr_mask); 2248 2249 return RISCV_EXCP_NONE; 2250 } 2251 2252 static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, 2253 target_ulong new_val) 2254 { 2255 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2256 2257 return write_mstateenh(env, csrno, wr_mask, new_val); 2258 } 2259 2260 static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno, 2261 target_ulong new_val) 2262 { 2263 return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); 2264 } 2265 2266 static RISCVException read_hstateen(CPURISCVState *env, int csrno, 2267 target_ulong *val) 2268 { 2269 int index = csrno - CSR_HSTATEEN0; 2270 2271 *val = env->hstateen[index] & env->mstateen[index]; 2272 2273 return RISCV_EXCP_NONE; 2274 } 2275 2276 static RISCVException write_hstateen(CPURISCVState *env, int csrno, 2277 uint64_t mask, target_ulong new_val) 2278 { 2279 int index = csrno - CSR_HSTATEEN0; 2280 uint64_t *reg, wr_mask; 2281 2282 reg = &env->hstateen[index]; 2283 wr_mask = env->mstateen[index] & mask; 2284 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); 2285 2286 return RISCV_EXCP_NONE; 2287 } 2288 2289 static RISCVException write_hstateen0(CPURISCVState *env, int csrno, 2290 target_ulong new_val) 2291 { 2292 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2293 2294 if (!riscv_has_ext(env, RVF)) { 2295 wr_mask |= SMSTATEEN0_FCSR; 2296 } 2297 2298 return write_hstateen(env, csrno, wr_mask, new_val); 2299 } 2300 2301 static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno, 2302 target_ulong new_val) 2303 { 2304 return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); 2305 } 2306 2307 static RISCVException read_hstateenh(CPURISCVState *env, int csrno, 2308 target_ulong *val) 2309 { 2310 int index = csrno - CSR_HSTATEEN0H; 2311 2312 *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); 2313 2314 return RISCV_EXCP_NONE; 2315 } 2316 2317 static RISCVException write_hstateenh(CPURISCVState *env, int csrno, 2318 uint64_t mask, target_ulong new_val) 2319 { 2320 int index = csrno - CSR_HSTATEEN0H; 2321 uint64_t *reg, wr_mask, val; 2322 2323 reg = &env->hstateen[index]; 2324 val = (uint64_t)new_val << 32; 2325 val |= *reg & 0xFFFFFFFF; 2326 wr_mask = env->mstateen[index] & mask; 2327 *reg = (*reg & ~wr_mask) | (val & wr_mask); 2328 2329 return RISCV_EXCP_NONE; 2330 } 2331 2332 static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, 2333 target_ulong new_val) 2334 { 2335 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2336 2337 return write_hstateenh(env, csrno, wr_mask, new_val); 2338 } 2339 2340 static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno, 2341 target_ulong new_val) 2342 { 2343 return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); 2344 } 2345 2346 static RISCVException read_sstateen(CPURISCVState *env, int csrno, 2347 target_ulong *val) 2348 { 2349 bool virt = env->virt_enabled; 2350 int index = csrno - CSR_SSTATEEN0; 2351 2352 *val = env->sstateen[index] & env->mstateen[index]; 2353 if (virt) { 2354 *val &= env->hstateen[index]; 2355 } 2356 2357 return RISCV_EXCP_NONE; 2358 } 2359 2360 static RISCVException write_sstateen(CPURISCVState *env, int csrno, 2361 uint64_t mask, target_ulong new_val) 2362 { 2363 bool virt = env->virt_enabled; 2364 int index = csrno - CSR_SSTATEEN0; 2365 uint64_t wr_mask; 2366 uint64_t *reg; 2367 2368 wr_mask = env->mstateen[index] & mask; 2369 if (virt) { 2370 wr_mask &= env->hstateen[index]; 2371 } 2372 2373 reg = &env->sstateen[index]; 2374 *reg = (*reg & ~wr_mask) | (new_val & wr_mask); 2375 2376 return RISCV_EXCP_NONE; 2377 } 2378 2379 static RISCVException write_sstateen0(CPURISCVState *env, int csrno, 2380 target_ulong new_val) 2381 { 2382 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; 2383 2384 if (!riscv_has_ext(env, RVF)) { 2385 wr_mask |= SMSTATEEN0_FCSR; 2386 } 2387 2388 return write_sstateen(env, csrno, wr_mask, new_val); 2389 } 2390 2391 static RISCVException write_sstateen_1_3(CPURISCVState *env, int csrno, 2392 target_ulong new_val) 2393 { 2394 return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); 2395 } 2396 2397 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 2398 uint64_t *ret_val, 2399 uint64_t new_val, uint64_t wr_mask) 2400 { 2401 uint64_t old_mip, mask = wr_mask & delegable_ints; 2402 uint32_t gin; 2403 2404 if (mask & MIP_SEIP) { 2405 env->software_seip = new_val & MIP_SEIP; 2406 new_val |= env->external_seip * MIP_SEIP; 2407 } 2408 2409 if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) && 2410 get_field(env->menvcfg, MENVCFG_STCE)) { 2411 /* sstc extension forbids STIP & VSTIP to be writeable in mip */ 2412 mask = mask & ~(MIP_STIP | MIP_VSTIP); 2413 } 2414 2415 if (mask) { 2416 old_mip = riscv_cpu_update_mip(env, mask, (new_val & mask)); 2417 } else { 2418 old_mip = env->mip; 2419 } 2420 2421 if (csrno != CSR_HVIP) { 2422 gin = get_field(env->hstatus, HSTATUS_VGEIN); 2423 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 2424 old_mip |= env->vstime_irq ? MIP_VSTIP : 0; 2425 } 2426 2427 if (ret_val) { 2428 *ret_val = old_mip; 2429 } 2430 2431 return RISCV_EXCP_NONE; 2432 } 2433 2434 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 2435 target_ulong *ret_val, 2436 target_ulong new_val, target_ulong wr_mask) 2437 { 2438 uint64_t rval; 2439 RISCVException ret; 2440 2441 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 2442 if (ret_val) { 2443 *ret_val = rval; 2444 } 2445 2446 return ret; 2447 } 2448 2449 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 2450 target_ulong *ret_val, 2451 target_ulong new_val, target_ulong wr_mask) 2452 { 2453 uint64_t rval; 2454 RISCVException ret; 2455 2456 ret = rmw_mip64(env, csrno, &rval, 2457 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2458 if (ret_val) { 2459 *ret_val = rval >> 32; 2460 } 2461 2462 return ret; 2463 } 2464 2465 /* 2466 * The function is written for two use-cases: 2467 * 1- To access mvip csr as is for m-mode access. 2468 * 2- To access sip as a combination of mip and mvip for s-mode. 2469 * 2470 * Both report bits 1, 5, 9 and 13:63 but with the exception of 2471 * STIP being read-only zero in case of mvip when sstc extension 2472 * is present. 2473 * Also, sip needs to be read-only zero when both mideleg[i] and 2474 * mvien[i] are zero but mvip needs to be an alias of mip. 2475 */ 2476 static RISCVException rmw_mvip64(CPURISCVState *env, int csrno, 2477 uint64_t *ret_val, 2478 uint64_t new_val, uint64_t wr_mask) 2479 { 2480 RISCVCPU *cpu = env_archcpu(env); 2481 target_ulong ret_mip = 0; 2482 RISCVException ret; 2483 uint64_t old_mvip; 2484 2485 /* 2486 * mideleg[i] mvien[i] 2487 * 0 0 No delegation. mvip[i] is alias of mip[i]. 2488 * 0 1 mvip[i] becomes source of interrupt, mip bypassed. 2489 * 1 X mip[i] is source of interrupt and mvip[i] aliases 2490 * mip[i]. 2491 * 2492 * So alias condition would be for bits: 2493 * ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (mideleg | ~mvien)) | 2494 * (!sstc & MIP_STIP) 2495 * 2496 * Non-alias condition will be for bits: 2497 * (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (~mideleg & mvien) 2498 * 2499 * alias_mask denotes the bits that come from mip nalias_mask denotes bits 2500 * that come from hvip. 2501 */ 2502 uint64_t alias_mask = ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & 2503 (env->mideleg | ~env->mvien)) | MIP_STIP; 2504 uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & 2505 (~env->mideleg & env->mvien); 2506 uint64_t wr_mask_mvip; 2507 uint64_t wr_mask_mip; 2508 2509 /* 2510 * mideleg[i] mvien[i] 2511 * 0 0 sip[i] read-only zero. 2512 * 0 1 sip[i] alias of mvip[i]. 2513 * 1 X sip[i] alias of mip[i]. 2514 * 2515 * Both alias and non-alias mask remain same for sip except for bits 2516 * which are zero in both mideleg and mvien. 2517 */ 2518 if (csrno == CSR_SIP) { 2519 /* Remove bits that are zero in both mideleg and mvien. */ 2520 alias_mask &= (env->mideleg | env->mvien); 2521 nalias_mask &= (env->mideleg | env->mvien); 2522 } 2523 2524 /* 2525 * If sstc is present, mvip.STIP is not an alias of mip.STIP so clear 2526 * that our in mip returned value. 2527 */ 2528 if (cpu->cfg.ext_sstc && (env->priv == PRV_M) && 2529 get_field(env->menvcfg, MENVCFG_STCE)) { 2530 alias_mask &= ~MIP_STIP; 2531 } 2532 2533 wr_mask_mip = wr_mask & alias_mask & mvip_writable_mask; 2534 wr_mask_mvip = wr_mask & nalias_mask & mvip_writable_mask; 2535 2536 /* 2537 * For bits set in alias_mask, mvip needs to be alias of mip, so forward 2538 * this to rmw_mip. 2539 */ 2540 ret = rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip); 2541 if (ret != RISCV_EXCP_NONE) { 2542 return ret; 2543 } 2544 2545 old_mvip = env->mvip; 2546 2547 /* 2548 * Write to mvip. Update only non-alias bits. Alias bits were updated 2549 * in mip in rmw_mip above. 2550 */ 2551 if (wr_mask_mvip) { 2552 env->mvip = (env->mvip & ~wr_mask_mvip) | (new_val & wr_mask_mvip); 2553 2554 /* 2555 * Given mvip is separate source from mip, we need to trigger interrupt 2556 * from here separately. Normally this happen from riscv_cpu_update_mip. 2557 */ 2558 riscv_cpu_interrupt(env); 2559 } 2560 2561 if (ret_val) { 2562 ret_mip &= alias_mask; 2563 old_mvip &= nalias_mask; 2564 2565 *ret_val = old_mvip | ret_mip; 2566 } 2567 2568 return RISCV_EXCP_NONE; 2569 } 2570 2571 static RISCVException rmw_mvip(CPURISCVState *env, int csrno, 2572 target_ulong *ret_val, 2573 target_ulong new_val, target_ulong wr_mask) 2574 { 2575 uint64_t rval; 2576 RISCVException ret; 2577 2578 ret = rmw_mvip64(env, csrno, &rval, new_val, wr_mask); 2579 if (ret_val) { 2580 *ret_val = rval; 2581 } 2582 2583 return ret; 2584 } 2585 2586 static RISCVException rmw_mviph(CPURISCVState *env, int csrno, 2587 target_ulong *ret_val, 2588 target_ulong new_val, target_ulong wr_mask) 2589 { 2590 uint64_t rval; 2591 RISCVException ret; 2592 2593 ret = rmw_mvip64(env, csrno, &rval, 2594 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2595 if (ret_val) { 2596 *ret_val = rval >> 32; 2597 } 2598 2599 return ret; 2600 } 2601 2602 /* Supervisor Trap Setup */ 2603 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 2604 Int128 *val) 2605 { 2606 uint64_t mask = sstatus_v1_10_mask; 2607 uint64_t sstatus = env->mstatus & mask; 2608 if (env->xl != MXL_RV32 || env->debugger) { 2609 mask |= SSTATUS64_UXL; 2610 } 2611 2612 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 2613 return RISCV_EXCP_NONE; 2614 } 2615 2616 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 2617 target_ulong *val) 2618 { 2619 target_ulong mask = (sstatus_v1_10_mask); 2620 if (env->xl != MXL_RV32 || env->debugger) { 2621 mask |= SSTATUS64_UXL; 2622 } 2623 /* TODO: Use SXL not MXL. */ 2624 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 2625 return RISCV_EXCP_NONE; 2626 } 2627 2628 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 2629 target_ulong val) 2630 { 2631 target_ulong mask = (sstatus_v1_10_mask); 2632 2633 if (env->xl != MXL_RV32 || env->debugger) { 2634 if ((val & SSTATUS64_UXL) != 0) { 2635 mask |= SSTATUS64_UXL; 2636 } 2637 } 2638 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 2639 return write_mstatus(env, CSR_MSTATUS, newval); 2640 } 2641 2642 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 2643 uint64_t *ret_val, 2644 uint64_t new_val, uint64_t wr_mask) 2645 { 2646 uint64_t alias_mask = (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS) & 2647 env->hideleg; 2648 uint64_t nalias_mask = LOCAL_INTERRUPTS & (~env->hideleg & env->hvien); 2649 uint64_t rval, rval_vs, vsbits; 2650 uint64_t wr_mask_vsie; 2651 uint64_t wr_mask_mie; 2652 RISCVException ret; 2653 2654 /* Bring VS-level bits to correct position */ 2655 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 2656 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 2657 new_val |= vsbits << 1; 2658 2659 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 2660 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 2661 wr_mask |= vsbits << 1; 2662 2663 wr_mask_mie = wr_mask & alias_mask; 2664 wr_mask_vsie = wr_mask & nalias_mask; 2665 2666 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask_mie); 2667 2668 rval_vs = env->vsie & nalias_mask; 2669 env->vsie = (env->vsie & ~wr_mask_vsie) | (new_val & wr_mask_vsie); 2670 2671 if (ret_val) { 2672 rval &= alias_mask; 2673 vsbits = rval & VS_MODE_INTERRUPTS; 2674 rval &= ~VS_MODE_INTERRUPTS; 2675 *ret_val = rval | (vsbits >> 1) | rval_vs; 2676 } 2677 2678 return ret; 2679 } 2680 2681 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 2682 target_ulong *ret_val, 2683 target_ulong new_val, target_ulong wr_mask) 2684 { 2685 uint64_t rval; 2686 RISCVException ret; 2687 2688 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 2689 if (ret_val) { 2690 *ret_val = rval; 2691 } 2692 2693 return ret; 2694 } 2695 2696 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 2697 target_ulong *ret_val, 2698 target_ulong new_val, target_ulong wr_mask) 2699 { 2700 uint64_t rval; 2701 RISCVException ret; 2702 2703 ret = rmw_vsie64(env, csrno, &rval, 2704 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2705 if (ret_val) { 2706 *ret_val = rval >> 32; 2707 } 2708 2709 return ret; 2710 } 2711 2712 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 2713 uint64_t *ret_val, 2714 uint64_t new_val, uint64_t wr_mask) 2715 { 2716 uint64_t nalias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & 2717 (~env->mideleg & env->mvien); 2718 uint64_t alias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->mideleg; 2719 uint64_t sie_mask = wr_mask & nalias_mask; 2720 RISCVException ret; 2721 2722 /* 2723 * mideleg[i] mvien[i] 2724 * 0 0 sie[i] read-only zero. 2725 * 0 1 sie[i] is a separate writable bit. 2726 * 1 X sie[i] alias of mie[i]. 2727 * 2728 * Both alias and non-alias mask remain same for sip except for bits 2729 * which are zero in both mideleg and mvien. 2730 */ 2731 if (env->virt_enabled) { 2732 if (env->hvictl & HVICTL_VTI) { 2733 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 2734 } 2735 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 2736 if (ret_val) { 2737 *ret_val &= alias_mask; 2738 } 2739 } else { 2740 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & alias_mask); 2741 if (ret_val) { 2742 *ret_val &= alias_mask; 2743 *ret_val |= env->sie & nalias_mask; 2744 } 2745 2746 env->sie = (env->sie & ~sie_mask) | (new_val & sie_mask); 2747 } 2748 2749 return ret; 2750 } 2751 2752 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 2753 target_ulong *ret_val, 2754 target_ulong new_val, target_ulong wr_mask) 2755 { 2756 uint64_t rval; 2757 RISCVException ret; 2758 2759 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 2760 if (ret == RISCV_EXCP_NONE && ret_val) { 2761 *ret_val = rval; 2762 } 2763 2764 return ret; 2765 } 2766 2767 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 2768 target_ulong *ret_val, 2769 target_ulong new_val, target_ulong wr_mask) 2770 { 2771 uint64_t rval; 2772 RISCVException ret; 2773 2774 ret = rmw_sie64(env, csrno, &rval, 2775 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2776 if (ret_val) { 2777 *ret_val = rval >> 32; 2778 } 2779 2780 return ret; 2781 } 2782 2783 static RISCVException read_stvec(CPURISCVState *env, int csrno, 2784 target_ulong *val) 2785 { 2786 *val = env->stvec; 2787 return RISCV_EXCP_NONE; 2788 } 2789 2790 static RISCVException write_stvec(CPURISCVState *env, int csrno, 2791 target_ulong val) 2792 { 2793 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 2794 if ((val & 3) < 2) { 2795 env->stvec = val; 2796 } else { 2797 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 2798 } 2799 return RISCV_EXCP_NONE; 2800 } 2801 2802 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 2803 target_ulong *val) 2804 { 2805 *val = env->scounteren; 2806 return RISCV_EXCP_NONE; 2807 } 2808 2809 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 2810 target_ulong val) 2811 { 2812 env->scounteren = val; 2813 return RISCV_EXCP_NONE; 2814 } 2815 2816 /* Supervisor Trap Handling */ 2817 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 2818 Int128 *val) 2819 { 2820 *val = int128_make128(env->sscratch, env->sscratchh); 2821 return RISCV_EXCP_NONE; 2822 } 2823 2824 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 2825 Int128 val) 2826 { 2827 env->sscratch = int128_getlo(val); 2828 env->sscratchh = int128_gethi(val); 2829 return RISCV_EXCP_NONE; 2830 } 2831 2832 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 2833 target_ulong *val) 2834 { 2835 *val = env->sscratch; 2836 return RISCV_EXCP_NONE; 2837 } 2838 2839 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 2840 target_ulong val) 2841 { 2842 env->sscratch = val; 2843 return RISCV_EXCP_NONE; 2844 } 2845 2846 static RISCVException read_sepc(CPURISCVState *env, int csrno, 2847 target_ulong *val) 2848 { 2849 *val = env->sepc; 2850 return RISCV_EXCP_NONE; 2851 } 2852 2853 static RISCVException write_sepc(CPURISCVState *env, int csrno, 2854 target_ulong val) 2855 { 2856 env->sepc = val; 2857 return RISCV_EXCP_NONE; 2858 } 2859 2860 static RISCVException read_scause(CPURISCVState *env, int csrno, 2861 target_ulong *val) 2862 { 2863 *val = env->scause; 2864 return RISCV_EXCP_NONE; 2865 } 2866 2867 static RISCVException write_scause(CPURISCVState *env, int csrno, 2868 target_ulong val) 2869 { 2870 env->scause = val; 2871 return RISCV_EXCP_NONE; 2872 } 2873 2874 static RISCVException read_stval(CPURISCVState *env, int csrno, 2875 target_ulong *val) 2876 { 2877 *val = env->stval; 2878 return RISCV_EXCP_NONE; 2879 } 2880 2881 static RISCVException write_stval(CPURISCVState *env, int csrno, 2882 target_ulong val) 2883 { 2884 env->stval = val; 2885 return RISCV_EXCP_NONE; 2886 } 2887 2888 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2889 uint64_t *ret_val, 2890 uint64_t new_val, uint64_t wr_mask); 2891 2892 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 2893 uint64_t *ret_val, 2894 uint64_t new_val, uint64_t wr_mask) 2895 { 2896 RISCVException ret; 2897 uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; 2898 uint64_t vsbits; 2899 2900 /* Add virtualized bits into vsip mask. */ 2901 mask |= env->hvien & ~env->hideleg; 2902 2903 /* Bring VS-level bits to correct position */ 2904 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 2905 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 2906 new_val |= vsbits << 1; 2907 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 2908 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 2909 wr_mask |= vsbits << 1; 2910 2911 ret = rmw_hvip64(env, csrno, &rval, new_val, 2912 wr_mask & mask & vsip_writable_mask); 2913 if (ret_val) { 2914 rval &= mask; 2915 vsbits = rval & VS_MODE_INTERRUPTS; 2916 rval &= ~VS_MODE_INTERRUPTS; 2917 *ret_val = rval | (vsbits >> 1); 2918 } 2919 2920 return ret; 2921 } 2922 2923 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 2924 target_ulong *ret_val, 2925 target_ulong new_val, target_ulong wr_mask) 2926 { 2927 uint64_t rval; 2928 RISCVException ret; 2929 2930 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 2931 if (ret_val) { 2932 *ret_val = rval; 2933 } 2934 2935 return ret; 2936 } 2937 2938 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 2939 target_ulong *ret_val, 2940 target_ulong new_val, target_ulong wr_mask) 2941 { 2942 uint64_t rval; 2943 RISCVException ret; 2944 2945 ret = rmw_vsip64(env, csrno, &rval, 2946 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2947 if (ret_val) { 2948 *ret_val = rval >> 32; 2949 } 2950 2951 return ret; 2952 } 2953 2954 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 2955 uint64_t *ret_val, 2956 uint64_t new_val, uint64_t wr_mask) 2957 { 2958 RISCVException ret; 2959 uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask; 2960 2961 if (env->virt_enabled) { 2962 if (env->hvictl & HVICTL_VTI) { 2963 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 2964 } 2965 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 2966 } else { 2967 ret = rmw_mvip64(env, csrno, ret_val, new_val, wr_mask & mask); 2968 } 2969 2970 if (ret_val) { 2971 *ret_val &= (env->mideleg | env->mvien) & 2972 (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); 2973 } 2974 2975 return ret; 2976 } 2977 2978 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 2979 target_ulong *ret_val, 2980 target_ulong new_val, target_ulong wr_mask) 2981 { 2982 uint64_t rval; 2983 RISCVException ret; 2984 2985 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 2986 if (ret_val) { 2987 *ret_val = rval; 2988 } 2989 2990 return ret; 2991 } 2992 2993 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 2994 target_ulong *ret_val, 2995 target_ulong new_val, target_ulong wr_mask) 2996 { 2997 uint64_t rval; 2998 RISCVException ret; 2999 3000 ret = rmw_sip64(env, csrno, &rval, 3001 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 3002 if (ret_val) { 3003 *ret_val = rval >> 32; 3004 } 3005 3006 return ret; 3007 } 3008 3009 /* Supervisor Protection and Translation */ 3010 static RISCVException read_satp(CPURISCVState *env, int csrno, 3011 target_ulong *val) 3012 { 3013 if (!riscv_cpu_cfg(env)->mmu) { 3014 *val = 0; 3015 return RISCV_EXCP_NONE; 3016 } 3017 *val = env->satp; 3018 return RISCV_EXCP_NONE; 3019 } 3020 3021 static RISCVException write_satp(CPURISCVState *env, int csrno, 3022 target_ulong val) 3023 { 3024 target_ulong mask; 3025 bool vm; 3026 3027 if (!riscv_cpu_cfg(env)->mmu) { 3028 return RISCV_EXCP_NONE; 3029 } 3030 3031 if (riscv_cpu_mxl(env) == MXL_RV32) { 3032 vm = validate_vm(env, get_field(val, SATP32_MODE)); 3033 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 3034 } else { 3035 vm = validate_vm(env, get_field(val, SATP64_MODE)); 3036 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 3037 } 3038 3039 if (vm && mask) { 3040 /* 3041 * The ISA defines SATP.MODE=Bare as "no translation", but we still 3042 * pass these through QEMU's TLB emulation as it improves 3043 * performance. Flushing the TLB on SATP writes with paging 3044 * enabled avoids leaking those invalid cached mappings. 3045 */ 3046 tlb_flush(env_cpu(env)); 3047 env->satp = val; 3048 } 3049 return RISCV_EXCP_NONE; 3050 } 3051 3052 static RISCVException read_vstopi(CPURISCVState *env, int csrno, 3053 target_ulong *val) 3054 { 3055 int irq, ret; 3056 target_ulong topei; 3057 uint64_t vseip, vsgein; 3058 uint32_t iid, iprio, hviid, hviprio, gein; 3059 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 3060 3061 gein = get_field(env->hstatus, HSTATUS_VGEIN); 3062 hviid = get_field(env->hvictl, HVICTL_IID); 3063 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 3064 3065 if (gein) { 3066 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 3067 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 3068 if (gein <= env->geilen && vseip) { 3069 siid[scount] = IRQ_S_EXT; 3070 siprio[scount] = IPRIO_MMAXIPRIO + 1; 3071 if (env->aia_ireg_rmw_fn[PRV_S]) { 3072 /* 3073 * Call machine specific IMSIC register emulation for 3074 * reading TOPEI. 3075 */ 3076 ret = env->aia_ireg_rmw_fn[PRV_S]( 3077 env->aia_ireg_rmw_fn_arg[PRV_S], 3078 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 3079 riscv_cpu_mxl_bits(env)), 3080 &topei, 0, 0); 3081 if (!ret && topei) { 3082 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 3083 } 3084 } 3085 scount++; 3086 } 3087 } else { 3088 if (hviid == IRQ_S_EXT && hviprio) { 3089 siid[scount] = IRQ_S_EXT; 3090 siprio[scount] = hviprio; 3091 scount++; 3092 } 3093 } 3094 3095 if (env->hvictl & HVICTL_VTI) { 3096 if (hviid != IRQ_S_EXT) { 3097 siid[scount] = hviid; 3098 siprio[scount] = hviprio; 3099 scount++; 3100 } 3101 } else { 3102 irq = riscv_cpu_vsirq_pending(env); 3103 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 3104 siid[scount] = irq; 3105 siprio[scount] = env->hviprio[irq]; 3106 scount++; 3107 } 3108 } 3109 3110 iid = 0; 3111 iprio = UINT_MAX; 3112 for (s = 0; s < scount; s++) { 3113 if (siprio[s] < iprio) { 3114 iid = siid[s]; 3115 iprio = siprio[s]; 3116 } 3117 } 3118 3119 if (iid) { 3120 if (env->hvictl & HVICTL_IPRIOM) { 3121 if (iprio > IPRIO_MMAXIPRIO) { 3122 iprio = IPRIO_MMAXIPRIO; 3123 } 3124 if (!iprio) { 3125 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 3126 iprio = IPRIO_MMAXIPRIO; 3127 } 3128 } 3129 } else { 3130 iprio = 1; 3131 } 3132 } else { 3133 iprio = 0; 3134 } 3135 3136 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 3137 *val |= iprio; 3138 3139 return RISCV_EXCP_NONE; 3140 } 3141 3142 static RISCVException read_stopi(CPURISCVState *env, int csrno, 3143 target_ulong *val) 3144 { 3145 int irq; 3146 uint8_t iprio; 3147 3148 if (env->virt_enabled) { 3149 return read_vstopi(env, CSR_VSTOPI, val); 3150 } 3151 3152 irq = riscv_cpu_sirq_pending(env); 3153 if (irq <= 0 || irq > 63) { 3154 *val = 0; 3155 } else { 3156 iprio = env->siprio[irq]; 3157 if (!iprio) { 3158 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 3159 iprio = IPRIO_MMAXIPRIO; 3160 } 3161 } 3162 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 3163 *val |= iprio; 3164 } 3165 3166 return RISCV_EXCP_NONE; 3167 } 3168 3169 /* Hypervisor Extensions */ 3170 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 3171 target_ulong *val) 3172 { 3173 *val = env->hstatus; 3174 if (riscv_cpu_mxl(env) != MXL_RV32) { 3175 /* We only support 64-bit VSXL */ 3176 *val = set_field(*val, HSTATUS_VSXL, 2); 3177 } 3178 /* We only support little endian */ 3179 *val = set_field(*val, HSTATUS_VSBE, 0); 3180 return RISCV_EXCP_NONE; 3181 } 3182 3183 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 3184 target_ulong val) 3185 { 3186 env->hstatus = val; 3187 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 3188 qemu_log_mask(LOG_UNIMP, 3189 "QEMU does not support mixed HSXLEN options."); 3190 } 3191 if (get_field(val, HSTATUS_VSBE) != 0) { 3192 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 3193 } 3194 return RISCV_EXCP_NONE; 3195 } 3196 3197 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 3198 target_ulong *val) 3199 { 3200 *val = env->hedeleg; 3201 return RISCV_EXCP_NONE; 3202 } 3203 3204 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 3205 target_ulong val) 3206 { 3207 env->hedeleg = val & vs_delegable_excps; 3208 return RISCV_EXCP_NONE; 3209 } 3210 3211 static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, 3212 uint64_t *ret_val, 3213 uint64_t new_val, uint64_t wr_mask) 3214 { 3215 uint64_t mask = wr_mask & hvien_writable_mask; 3216 3217 if (ret_val) { 3218 *ret_val = env->hvien; 3219 } 3220 3221 env->hvien = (env->hvien & ~mask) | (new_val & mask); 3222 3223 return RISCV_EXCP_NONE; 3224 } 3225 3226 static RISCVException rmw_hvien(CPURISCVState *env, int csrno, 3227 target_ulong *ret_val, 3228 target_ulong new_val, target_ulong wr_mask) 3229 { 3230 uint64_t rval; 3231 RISCVException ret; 3232 3233 ret = rmw_hvien64(env, csrno, &rval, new_val, wr_mask); 3234 if (ret_val) { 3235 *ret_val = rval; 3236 } 3237 3238 return ret; 3239 } 3240 3241 static RISCVException rmw_hvienh(CPURISCVState *env, int csrno, 3242 target_ulong *ret_val, 3243 target_ulong new_val, target_ulong wr_mask) 3244 { 3245 uint64_t rval; 3246 RISCVException ret; 3247 3248 ret = rmw_hvien64(env, csrno, &rval, 3249 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 3250 if (ret_val) { 3251 *ret_val = rval >> 32; 3252 } 3253 3254 return ret; 3255 } 3256 3257 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 3258 uint64_t *ret_val, 3259 uint64_t new_val, uint64_t wr_mask) 3260 { 3261 uint64_t mask = wr_mask & vs_delegable_ints; 3262 3263 if (ret_val) { 3264 *ret_val = env->hideleg & vs_delegable_ints; 3265 } 3266 3267 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 3268 return RISCV_EXCP_NONE; 3269 } 3270 3271 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 3272 target_ulong *ret_val, 3273 target_ulong new_val, target_ulong wr_mask) 3274 { 3275 uint64_t rval; 3276 RISCVException ret; 3277 3278 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 3279 if (ret_val) { 3280 *ret_val = rval; 3281 } 3282 3283 return ret; 3284 } 3285 3286 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 3287 target_ulong *ret_val, 3288 target_ulong new_val, target_ulong wr_mask) 3289 { 3290 uint64_t rval; 3291 RISCVException ret; 3292 3293 ret = rmw_hideleg64(env, csrno, &rval, 3294 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 3295 if (ret_val) { 3296 *ret_val = rval >> 32; 3297 } 3298 3299 return ret; 3300 } 3301 3302 /* 3303 * The function is written for two use-cases: 3304 * 1- To access hvip csr as is for HS-mode access. 3305 * 2- To access vsip as a combination of hvip, and mip for vs-mode. 3306 * 3307 * Both report bits 2, 6, 10 and 13:63. 3308 * vsip needs to be read-only zero when both hideleg[i] and 3309 * hvien[i] are zero. 3310 */ 3311 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 3312 uint64_t *ret_val, 3313 uint64_t new_val, uint64_t wr_mask) 3314 { 3315 RISCVException ret; 3316 uint64_t old_hvip; 3317 uint64_t ret_mip; 3318 3319 /* 3320 * For bits 10, 6 and 2, vsip[i] is an alias of hip[i]. These bits are 3321 * present in hip, hvip and mip. Where mip[i] is alias of hip[i] and hvip[i] 3322 * is OR'ed in hip[i] to inject virtual interrupts from hypervisor. These 3323 * bits are actually being maintained in mip so we read them from there. 3324 * This way we have a single source of truth and allows for easier 3325 * implementation. 3326 * 3327 * For bits 13:63 we have: 3328 * 3329 * hideleg[i] hvien[i] 3330 * 0 0 No delegation. vsip[i] readonly zero. 3331 * 0 1 vsip[i] is alias of hvip[i], sip bypassed. 3332 * 1 X vsip[i] is alias of sip[i], hvip bypassed. 3333 * 3334 * alias_mask denotes the bits that come from sip (mip here given we 3335 * maintain all bits there). nalias_mask denotes bits that come from 3336 * hvip. 3337 */ 3338 uint64_t alias_mask = (env->hideleg | ~env->hvien) | VS_MODE_INTERRUPTS; 3339 uint64_t nalias_mask = (~env->hideleg & env->hvien); 3340 uint64_t wr_mask_hvip; 3341 uint64_t wr_mask_mip; 3342 3343 /* 3344 * Both alias and non-alias mask remain same for vsip except: 3345 * 1- For VS* bits if they are zero in hideleg. 3346 * 2- For 13:63 bits if they are zero in both hideleg and hvien. 3347 */ 3348 if (csrno == CSR_VSIP) { 3349 /* zero-out VS* bits that are not delegated to VS mode. */ 3350 alias_mask &= (env->hideleg | ~VS_MODE_INTERRUPTS); 3351 3352 /* 3353 * zero-out 13:63 bits that are zero in both hideleg and hvien. 3354 * nalias_mask mask can not contain any VS* bits so only second 3355 * condition applies on it. 3356 */ 3357 nalias_mask &= (env->hideleg | env->hvien); 3358 alias_mask &= (env->hideleg | env->hvien); 3359 } 3360 3361 wr_mask_hvip = wr_mask & nalias_mask & hvip_writable_mask; 3362 wr_mask_mip = wr_mask & alias_mask & hvip_writable_mask; 3363 3364 /* Aliased bits, bits 10, 6, 2 need to come from mip. */ 3365 ret = rmw_mip64(env, csrno, &ret_mip, new_val, wr_mask_mip); 3366 if (ret != RISCV_EXCP_NONE) { 3367 return ret; 3368 } 3369 3370 old_hvip = env->hvip; 3371 3372 if (wr_mask_hvip) { 3373 env->hvip = (env->hvip & ~wr_mask_hvip) | (new_val & wr_mask_hvip); 3374 3375 /* 3376 * Given hvip is separate source from mip, we need to trigger interrupt 3377 * from here separately. Normally this happen from riscv_cpu_update_mip. 3378 */ 3379 riscv_cpu_interrupt(env); 3380 } 3381 3382 if (ret_val) { 3383 /* Only take VS* bits from mip. */ 3384 ret_mip &= alias_mask; 3385 3386 /* Take in non-delegated 13:63 bits from hvip. */ 3387 old_hvip &= nalias_mask; 3388 3389 *ret_val = ret_mip | old_hvip; 3390 } 3391 3392 return ret; 3393 } 3394 3395 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 3396 target_ulong *ret_val, 3397 target_ulong new_val, target_ulong wr_mask) 3398 { 3399 uint64_t rval; 3400 RISCVException ret; 3401 3402 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 3403 if (ret_val) { 3404 *ret_val = rval; 3405 } 3406 3407 return ret; 3408 } 3409 3410 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 3411 target_ulong *ret_val, 3412 target_ulong new_val, target_ulong wr_mask) 3413 { 3414 uint64_t rval; 3415 RISCVException ret; 3416 3417 ret = rmw_hvip64(env, csrno, &rval, 3418 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 3419 if (ret_val) { 3420 *ret_val = rval >> 32; 3421 } 3422 3423 return ret; 3424 } 3425 3426 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 3427 target_ulong *ret_value, 3428 target_ulong new_value, target_ulong write_mask) 3429 { 3430 int ret = rmw_mip(env, csrno, ret_value, new_value, 3431 write_mask & hip_writable_mask); 3432 3433 if (ret_value) { 3434 *ret_value &= HS_MODE_INTERRUPTS; 3435 } 3436 return ret; 3437 } 3438 3439 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 3440 target_ulong *ret_val, 3441 target_ulong new_val, target_ulong wr_mask) 3442 { 3443 uint64_t rval; 3444 RISCVException ret; 3445 3446 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 3447 if (ret_val) { 3448 *ret_val = rval & HS_MODE_INTERRUPTS; 3449 } 3450 3451 return ret; 3452 } 3453 3454 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 3455 target_ulong *val) 3456 { 3457 *val = env->hcounteren; 3458 return RISCV_EXCP_NONE; 3459 } 3460 3461 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 3462 target_ulong val) 3463 { 3464 env->hcounteren = val; 3465 return RISCV_EXCP_NONE; 3466 } 3467 3468 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 3469 target_ulong *val) 3470 { 3471 if (val) { 3472 *val = env->hgeie; 3473 } 3474 return RISCV_EXCP_NONE; 3475 } 3476 3477 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 3478 target_ulong val) 3479 { 3480 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 3481 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 3482 env->hgeie = val; 3483 /* Update mip.SGEIP bit */ 3484 riscv_cpu_update_mip(env, MIP_SGEIP, 3485 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 3486 return RISCV_EXCP_NONE; 3487 } 3488 3489 static RISCVException read_htval(CPURISCVState *env, int csrno, 3490 target_ulong *val) 3491 { 3492 *val = env->htval; 3493 return RISCV_EXCP_NONE; 3494 } 3495 3496 static RISCVException write_htval(CPURISCVState *env, int csrno, 3497 target_ulong val) 3498 { 3499 env->htval = val; 3500 return RISCV_EXCP_NONE; 3501 } 3502 3503 static RISCVException read_htinst(CPURISCVState *env, int csrno, 3504 target_ulong *val) 3505 { 3506 *val = env->htinst; 3507 return RISCV_EXCP_NONE; 3508 } 3509 3510 static RISCVException write_htinst(CPURISCVState *env, int csrno, 3511 target_ulong val) 3512 { 3513 return RISCV_EXCP_NONE; 3514 } 3515 3516 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 3517 target_ulong *val) 3518 { 3519 if (val) { 3520 *val = env->hgeip; 3521 } 3522 return RISCV_EXCP_NONE; 3523 } 3524 3525 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 3526 target_ulong *val) 3527 { 3528 *val = env->hgatp; 3529 return RISCV_EXCP_NONE; 3530 } 3531 3532 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 3533 target_ulong val) 3534 { 3535 env->hgatp = val; 3536 return RISCV_EXCP_NONE; 3537 } 3538 3539 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 3540 target_ulong *val) 3541 { 3542 if (!env->rdtime_fn) { 3543 return RISCV_EXCP_ILLEGAL_INST; 3544 } 3545 3546 *val = env->htimedelta; 3547 return RISCV_EXCP_NONE; 3548 } 3549 3550 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 3551 target_ulong val) 3552 { 3553 if (!env->rdtime_fn) { 3554 return RISCV_EXCP_ILLEGAL_INST; 3555 } 3556 3557 if (riscv_cpu_mxl(env) == MXL_RV32) { 3558 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 3559 } else { 3560 env->htimedelta = val; 3561 } 3562 3563 if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { 3564 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 3565 env->htimedelta, MIP_VSTIP); 3566 } 3567 3568 return RISCV_EXCP_NONE; 3569 } 3570 3571 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 3572 target_ulong *val) 3573 { 3574 if (!env->rdtime_fn) { 3575 return RISCV_EXCP_ILLEGAL_INST; 3576 } 3577 3578 *val = env->htimedelta >> 32; 3579 return RISCV_EXCP_NONE; 3580 } 3581 3582 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 3583 target_ulong val) 3584 { 3585 if (!env->rdtime_fn) { 3586 return RISCV_EXCP_ILLEGAL_INST; 3587 } 3588 3589 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 3590 3591 if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { 3592 riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, 3593 env->htimedelta, MIP_VSTIP); 3594 } 3595 3596 return RISCV_EXCP_NONE; 3597 } 3598 3599 static RISCVException read_hvictl(CPURISCVState *env, int csrno, 3600 target_ulong *val) 3601 { 3602 *val = env->hvictl; 3603 return RISCV_EXCP_NONE; 3604 } 3605 3606 static RISCVException write_hvictl(CPURISCVState *env, int csrno, 3607 target_ulong val) 3608 { 3609 env->hvictl = val & HVICTL_VALID_MASK; 3610 return RISCV_EXCP_NONE; 3611 } 3612 3613 static RISCVException read_hvipriox(CPURISCVState *env, int first_index, 3614 uint8_t *iprio, target_ulong *val) 3615 { 3616 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 3617 3618 /* First index has to be a multiple of number of irqs per register */ 3619 if (first_index % num_irqs) { 3620 return (env->virt_enabled) ? 3621 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 3622 } 3623 3624 /* Fill-up return value */ 3625 *val = 0; 3626 for (i = 0; i < num_irqs; i++) { 3627 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 3628 continue; 3629 } 3630 if (rdzero) { 3631 continue; 3632 } 3633 *val |= ((target_ulong)iprio[irq]) << (i * 8); 3634 } 3635 3636 return RISCV_EXCP_NONE; 3637 } 3638 3639 static RISCVException write_hvipriox(CPURISCVState *env, int first_index, 3640 uint8_t *iprio, target_ulong val) 3641 { 3642 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 3643 3644 /* First index has to be a multiple of number of irqs per register */ 3645 if (first_index % num_irqs) { 3646 return (env->virt_enabled) ? 3647 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 3648 } 3649 3650 /* Fill-up priority array */ 3651 for (i = 0; i < num_irqs; i++) { 3652 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 3653 continue; 3654 } 3655 if (rdzero) { 3656 iprio[irq] = 0; 3657 } else { 3658 iprio[irq] = (val >> (i * 8)) & 0xff; 3659 } 3660 } 3661 3662 return RISCV_EXCP_NONE; 3663 } 3664 3665 static RISCVException read_hviprio1(CPURISCVState *env, int csrno, 3666 target_ulong *val) 3667 { 3668 return read_hvipriox(env, 0, env->hviprio, val); 3669 } 3670 3671 static RISCVException write_hviprio1(CPURISCVState *env, int csrno, 3672 target_ulong val) 3673 { 3674 return write_hvipriox(env, 0, env->hviprio, val); 3675 } 3676 3677 static RISCVException read_hviprio1h(CPURISCVState *env, int csrno, 3678 target_ulong *val) 3679 { 3680 return read_hvipriox(env, 4, env->hviprio, val); 3681 } 3682 3683 static RISCVException write_hviprio1h(CPURISCVState *env, int csrno, 3684 target_ulong val) 3685 { 3686 return write_hvipriox(env, 4, env->hviprio, val); 3687 } 3688 3689 static RISCVException read_hviprio2(CPURISCVState *env, int csrno, 3690 target_ulong *val) 3691 { 3692 return read_hvipriox(env, 8, env->hviprio, val); 3693 } 3694 3695 static RISCVException write_hviprio2(CPURISCVState *env, int csrno, 3696 target_ulong val) 3697 { 3698 return write_hvipriox(env, 8, env->hviprio, val); 3699 } 3700 3701 static RISCVException read_hviprio2h(CPURISCVState *env, int csrno, 3702 target_ulong *val) 3703 { 3704 return read_hvipriox(env, 12, env->hviprio, val); 3705 } 3706 3707 static RISCVException write_hviprio2h(CPURISCVState *env, int csrno, 3708 target_ulong val) 3709 { 3710 return write_hvipriox(env, 12, env->hviprio, val); 3711 } 3712 3713 /* Virtual CSR Registers */ 3714 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 3715 target_ulong *val) 3716 { 3717 *val = env->vsstatus; 3718 return RISCV_EXCP_NONE; 3719 } 3720 3721 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 3722 target_ulong val) 3723 { 3724 uint64_t mask = (target_ulong)-1; 3725 if ((val & VSSTATUS64_UXL) == 0) { 3726 mask &= ~VSSTATUS64_UXL; 3727 } 3728 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 3729 return RISCV_EXCP_NONE; 3730 } 3731 3732 static RISCVException read_vstvec(CPURISCVState *env, int csrno, 3733 target_ulong *val) 3734 { 3735 *val = env->vstvec; 3736 return RISCV_EXCP_NONE; 3737 } 3738 3739 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 3740 target_ulong val) 3741 { 3742 env->vstvec = val; 3743 return RISCV_EXCP_NONE; 3744 } 3745 3746 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 3747 target_ulong *val) 3748 { 3749 *val = env->vsscratch; 3750 return RISCV_EXCP_NONE; 3751 } 3752 3753 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 3754 target_ulong val) 3755 { 3756 env->vsscratch = val; 3757 return RISCV_EXCP_NONE; 3758 } 3759 3760 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 3761 target_ulong *val) 3762 { 3763 *val = env->vsepc; 3764 return RISCV_EXCP_NONE; 3765 } 3766 3767 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 3768 target_ulong val) 3769 { 3770 env->vsepc = val; 3771 return RISCV_EXCP_NONE; 3772 } 3773 3774 static RISCVException read_vscause(CPURISCVState *env, int csrno, 3775 target_ulong *val) 3776 { 3777 *val = env->vscause; 3778 return RISCV_EXCP_NONE; 3779 } 3780 3781 static RISCVException write_vscause(CPURISCVState *env, int csrno, 3782 target_ulong val) 3783 { 3784 env->vscause = val; 3785 return RISCV_EXCP_NONE; 3786 } 3787 3788 static RISCVException read_vstval(CPURISCVState *env, int csrno, 3789 target_ulong *val) 3790 { 3791 *val = env->vstval; 3792 return RISCV_EXCP_NONE; 3793 } 3794 3795 static RISCVException write_vstval(CPURISCVState *env, int csrno, 3796 target_ulong val) 3797 { 3798 env->vstval = val; 3799 return RISCV_EXCP_NONE; 3800 } 3801 3802 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 3803 target_ulong *val) 3804 { 3805 *val = env->vsatp; 3806 return RISCV_EXCP_NONE; 3807 } 3808 3809 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 3810 target_ulong val) 3811 { 3812 env->vsatp = val; 3813 return RISCV_EXCP_NONE; 3814 } 3815 3816 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 3817 target_ulong *val) 3818 { 3819 *val = env->mtval2; 3820 return RISCV_EXCP_NONE; 3821 } 3822 3823 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 3824 target_ulong val) 3825 { 3826 env->mtval2 = val; 3827 return RISCV_EXCP_NONE; 3828 } 3829 3830 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 3831 target_ulong *val) 3832 { 3833 *val = env->mtinst; 3834 return RISCV_EXCP_NONE; 3835 } 3836 3837 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 3838 target_ulong val) 3839 { 3840 env->mtinst = val; 3841 return RISCV_EXCP_NONE; 3842 } 3843 3844 /* Physical Memory Protection */ 3845 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 3846 target_ulong *val) 3847 { 3848 *val = mseccfg_csr_read(env); 3849 return RISCV_EXCP_NONE; 3850 } 3851 3852 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 3853 target_ulong val) 3854 { 3855 mseccfg_csr_write(env, val); 3856 return RISCV_EXCP_NONE; 3857 } 3858 3859 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 3860 target_ulong *val) 3861 { 3862 uint32_t reg_index = csrno - CSR_PMPCFG0; 3863 3864 *val = pmpcfg_csr_read(env, reg_index); 3865 return RISCV_EXCP_NONE; 3866 } 3867 3868 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 3869 target_ulong val) 3870 { 3871 uint32_t reg_index = csrno - CSR_PMPCFG0; 3872 3873 pmpcfg_csr_write(env, reg_index, val); 3874 return RISCV_EXCP_NONE; 3875 } 3876 3877 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 3878 target_ulong *val) 3879 { 3880 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 3881 return RISCV_EXCP_NONE; 3882 } 3883 3884 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 3885 target_ulong val) 3886 { 3887 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 3888 return RISCV_EXCP_NONE; 3889 } 3890 3891 static RISCVException read_tselect(CPURISCVState *env, int csrno, 3892 target_ulong *val) 3893 { 3894 *val = tselect_csr_read(env); 3895 return RISCV_EXCP_NONE; 3896 } 3897 3898 static RISCVException write_tselect(CPURISCVState *env, int csrno, 3899 target_ulong val) 3900 { 3901 tselect_csr_write(env, val); 3902 return RISCV_EXCP_NONE; 3903 } 3904 3905 static RISCVException read_tdata(CPURISCVState *env, int csrno, 3906 target_ulong *val) 3907 { 3908 /* return 0 in tdata1 to end the trigger enumeration */ 3909 if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) { 3910 *val = 0; 3911 return RISCV_EXCP_NONE; 3912 } 3913 3914 if (!tdata_available(env, csrno - CSR_TDATA1)) { 3915 return RISCV_EXCP_ILLEGAL_INST; 3916 } 3917 3918 *val = tdata_csr_read(env, csrno - CSR_TDATA1); 3919 return RISCV_EXCP_NONE; 3920 } 3921 3922 static RISCVException write_tdata(CPURISCVState *env, int csrno, 3923 target_ulong val) 3924 { 3925 if (!tdata_available(env, csrno - CSR_TDATA1)) { 3926 return RISCV_EXCP_ILLEGAL_INST; 3927 } 3928 3929 tdata_csr_write(env, csrno - CSR_TDATA1, val); 3930 return RISCV_EXCP_NONE; 3931 } 3932 3933 static RISCVException read_tinfo(CPURISCVState *env, int csrno, 3934 target_ulong *val) 3935 { 3936 *val = tinfo_csr_read(env); 3937 return RISCV_EXCP_NONE; 3938 } 3939 3940 static RISCVException read_mcontext(CPURISCVState *env, int csrno, 3941 target_ulong *val) 3942 { 3943 *val = env->mcontext; 3944 return RISCV_EXCP_NONE; 3945 } 3946 3947 static RISCVException write_mcontext(CPURISCVState *env, int csrno, 3948 target_ulong val) 3949 { 3950 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; 3951 int32_t mask; 3952 3953 if (riscv_has_ext(env, RVH)) { 3954 /* Spec suggest 7-bit for RV32 and 14-bit for RV64 w/ H extension */ 3955 mask = rv32 ? MCONTEXT32_HCONTEXT : MCONTEXT64_HCONTEXT; 3956 } else { 3957 /* Spec suggest 6-bit for RV32 and 13-bit for RV64 w/o H extension */ 3958 mask = rv32 ? MCONTEXT32 : MCONTEXT64; 3959 } 3960 3961 env->mcontext = val & mask; 3962 return RISCV_EXCP_NONE; 3963 } 3964 3965 /* 3966 * Functions to access Pointer Masking feature registers 3967 * We have to check if current priv lvl could modify 3968 * csr in given mode 3969 */ 3970 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 3971 { 3972 int csr_priv = get_field(csrno, 0x300); 3973 int pm_current; 3974 3975 if (env->debugger) { 3976 return false; 3977 } 3978 /* 3979 * If priv lvls differ that means we're accessing csr from higher priv lvl, 3980 * so allow the access 3981 */ 3982 if (env->priv != csr_priv) { 3983 return false; 3984 } 3985 switch (env->priv) { 3986 case PRV_M: 3987 pm_current = get_field(env->mmte, M_PM_CURRENT); 3988 break; 3989 case PRV_S: 3990 pm_current = get_field(env->mmte, S_PM_CURRENT); 3991 break; 3992 case PRV_U: 3993 pm_current = get_field(env->mmte, U_PM_CURRENT); 3994 break; 3995 default: 3996 g_assert_not_reached(); 3997 } 3998 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 3999 return !pm_current; 4000 } 4001 4002 static RISCVException read_mmte(CPURISCVState *env, int csrno, 4003 target_ulong *val) 4004 { 4005 *val = env->mmte & MMTE_MASK; 4006 return RISCV_EXCP_NONE; 4007 } 4008 4009 static RISCVException write_mmte(CPURISCVState *env, int csrno, 4010 target_ulong val) 4011 { 4012 uint64_t mstatus; 4013 target_ulong wpri_val = val & MMTE_MASK; 4014 4015 if (val != wpri_val) { 4016 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" 4017 TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x", 4018 val, "vs expected 0x", wpri_val); 4019 } 4020 /* for machine mode pm.current is hardwired to 1 */ 4021 wpri_val |= MMTE_M_PM_CURRENT; 4022 4023 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 4024 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 4025 env->mmte = wpri_val | EXT_STATUS_DIRTY; 4026 riscv_cpu_update_mask(env); 4027 4028 /* Set XS and SD bits, since PM CSRs are dirty */ 4029 mstatus = env->mstatus | MSTATUS_XS; 4030 write_mstatus(env, csrno, mstatus); 4031 return RISCV_EXCP_NONE; 4032 } 4033 4034 static RISCVException read_smte(CPURISCVState *env, int csrno, 4035 target_ulong *val) 4036 { 4037 *val = env->mmte & SMTE_MASK; 4038 return RISCV_EXCP_NONE; 4039 } 4040 4041 static RISCVException write_smte(CPURISCVState *env, int csrno, 4042 target_ulong val) 4043 { 4044 target_ulong wpri_val = val & SMTE_MASK; 4045 4046 if (val != wpri_val) { 4047 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" 4048 TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x", 4049 val, "vs expected 0x", wpri_val); 4050 } 4051 4052 /* if pm.current==0 we can't modify current PM CSRs */ 4053 if (check_pm_current_disabled(env, csrno)) { 4054 return RISCV_EXCP_NONE; 4055 } 4056 4057 wpri_val |= (env->mmte & ~SMTE_MASK); 4058 write_mmte(env, csrno, wpri_val); 4059 return RISCV_EXCP_NONE; 4060 } 4061 4062 static RISCVException read_umte(CPURISCVState *env, int csrno, 4063 target_ulong *val) 4064 { 4065 *val = env->mmte & UMTE_MASK; 4066 return RISCV_EXCP_NONE; 4067 } 4068 4069 static RISCVException write_umte(CPURISCVState *env, int csrno, 4070 target_ulong val) 4071 { 4072 target_ulong wpri_val = val & UMTE_MASK; 4073 4074 if (val != wpri_val) { 4075 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" 4076 TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x", 4077 val, "vs expected 0x", wpri_val); 4078 } 4079 4080 if (check_pm_current_disabled(env, csrno)) { 4081 return RISCV_EXCP_NONE; 4082 } 4083 4084 wpri_val |= (env->mmte & ~UMTE_MASK); 4085 write_mmte(env, csrno, wpri_val); 4086 return RISCV_EXCP_NONE; 4087 } 4088 4089 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 4090 target_ulong *val) 4091 { 4092 *val = env->mpmmask; 4093 return RISCV_EXCP_NONE; 4094 } 4095 4096 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 4097 target_ulong val) 4098 { 4099 uint64_t mstatus; 4100 4101 env->mpmmask = val; 4102 if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { 4103 env->cur_pmmask = val; 4104 } 4105 env->mmte |= EXT_STATUS_DIRTY; 4106 4107 /* Set XS and SD bits, since PM CSRs are dirty */ 4108 mstatus = env->mstatus | MSTATUS_XS; 4109 write_mstatus(env, csrno, mstatus); 4110 return RISCV_EXCP_NONE; 4111 } 4112 4113 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 4114 target_ulong *val) 4115 { 4116 *val = env->spmmask; 4117 return RISCV_EXCP_NONE; 4118 } 4119 4120 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 4121 target_ulong val) 4122 { 4123 uint64_t mstatus; 4124 4125 /* if pm.current==0 we can't modify current PM CSRs */ 4126 if (check_pm_current_disabled(env, csrno)) { 4127 return RISCV_EXCP_NONE; 4128 } 4129 env->spmmask = val; 4130 if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { 4131 env->cur_pmmask = val; 4132 if (cpu_get_xl(env, PRV_S) == MXL_RV32) { 4133 env->cur_pmmask &= UINT32_MAX; 4134 } 4135 } 4136 env->mmte |= EXT_STATUS_DIRTY; 4137 4138 /* Set XS and SD bits, since PM CSRs are dirty */ 4139 mstatus = env->mstatus | MSTATUS_XS; 4140 write_mstatus(env, csrno, mstatus); 4141 return RISCV_EXCP_NONE; 4142 } 4143 4144 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 4145 target_ulong *val) 4146 { 4147 *val = env->upmmask; 4148 return RISCV_EXCP_NONE; 4149 } 4150 4151 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 4152 target_ulong val) 4153 { 4154 uint64_t mstatus; 4155 4156 /* if pm.current==0 we can't modify current PM CSRs */ 4157 if (check_pm_current_disabled(env, csrno)) { 4158 return RISCV_EXCP_NONE; 4159 } 4160 env->upmmask = val; 4161 if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { 4162 env->cur_pmmask = val; 4163 if (cpu_get_xl(env, PRV_U) == MXL_RV32) { 4164 env->cur_pmmask &= UINT32_MAX; 4165 } 4166 } 4167 env->mmte |= EXT_STATUS_DIRTY; 4168 4169 /* Set XS and SD bits, since PM CSRs are dirty */ 4170 mstatus = env->mstatus | MSTATUS_XS; 4171 write_mstatus(env, csrno, mstatus); 4172 return RISCV_EXCP_NONE; 4173 } 4174 4175 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 4176 target_ulong *val) 4177 { 4178 *val = env->mpmbase; 4179 return RISCV_EXCP_NONE; 4180 } 4181 4182 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 4183 target_ulong val) 4184 { 4185 uint64_t mstatus; 4186 4187 env->mpmbase = val; 4188 if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { 4189 env->cur_pmbase = val; 4190 } 4191 env->mmte |= EXT_STATUS_DIRTY; 4192 4193 /* Set XS and SD bits, since PM CSRs are dirty */ 4194 mstatus = env->mstatus | MSTATUS_XS; 4195 write_mstatus(env, csrno, mstatus); 4196 return RISCV_EXCP_NONE; 4197 } 4198 4199 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 4200 target_ulong *val) 4201 { 4202 *val = env->spmbase; 4203 return RISCV_EXCP_NONE; 4204 } 4205 4206 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 4207 target_ulong val) 4208 { 4209 uint64_t mstatus; 4210 4211 /* if pm.current==0 we can't modify current PM CSRs */ 4212 if (check_pm_current_disabled(env, csrno)) { 4213 return RISCV_EXCP_NONE; 4214 } 4215 env->spmbase = val; 4216 if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { 4217 env->cur_pmbase = val; 4218 if (cpu_get_xl(env, PRV_S) == MXL_RV32) { 4219 env->cur_pmbase &= UINT32_MAX; 4220 } 4221 } 4222 env->mmte |= EXT_STATUS_DIRTY; 4223 4224 /* Set XS and SD bits, since PM CSRs are dirty */ 4225 mstatus = env->mstatus | MSTATUS_XS; 4226 write_mstatus(env, csrno, mstatus); 4227 return RISCV_EXCP_NONE; 4228 } 4229 4230 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 4231 target_ulong *val) 4232 { 4233 *val = env->upmbase; 4234 return RISCV_EXCP_NONE; 4235 } 4236 4237 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 4238 target_ulong val) 4239 { 4240 uint64_t mstatus; 4241 4242 /* if pm.current==0 we can't modify current PM CSRs */ 4243 if (check_pm_current_disabled(env, csrno)) { 4244 return RISCV_EXCP_NONE; 4245 } 4246 env->upmbase = val; 4247 if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { 4248 env->cur_pmbase = val; 4249 if (cpu_get_xl(env, PRV_U) == MXL_RV32) { 4250 env->cur_pmbase &= UINT32_MAX; 4251 } 4252 } 4253 env->mmte |= EXT_STATUS_DIRTY; 4254 4255 /* Set XS and SD bits, since PM CSRs are dirty */ 4256 mstatus = env->mstatus | MSTATUS_XS; 4257 write_mstatus(env, csrno, mstatus); 4258 return RISCV_EXCP_NONE; 4259 } 4260 4261 #endif 4262 4263 /* Crypto Extension */ 4264 static RISCVException rmw_seed(CPURISCVState *env, int csrno, 4265 target_ulong *ret_value, 4266 target_ulong new_value, 4267 target_ulong write_mask) 4268 { 4269 uint16_t random_v; 4270 Error *random_e = NULL; 4271 int random_r; 4272 target_ulong rval; 4273 4274 random_r = qemu_guest_getrandom(&random_v, 2, &random_e); 4275 if (unlikely(random_r < 0)) { 4276 /* 4277 * Failed, for unknown reasons in the crypto subsystem. 4278 * The best we can do is log the reason and return a 4279 * failure indication to the guest. There is no reason 4280 * we know to expect the failure to be transitory, so 4281 * indicate DEAD to avoid having the guest spin on WAIT. 4282 */ 4283 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", 4284 __func__, error_get_pretty(random_e)); 4285 error_free(random_e); 4286 rval = SEED_OPST_DEAD; 4287 } else { 4288 rval = random_v | SEED_OPST_ES16; 4289 } 4290 4291 if (ret_value) { 4292 *ret_value = rval; 4293 } 4294 4295 return RISCV_EXCP_NONE; 4296 } 4297 4298 /* 4299 * riscv_csrrw - read and/or update control and status register 4300 * 4301 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 4302 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 4303 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 4304 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 4305 */ 4306 4307 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 4308 int csrno, 4309 bool write_mask) 4310 { 4311 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 4312 bool read_only = get_field(csrno, 0xC00) == 3; 4313 int csr_min_priv = csr_ops[csrno].min_priv_ver; 4314 4315 /* ensure the CSR extension is enabled */ 4316 if (!riscv_cpu_cfg(env)->ext_zicsr) { 4317 return RISCV_EXCP_ILLEGAL_INST; 4318 } 4319 4320 /* ensure CSR is implemented by checking predicate */ 4321 if (!csr_ops[csrno].predicate) { 4322 return RISCV_EXCP_ILLEGAL_INST; 4323 } 4324 4325 /* privileged spec version check */ 4326 if (env->priv_ver < csr_min_priv) { 4327 return RISCV_EXCP_ILLEGAL_INST; 4328 } 4329 4330 /* read / write check */ 4331 if (write_mask && read_only) { 4332 return RISCV_EXCP_ILLEGAL_INST; 4333 } 4334 4335 /* 4336 * The predicate() not only does existence check but also does some 4337 * access control check which triggers for example virtual instruction 4338 * exception in some cases. When writing read-only CSRs in those cases 4339 * illegal instruction exception should be triggered instead of virtual 4340 * instruction exception. Hence this comes after the read / write check. 4341 */ 4342 RISCVException ret = csr_ops[csrno].predicate(env, csrno); 4343 if (ret != RISCV_EXCP_NONE) { 4344 return ret; 4345 } 4346 4347 #if !defined(CONFIG_USER_ONLY) 4348 int csr_priv, effective_priv = env->priv; 4349 4350 if (riscv_has_ext(env, RVH) && env->priv == PRV_S && 4351 !env->virt_enabled) { 4352 /* 4353 * We are in HS mode. Add 1 to the effective privilege level to 4354 * allow us to access the Hypervisor CSRs. 4355 */ 4356 effective_priv++; 4357 } 4358 4359 csr_priv = get_field(csrno, 0x300); 4360 if (!env->debugger && (effective_priv < csr_priv)) { 4361 if (csr_priv == (PRV_S + 1) && env->virt_enabled) { 4362 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 4363 } 4364 return RISCV_EXCP_ILLEGAL_INST; 4365 } 4366 #endif 4367 return RISCV_EXCP_NONE; 4368 } 4369 4370 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 4371 target_ulong *ret_value, 4372 target_ulong new_value, 4373 target_ulong write_mask) 4374 { 4375 RISCVException ret; 4376 target_ulong old_value = 0; 4377 4378 /* execute combined read/write operation if it exists */ 4379 if (csr_ops[csrno].op) { 4380 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 4381 } 4382 4383 /* 4384 * ret_value == NULL means that rd=x0 and we're coming from helper_csrw() 4385 * and we can't throw side effects caused by CSR reads. 4386 */ 4387 if (ret_value) { 4388 /* if no accessor exists then return failure */ 4389 if (!csr_ops[csrno].read) { 4390 return RISCV_EXCP_ILLEGAL_INST; 4391 } 4392 /* read old value */ 4393 ret = csr_ops[csrno].read(env, csrno, &old_value); 4394 if (ret != RISCV_EXCP_NONE) { 4395 return ret; 4396 } 4397 } 4398 4399 /* write value if writable and write mask set, otherwise drop writes */ 4400 if (write_mask) { 4401 new_value = (old_value & ~write_mask) | (new_value & write_mask); 4402 if (csr_ops[csrno].write) { 4403 ret = csr_ops[csrno].write(env, csrno, new_value); 4404 if (ret != RISCV_EXCP_NONE) { 4405 return ret; 4406 } 4407 } 4408 } 4409 4410 /* return old value */ 4411 if (ret_value) { 4412 *ret_value = old_value; 4413 } 4414 4415 return RISCV_EXCP_NONE; 4416 } 4417 4418 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 4419 target_ulong *ret_value, 4420 target_ulong new_value, target_ulong write_mask) 4421 { 4422 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask); 4423 if (ret != RISCV_EXCP_NONE) { 4424 return ret; 4425 } 4426 4427 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 4428 } 4429 4430 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 4431 Int128 *ret_value, 4432 Int128 new_value, 4433 Int128 write_mask) 4434 { 4435 RISCVException ret; 4436 Int128 old_value; 4437 4438 /* read old value */ 4439 ret = csr_ops[csrno].read128(env, csrno, &old_value); 4440 if (ret != RISCV_EXCP_NONE) { 4441 return ret; 4442 } 4443 4444 /* write value if writable and write mask set, otherwise drop writes */ 4445 if (int128_nz(write_mask)) { 4446 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 4447 int128_and(new_value, write_mask)); 4448 if (csr_ops[csrno].write128) { 4449 ret = csr_ops[csrno].write128(env, csrno, new_value); 4450 if (ret != RISCV_EXCP_NONE) { 4451 return ret; 4452 } 4453 } else if (csr_ops[csrno].write) { 4454 /* avoids having to write wrappers for all registers */ 4455 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 4456 if (ret != RISCV_EXCP_NONE) { 4457 return ret; 4458 } 4459 } 4460 } 4461 4462 /* return old value */ 4463 if (ret_value) { 4464 *ret_value = old_value; 4465 } 4466 4467 return RISCV_EXCP_NONE; 4468 } 4469 4470 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 4471 Int128 *ret_value, 4472 Int128 new_value, Int128 write_mask) 4473 { 4474 RISCVException ret; 4475 4476 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask)); 4477 if (ret != RISCV_EXCP_NONE) { 4478 return ret; 4479 } 4480 4481 if (csr_ops[csrno].read128) { 4482 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 4483 } 4484 4485 /* 4486 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 4487 * at all defined. 4488 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 4489 * significant), for those, this fallback is correctly handling the 4490 * accesses 4491 */ 4492 target_ulong old_value; 4493 ret = riscv_csrrw_do64(env, csrno, &old_value, 4494 int128_getlo(new_value), 4495 int128_getlo(write_mask)); 4496 if (ret == RISCV_EXCP_NONE && ret_value) { 4497 *ret_value = int128_make64(old_value); 4498 } 4499 return ret; 4500 } 4501 4502 /* 4503 * Debugger support. If not in user mode, set env->debugger before the 4504 * riscv_csrrw call and clear it after the call. 4505 */ 4506 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 4507 target_ulong *ret_value, 4508 target_ulong new_value, 4509 target_ulong write_mask) 4510 { 4511 RISCVException ret; 4512 #if !defined(CONFIG_USER_ONLY) 4513 env->debugger = true; 4514 #endif 4515 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 4516 #if !defined(CONFIG_USER_ONLY) 4517 env->debugger = false; 4518 #endif 4519 return ret; 4520 } 4521 4522 static RISCVException read_jvt(CPURISCVState *env, int csrno, 4523 target_ulong *val) 4524 { 4525 *val = env->jvt; 4526 return RISCV_EXCP_NONE; 4527 } 4528 4529 static RISCVException write_jvt(CPURISCVState *env, int csrno, 4530 target_ulong val) 4531 { 4532 env->jvt = val; 4533 return RISCV_EXCP_NONE; 4534 } 4535 4536 /* 4537 * Control and Status Register function table 4538 * riscv_csr_operations::predicate() must be provided for an implemented CSR 4539 */ 4540 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 4541 /* User Floating-Point CSRs */ 4542 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 4543 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 4544 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 4545 /* Vector CSRs */ 4546 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, 4547 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, 4548 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, 4549 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, 4550 [CSR_VL] = { "vl", vs, read_vl }, 4551 [CSR_VTYPE] = { "vtype", vs, read_vtype }, 4552 [CSR_VLENB] = { "vlenb", vs, read_vlenb }, 4553 /* User Timers and Counters */ 4554 [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter }, 4555 [CSR_INSTRET] = { "instret", ctr, read_hpmcounter }, 4556 [CSR_CYCLEH] = { "cycleh", ctr32, read_hpmcounterh }, 4557 [CSR_INSTRETH] = { "instreth", ctr32, read_hpmcounterh }, 4558 4559 /* 4560 * In privileged mode, the monitor will have to emulate TIME CSRs only if 4561 * rdtime callback is not provided by machine/platform emulation. 4562 */ 4563 [CSR_TIME] = { "time", ctr, read_time }, 4564 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 4565 4566 /* Crypto Extension */ 4567 [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, 4568 4569 /* Zcmt Extension */ 4570 [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt}, 4571 4572 #if !defined(CONFIG_USER_ONLY) 4573 /* Machine Timers and Counters */ 4574 [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, 4575 write_mhpmcounter }, 4576 [CSR_MINSTRET] = { "minstret", any, read_hpmcounter, 4577 write_mhpmcounter }, 4578 [CSR_MCYCLEH] = { "mcycleh", any32, read_hpmcounterh, 4579 write_mhpmcounterh }, 4580 [CSR_MINSTRETH] = { "minstreth", any32, read_hpmcounterh, 4581 write_mhpmcounterh }, 4582 4583 /* Machine Information Registers */ 4584 [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, 4585 [CSR_MARCHID] = { "marchid", any, read_marchid }, 4586 [CSR_MIMPID] = { "mimpid", any, read_mimpid }, 4587 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 4588 4589 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 4590 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4591 /* Machine Trap Setup */ 4592 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, 4593 NULL, read_mstatus_i128 }, 4594 [CSR_MISA] = { "misa", any, read_misa, write_misa, 4595 NULL, read_misa_i128 }, 4596 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 4597 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 4598 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 4599 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 4600 [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, 4601 write_mcounteren }, 4602 4603 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, 4604 write_mstatush }, 4605 4606 /* Machine Trap Handling */ 4607 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, 4608 NULL, read_mscratch_i128, write_mscratch_i128 }, 4609 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 4610 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 4611 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 4612 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 4613 4614 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 4615 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 4616 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 4617 4618 /* Machine-Level Interrupts (AIA) */ 4619 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 4620 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 4621 4622 /* Virtual Interrupts for Supervisor Level (AIA) */ 4623 [CSR_MVIEN] = { "mvien", aia_any, NULL, NULL, rmw_mvien }, 4624 [CSR_MVIP] = { "mvip", aia_any, NULL, NULL, rmw_mvip }, 4625 4626 /* Machine-Level High-Half CSRs (AIA) */ 4627 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 4628 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 4629 [CSR_MVIENH] = { "mvienh", aia_any32, NULL, NULL, rmw_mvienh }, 4630 [CSR_MVIPH] = { "mviph", aia_any32, NULL, NULL, rmw_mviph }, 4631 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 4632 4633 /* Execution environment configuration */ 4634 [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, 4635 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4636 [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, 4637 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4638 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 4639 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4640 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 4641 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4642 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 4643 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4644 4645 /* Smstateen extension CSRs */ 4646 [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0, 4647 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4648 [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, 4649 write_mstateen0h, 4650 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4651 [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen, 4652 write_mstateen_1_3, 4653 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4654 [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh, 4655 write_mstateenh_1_3, 4656 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4657 [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen, 4658 write_mstateen_1_3, 4659 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4660 [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh, 4661 write_mstateenh_1_3, 4662 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4663 [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen, 4664 write_mstateen_1_3, 4665 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4666 [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh, 4667 write_mstateenh_1_3, 4668 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4669 [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0, 4670 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4671 [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh, 4672 write_hstateen0h, 4673 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4674 [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen, 4675 write_hstateen_1_3, 4676 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4677 [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh, 4678 write_hstateenh_1_3, 4679 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4680 [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen, 4681 write_hstateen_1_3, 4682 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4683 [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh, 4684 write_hstateenh_1_3, 4685 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4686 [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen, 4687 write_hstateen_1_3, 4688 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4689 [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh, 4690 write_hstateenh_1_3, 4691 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4692 [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0, 4693 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4694 [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen, 4695 write_sstateen_1_3, 4696 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4697 [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen, 4698 write_sstateen_1_3, 4699 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4700 [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen, 4701 write_sstateen_1_3, 4702 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4703 4704 /* Supervisor Trap Setup */ 4705 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, 4706 NULL, read_sstatus_i128 }, 4707 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 4708 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 4709 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, 4710 write_scounteren }, 4711 4712 /* Supervisor Trap Handling */ 4713 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, 4714 NULL, read_sscratch_i128, write_sscratch_i128 }, 4715 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 4716 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 4717 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 4718 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 4719 [CSR_STIMECMP] = { "stimecmp", sstc, read_stimecmp, write_stimecmp, 4720 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4721 [CSR_STIMECMPH] = { "stimecmph", sstc_32, read_stimecmph, write_stimecmph, 4722 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4723 [CSR_VSTIMECMP] = { "vstimecmp", sstc, read_vstimecmp, 4724 write_vstimecmp, 4725 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4726 [CSR_VSTIMECMPH] = { "vstimecmph", sstc_32, read_vstimecmph, 4727 write_vstimecmph, 4728 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4729 4730 /* Supervisor Protection and Translation */ 4731 [CSR_SATP] = { "satp", satp, read_satp, write_satp }, 4732 4733 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 4734 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 4735 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 4736 4737 /* Supervisor-Level Interrupts (AIA) */ 4738 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 4739 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 4740 4741 /* Supervisor-Level High-Half CSRs (AIA) */ 4742 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 4743 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 4744 4745 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 4746 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4747 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 4748 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4749 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 4750 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4751 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 4752 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4753 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 4754 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4755 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 4756 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4757 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, 4758 write_hcounteren, 4759 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4760 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 4761 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4762 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 4763 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4764 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 4765 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4766 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 4767 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4768 [CSR_HGATP] = { "hgatp", hgatp, read_hgatp, write_hgatp, 4769 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4770 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, 4771 write_htimedelta, 4772 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4773 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, 4774 write_htimedeltah, 4775 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4776 4777 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, 4778 write_vsstatus, 4779 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4780 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 4781 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4782 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 4783 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4784 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 4785 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4786 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, 4787 write_vsscratch, 4788 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4789 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 4790 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4791 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 4792 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4793 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 4794 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4795 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 4796 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4797 4798 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 4799 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4800 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 4801 .min_priv_ver = PRIV_VERSION_1_12_0 }, 4802 4803 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 4804 [CSR_HVIEN] = { "hvien", aia_hmode, NULL, NULL, rmw_hvien }, 4805 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, 4806 write_hvictl }, 4807 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, 4808 write_hviprio1 }, 4809 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, 4810 write_hviprio2 }, 4811 /* 4812 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 4813 */ 4814 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, 4815 rmw_xiselect }, 4816 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 4817 4818 /* VS-Level Interrupts (H-extension with AIA) */ 4819 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 4820 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 4821 4822 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 4823 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, 4824 rmw_hidelegh }, 4825 [CSR_HVIENH] = { "hvienh", aia_hmode32, NULL, NULL, rmw_hvienh }, 4826 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 4827 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, 4828 write_hviprio1h }, 4829 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, 4830 write_hviprio2h }, 4831 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 4832 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 4833 4834 /* Physical Memory Protection */ 4835 [CSR_MSECCFG] = { "mseccfg", have_mseccfg, read_mseccfg, write_mseccfg, 4836 .min_priv_ver = PRIV_VERSION_1_11_0 }, 4837 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 4838 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 4839 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 4840 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 4841 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 4842 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 4843 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 4844 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 4845 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 4846 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 4847 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 4848 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 4849 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 4850 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 4851 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 4852 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 4853 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 4854 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 4855 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 4856 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 4857 4858 /* Debug CSRs */ 4859 [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, 4860 [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, 4861 [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, 4862 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, 4863 [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, 4864 [CSR_MCONTEXT] = { "mcontext", debug, read_mcontext, write_mcontext }, 4865 4866 /* User Pointer Masking */ 4867 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 4868 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, 4869 write_upmmask }, 4870 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, 4871 write_upmbase }, 4872 /* Machine Pointer Masking */ 4873 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 4874 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, 4875 write_mpmmask }, 4876 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, 4877 write_mpmbase }, 4878 /* Supervisor Pointer Masking */ 4879 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 4880 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, 4881 write_spmmask }, 4882 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, 4883 write_spmbase }, 4884 4885 /* Performance Counters */ 4886 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter }, 4887 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter }, 4888 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter }, 4889 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter }, 4890 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter }, 4891 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter }, 4892 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter }, 4893 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter }, 4894 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter }, 4895 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter }, 4896 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter }, 4897 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter }, 4898 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter }, 4899 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter }, 4900 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter }, 4901 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter }, 4902 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter }, 4903 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter }, 4904 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter }, 4905 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter }, 4906 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter }, 4907 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter }, 4908 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter }, 4909 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter }, 4910 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter }, 4911 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter }, 4912 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter }, 4913 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter }, 4914 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter }, 4915 4916 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter, 4917 write_mhpmcounter }, 4918 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter, 4919 write_mhpmcounter }, 4920 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter, 4921 write_mhpmcounter }, 4922 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter, 4923 write_mhpmcounter }, 4924 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter, 4925 write_mhpmcounter }, 4926 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter, 4927 write_mhpmcounter }, 4928 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter, 4929 write_mhpmcounter }, 4930 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter, 4931 write_mhpmcounter }, 4932 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter, 4933 write_mhpmcounter }, 4934 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter, 4935 write_mhpmcounter }, 4936 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter, 4937 write_mhpmcounter }, 4938 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter, 4939 write_mhpmcounter }, 4940 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter, 4941 write_mhpmcounter }, 4942 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter, 4943 write_mhpmcounter }, 4944 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter, 4945 write_mhpmcounter }, 4946 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter, 4947 write_mhpmcounter }, 4948 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter, 4949 write_mhpmcounter }, 4950 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter, 4951 write_mhpmcounter }, 4952 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter, 4953 write_mhpmcounter }, 4954 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter, 4955 write_mhpmcounter }, 4956 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter, 4957 write_mhpmcounter }, 4958 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter, 4959 write_mhpmcounter }, 4960 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter, 4961 write_mhpmcounter }, 4962 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter, 4963 write_mhpmcounter }, 4964 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter, 4965 write_mhpmcounter }, 4966 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter, 4967 write_mhpmcounter }, 4968 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter, 4969 write_mhpmcounter }, 4970 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter, 4971 write_mhpmcounter }, 4972 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter, 4973 write_mhpmcounter }, 4974 4975 [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, 4976 write_mcountinhibit, 4977 .min_priv_ver = PRIV_VERSION_1_11_0 }, 4978 4979 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, 4980 write_mhpmevent }, 4981 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent, 4982 write_mhpmevent }, 4983 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent, 4984 write_mhpmevent }, 4985 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent, 4986 write_mhpmevent }, 4987 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent, 4988 write_mhpmevent }, 4989 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent, 4990 write_mhpmevent }, 4991 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent, 4992 write_mhpmevent }, 4993 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent, 4994 write_mhpmevent }, 4995 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent, 4996 write_mhpmevent }, 4997 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent, 4998 write_mhpmevent }, 4999 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent, 5000 write_mhpmevent }, 5001 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent, 5002 write_mhpmevent }, 5003 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent, 5004 write_mhpmevent }, 5005 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent, 5006 write_mhpmevent }, 5007 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent, 5008 write_mhpmevent }, 5009 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent, 5010 write_mhpmevent }, 5011 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent, 5012 write_mhpmevent }, 5013 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent, 5014 write_mhpmevent }, 5015 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent, 5016 write_mhpmevent }, 5017 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent, 5018 write_mhpmevent }, 5019 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent, 5020 write_mhpmevent }, 5021 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent, 5022 write_mhpmevent }, 5023 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent, 5024 write_mhpmevent }, 5025 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent, 5026 write_mhpmevent }, 5027 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent, 5028 write_mhpmevent }, 5029 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent, 5030 write_mhpmevent }, 5031 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent, 5032 write_mhpmevent }, 5033 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent, 5034 write_mhpmevent }, 5035 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent, 5036 write_mhpmevent }, 5037 5038 [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh, 5039 write_mhpmeventh, 5040 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5041 [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscofpmf, read_mhpmeventh, 5042 write_mhpmeventh, 5043 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5044 [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscofpmf, read_mhpmeventh, 5045 write_mhpmeventh, 5046 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5047 [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscofpmf, read_mhpmeventh, 5048 write_mhpmeventh, 5049 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5050 [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscofpmf, read_mhpmeventh, 5051 write_mhpmeventh, 5052 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5053 [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscofpmf, read_mhpmeventh, 5054 write_mhpmeventh, 5055 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5056 [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscofpmf, read_mhpmeventh, 5057 write_mhpmeventh, 5058 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5059 [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscofpmf, read_mhpmeventh, 5060 write_mhpmeventh, 5061 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5062 [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscofpmf, read_mhpmeventh, 5063 write_mhpmeventh, 5064 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5065 [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscofpmf, read_mhpmeventh, 5066 write_mhpmeventh, 5067 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5068 [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscofpmf, read_mhpmeventh, 5069 write_mhpmeventh, 5070 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5071 [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscofpmf, read_mhpmeventh, 5072 write_mhpmeventh, 5073 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5074 [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscofpmf, read_mhpmeventh, 5075 write_mhpmeventh, 5076 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5077 [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscofpmf, read_mhpmeventh, 5078 write_mhpmeventh, 5079 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5080 [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscofpmf, read_mhpmeventh, 5081 write_mhpmeventh, 5082 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5083 [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscofpmf, read_mhpmeventh, 5084 write_mhpmeventh, 5085 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5086 [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscofpmf, read_mhpmeventh, 5087 write_mhpmeventh, 5088 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5089 [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscofpmf, read_mhpmeventh, 5090 write_mhpmeventh, 5091 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5092 [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscofpmf, read_mhpmeventh, 5093 write_mhpmeventh, 5094 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5095 [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscofpmf, read_mhpmeventh, 5096 write_mhpmeventh, 5097 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5098 [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscofpmf, read_mhpmeventh, 5099 write_mhpmeventh, 5100 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5101 [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscofpmf, read_mhpmeventh, 5102 write_mhpmeventh, 5103 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5104 [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscofpmf, read_mhpmeventh, 5105 write_mhpmeventh, 5106 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5107 [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscofpmf, read_mhpmeventh, 5108 write_mhpmeventh, 5109 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5110 [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscofpmf, read_mhpmeventh, 5111 write_mhpmeventh, 5112 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5113 [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscofpmf, read_mhpmeventh, 5114 write_mhpmeventh, 5115 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5116 [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscofpmf, read_mhpmeventh, 5117 write_mhpmeventh, 5118 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5119 [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscofpmf, read_mhpmeventh, 5120 write_mhpmeventh, 5121 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5122 [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscofpmf, read_mhpmeventh, 5123 write_mhpmeventh, 5124 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5125 5126 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh }, 5127 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh }, 5128 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh }, 5129 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh }, 5130 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh }, 5131 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh }, 5132 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh }, 5133 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh }, 5134 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh }, 5135 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh }, 5136 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh }, 5137 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh }, 5138 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh }, 5139 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh }, 5140 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh }, 5141 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh }, 5142 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh }, 5143 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh }, 5144 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh }, 5145 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh }, 5146 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh }, 5147 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh }, 5148 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh }, 5149 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh }, 5150 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh }, 5151 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh }, 5152 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh }, 5153 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh }, 5154 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh }, 5155 5156 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh, 5157 write_mhpmcounterh }, 5158 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh, 5159 write_mhpmcounterh }, 5160 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh, 5161 write_mhpmcounterh }, 5162 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh, 5163 write_mhpmcounterh }, 5164 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh, 5165 write_mhpmcounterh }, 5166 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh, 5167 write_mhpmcounterh }, 5168 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh, 5169 write_mhpmcounterh }, 5170 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh, 5171 write_mhpmcounterh }, 5172 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh, 5173 write_mhpmcounterh }, 5174 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh, 5175 write_mhpmcounterh }, 5176 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh, 5177 write_mhpmcounterh }, 5178 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh, 5179 write_mhpmcounterh }, 5180 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh, 5181 write_mhpmcounterh }, 5182 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh, 5183 write_mhpmcounterh }, 5184 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh, 5185 write_mhpmcounterh }, 5186 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh, 5187 write_mhpmcounterh }, 5188 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh, 5189 write_mhpmcounterh }, 5190 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh, 5191 write_mhpmcounterh }, 5192 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh, 5193 write_mhpmcounterh }, 5194 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh, 5195 write_mhpmcounterh }, 5196 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh, 5197 write_mhpmcounterh }, 5198 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh, 5199 write_mhpmcounterh }, 5200 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh, 5201 write_mhpmcounterh }, 5202 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh, 5203 write_mhpmcounterh }, 5204 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh, 5205 write_mhpmcounterh }, 5206 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh, 5207 write_mhpmcounterh }, 5208 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh, 5209 write_mhpmcounterh }, 5210 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh, 5211 write_mhpmcounterh }, 5212 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh, 5213 write_mhpmcounterh }, 5214 [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf, 5215 .min_priv_ver = PRIV_VERSION_1_12_0 }, 5216 5217 #endif /* !CONFIG_USER_ONLY */ 5218 }; 5219