1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table */ 27 static riscv_csr_operations csr_ops[]; 28 29 /* CSR function table constants */ 30 enum { 31 CSR_TABLE_SIZE = 0x1000 32 }; 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 static int fs(CPURISCVState *env, int csrno) 47 { 48 #if !defined(CONFIG_USER_ONLY) 49 if (!(env->mstatus & MSTATUS_FS)) { 50 return -1; 51 } 52 #endif 53 return 0; 54 } 55 56 static int ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 target_ulong ctr_en = env->priv == PRV_U ? env->scounteren : 60 env->priv == PRV_S ? env->mcounteren : -1U; 61 if (!(ctr_en & (1 << (csrno & 31)))) { 62 return -1; 63 } 64 #endif 65 return 0; 66 } 67 68 #if !defined(CONFIG_USER_ONLY) 69 static int any(CPURISCVState *env, int csrno) 70 { 71 return 0; 72 } 73 74 static int smode(CPURISCVState *env, int csrno) 75 { 76 return -!riscv_has_ext(env, RVS); 77 } 78 79 static int pmp(CPURISCVState *env, int csrno) 80 { 81 return -!riscv_feature(env, RISCV_FEATURE_PMP); 82 } 83 #endif 84 85 /* User Floating-Point CSRs */ 86 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 87 { 88 #if !defined(CONFIG_USER_ONLY) 89 if (!(env->mstatus & MSTATUS_FS)) { 90 return -1; 91 } 92 #endif 93 *val = riscv_cpu_get_fflags(env); 94 return 0; 95 } 96 97 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 98 { 99 #if !defined(CONFIG_USER_ONLY) 100 if (!(env->mstatus & MSTATUS_FS)) { 101 return -1; 102 } 103 env->mstatus |= MSTATUS_FS; 104 #endif 105 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 106 return 0; 107 } 108 109 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 110 { 111 #if !defined(CONFIG_USER_ONLY) 112 if (!(env->mstatus & MSTATUS_FS)) { 113 return -1; 114 } 115 #endif 116 *val = env->frm; 117 return 0; 118 } 119 120 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 121 { 122 #if !defined(CONFIG_USER_ONLY) 123 if (!(env->mstatus & MSTATUS_FS)) { 124 return -1; 125 } 126 env->mstatus |= MSTATUS_FS; 127 #endif 128 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 129 return 0; 130 } 131 132 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 133 { 134 #if !defined(CONFIG_USER_ONLY) 135 if (!(env->mstatus & MSTATUS_FS)) { 136 return -1; 137 } 138 #endif 139 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 140 | (env->frm << FSR_RD_SHIFT); 141 return 0; 142 } 143 144 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 145 { 146 #if !defined(CONFIG_USER_ONLY) 147 if (!(env->mstatus & MSTATUS_FS)) { 148 return -1; 149 } 150 env->mstatus |= MSTATUS_FS; 151 #endif 152 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 153 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 154 return 0; 155 } 156 157 /* User Timers and Counters */ 158 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 159 { 160 #if !defined(CONFIG_USER_ONLY) 161 if (use_icount) { 162 *val = cpu_get_icount(); 163 } else { 164 *val = cpu_get_host_ticks(); 165 } 166 #else 167 *val = cpu_get_host_ticks(); 168 #endif 169 return 0; 170 } 171 172 #if defined(TARGET_RISCV32) 173 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 174 { 175 #if !defined(CONFIG_USER_ONLY) 176 if (use_icount) { 177 *val = cpu_get_icount() >> 32; 178 } else { 179 *val = cpu_get_host_ticks() >> 32; 180 } 181 #else 182 *val = cpu_get_host_ticks() >> 32; 183 #endif 184 return 0; 185 } 186 #endif /* TARGET_RISCV32 */ 187 188 #if defined(CONFIG_USER_ONLY) 189 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 190 { 191 *val = cpu_get_host_ticks(); 192 return 0; 193 } 194 195 #if defined(TARGET_RISCV32) 196 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 197 { 198 *val = cpu_get_host_ticks() >> 32; 199 return 0; 200 } 201 #endif 202 203 #else /* CONFIG_USER_ONLY */ 204 205 /* Machine constants */ 206 207 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 208 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 209 210 static const target_ulong delegable_ints = S_MODE_INTERRUPTS; 211 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS; 212 static const target_ulong delegable_excps = 213 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 214 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 215 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 216 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 217 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 218 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 219 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 220 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 221 (1ULL << (RISCV_EXCP_U_ECALL)) | 222 (1ULL << (RISCV_EXCP_S_ECALL)) | 223 (1ULL << (RISCV_EXCP_H_ECALL)) | 224 (1ULL << (RISCV_EXCP_M_ECALL)) | 225 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 226 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 227 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)); 228 static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | 229 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 230 SSTATUS_SUM | SSTATUS_SD; 231 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 232 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 233 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 234 235 #if defined(TARGET_RISCV32) 236 static const char valid_vm_1_09[16] = { 237 [VM_1_09_MBARE] = 1, 238 [VM_1_09_SV32] = 1, 239 }; 240 static const char valid_vm_1_10[16] = { 241 [VM_1_10_MBARE] = 1, 242 [VM_1_10_SV32] = 1 243 }; 244 #elif defined(TARGET_RISCV64) 245 static const char valid_vm_1_09[16] = { 246 [VM_1_09_MBARE] = 1, 247 [VM_1_09_SV39] = 1, 248 [VM_1_09_SV48] = 1, 249 }; 250 static const char valid_vm_1_10[16] = { 251 [VM_1_10_MBARE] = 1, 252 [VM_1_10_SV39] = 1, 253 [VM_1_10_SV48] = 1, 254 [VM_1_10_SV57] = 1 255 }; 256 #endif /* CONFIG_USER_ONLY */ 257 258 /* Machine Information Registers */ 259 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 260 { 261 return *val = 0; 262 } 263 264 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 265 { 266 *val = env->mhartid; 267 return 0; 268 } 269 270 /* Machine Trap Setup */ 271 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 272 { 273 *val = env->mstatus; 274 return 0; 275 } 276 277 static int validate_vm(CPURISCVState *env, target_ulong vm) 278 { 279 return (env->priv_ver >= PRIV_VERSION_1_10_0) ? 280 valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; 281 } 282 283 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 284 { 285 target_ulong mstatus = env->mstatus; 286 target_ulong mask = 0; 287 target_ulong mpp = get_field(val, MSTATUS_MPP); 288 289 /* flush tlb on mstatus fields that affect VM */ 290 if (env->priv_ver <= PRIV_VERSION_1_09_1) { 291 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 292 MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { 293 tlb_flush(CPU(riscv_env_get_cpu(env))); 294 } 295 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 296 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 297 MSTATUS_MPP | MSTATUS_MXR | 298 (validate_vm(env, get_field(val, MSTATUS_VM)) ? 299 MSTATUS_VM : 0); 300 } 301 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 302 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 303 MSTATUS_MPRV | MSTATUS_SUM)) { 304 tlb_flush(CPU(riscv_env_get_cpu(env))); 305 } 306 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 307 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 308 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 309 MSTATUS_TW; 310 } 311 312 /* silenty discard mstatus.mpp writes for unsupported modes */ 313 if (mpp == PRV_H || 314 (!riscv_has_ext(env, RVS) && mpp == PRV_S) || 315 (!riscv_has_ext(env, RVU) && mpp == PRV_U)) { 316 mask &= ~MSTATUS_MPP; 317 } 318 319 mstatus = (mstatus & ~mask) | (val & mask); 320 321 int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 322 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 323 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 324 env->mstatus = mstatus; 325 326 return 0; 327 } 328 329 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 330 { 331 *val = env->misa; 332 return 0; 333 } 334 335 static int write_misa(CPURISCVState *env, int csrno, target_ulong val) 336 { 337 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 338 /* drop write to misa */ 339 return 0; 340 } 341 342 /* 'I' or 'E' must be present */ 343 if (!(val & (RVI | RVE))) { 344 /* It is not, drop write to misa */ 345 return 0; 346 } 347 348 /* 'E' excludes all other extensions */ 349 if (val & RVE) { 350 /* when we support 'E' we can do "val = RVE;" however 351 * for now we just drop writes if 'E' is present. 352 */ 353 return 0; 354 } 355 356 /* Mask extensions that are not supported by this hart */ 357 val &= env->misa_mask; 358 359 /* Mask extensions that are not supported by QEMU */ 360 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 361 362 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 363 if ((val & RVD) && !(val & RVF)) { 364 val &= ~RVD; 365 } 366 367 /* Suppress 'C' if next instruction is not aligned 368 * TODO: this should check next_pc 369 */ 370 if ((val & RVC) && (GETPC() & ~3) != 0) { 371 val &= ~RVC; 372 } 373 374 /* misa.MXL writes are not supported by QEMU */ 375 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); 376 377 /* flush translation cache */ 378 if (val != env->misa) { 379 tb_flush(CPU(riscv_env_get_cpu(env))); 380 } 381 382 env->misa = val; 383 384 return 0; 385 } 386 387 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 388 { 389 *val = env->medeleg; 390 return 0; 391 } 392 393 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 394 { 395 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 396 return 0; 397 } 398 399 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 400 { 401 *val = env->mideleg; 402 return 0; 403 } 404 405 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 406 { 407 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 408 return 0; 409 } 410 411 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 412 { 413 *val = env->mie; 414 return 0; 415 } 416 417 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 418 { 419 env->mie = (env->mie & ~all_ints) | (val & all_ints); 420 return 0; 421 } 422 423 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 424 { 425 *val = env->mtvec; 426 return 0; 427 } 428 429 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 430 { 431 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 432 if ((val & 3) == 0) { 433 env->mtvec = val >> 2 << 2; 434 } else { 435 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported"); 436 } 437 return 0; 438 } 439 440 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 441 { 442 if (env->priv_ver < PRIV_VERSION_1_10_0) { 443 return -1; 444 } 445 *val = env->mcounteren; 446 return 0; 447 } 448 449 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 450 { 451 if (env->priv_ver < PRIV_VERSION_1_10_0) { 452 return -1; 453 } 454 env->mcounteren = val; 455 return 0; 456 } 457 458 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) 459 { 460 if (env->priv_ver > PRIV_VERSION_1_09_1) { 461 return -1; 462 } 463 *val = env->mcounteren; 464 return 0; 465 } 466 467 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) 468 { 469 if (env->priv_ver > PRIV_VERSION_1_09_1) { 470 return -1; 471 } 472 env->mcounteren = val; 473 return 0; 474 } 475 476 static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) 477 { 478 if (env->priv_ver > PRIV_VERSION_1_09_1) { 479 return -1; 480 } 481 *val = env->scounteren; 482 return 0; 483 } 484 485 static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) 486 { 487 if (env->priv_ver > PRIV_VERSION_1_09_1) { 488 return -1; 489 } 490 env->scounteren = val; 491 return 0; 492 } 493 494 /* Machine Trap Handling */ 495 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 496 { 497 *val = env->mscratch; 498 return 0; 499 } 500 501 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 502 { 503 env->mscratch = val; 504 return 0; 505 } 506 507 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 508 { 509 *val = env->mepc; 510 return 0; 511 } 512 513 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 514 { 515 env->mepc = val; 516 return 0; 517 } 518 519 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 520 { 521 *val = env->mcause; 522 return 0; 523 } 524 525 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 526 { 527 env->mcause = val; 528 return 0; 529 } 530 531 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 532 { 533 *val = env->mbadaddr; 534 return 0; 535 } 536 537 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) 538 { 539 env->mbadaddr = val; 540 return 0; 541 } 542 543 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 544 target_ulong new_value, target_ulong write_mask) 545 { 546 RISCVCPU *cpu = riscv_env_get_cpu(env); 547 target_ulong mask = write_mask & delegable_ints; 548 uint32_t old_mip; 549 550 /* We can't allow the supervisor to control SEIP as this would allow the 551 * supervisor to clear a pending external interrupt which will result in 552 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be 553 * hardware controlled when a PLIC is attached. This should be an option 554 * for CPUs with software-delegated Supervisor External Interrupts. */ 555 mask &= ~MIP_SEIP; 556 557 if (mask) { 558 qemu_mutex_lock_iothread(); 559 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 560 qemu_mutex_unlock_iothread(); 561 } else { 562 old_mip = atomic_read(&env->mip); 563 } 564 565 if (ret_value) { 566 *ret_value = old_mip; 567 } 568 569 return 0; 570 } 571 572 /* Supervisor Trap Setup */ 573 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 574 { 575 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 576 sstatus_v1_10_mask : sstatus_v1_9_mask); 577 *val = env->mstatus & mask; 578 return 0; 579 } 580 581 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 582 { 583 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 584 sstatus_v1_10_mask : sstatus_v1_9_mask); 585 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 586 return write_mstatus(env, CSR_MSTATUS, newval); 587 } 588 589 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 590 { 591 *val = env->mie & env->mideleg; 592 return 0; 593 } 594 595 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 596 { 597 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg); 598 return write_mie(env, CSR_MIE, newval); 599 } 600 601 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 602 { 603 *val = env->stvec; 604 return 0; 605 } 606 607 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 608 { 609 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 610 if ((val & 3) == 0) { 611 env->stvec = val >> 2 << 2; 612 } else { 613 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported"); 614 } 615 return 0; 616 } 617 618 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 619 { 620 if (env->priv_ver < PRIV_VERSION_1_10_0) { 621 return -1; 622 } 623 *val = env->scounteren; 624 return 0; 625 } 626 627 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 628 { 629 if (env->priv_ver < PRIV_VERSION_1_10_0) { 630 return -1; 631 } 632 env->scounteren = val; 633 return 0; 634 } 635 636 /* Supervisor Trap Handling */ 637 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 638 { 639 *val = env->sscratch; 640 return 0; 641 } 642 643 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 644 { 645 env->sscratch = val; 646 return 0; 647 } 648 649 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 650 { 651 *val = env->sepc; 652 return 0; 653 } 654 655 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 656 { 657 env->sepc = val; 658 return 0; 659 } 660 661 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 662 { 663 *val = env->scause; 664 return 0; 665 } 666 667 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 668 { 669 env->scause = val; 670 return 0; 671 } 672 673 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 674 { 675 *val = env->sbadaddr; 676 return 0; 677 } 678 679 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 680 { 681 env->sbadaddr = val; 682 return 0; 683 } 684 685 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 686 target_ulong new_value, target_ulong write_mask) 687 { 688 return rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 689 write_mask & env->mideleg); 690 } 691 692 /* Supervisor Protection and Translation */ 693 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 694 { 695 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 696 *val = 0; 697 } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { 698 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 699 return -1; 700 } else { 701 *val = env->satp; 702 } 703 } else { 704 *val = env->sptbr; 705 } 706 return 0; 707 } 708 709 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 710 { 711 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 712 return 0; 713 } 714 if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { 715 tlb_flush(CPU(riscv_env_get_cpu(env))); 716 env->sptbr = val & (((target_ulong) 717 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); 718 } 719 if (env->priv_ver >= PRIV_VERSION_1_10_0 && 720 validate_vm(env, get_field(val, SATP_MODE)) && 721 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 722 { 723 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 724 return -1; 725 } else { 726 tlb_flush(CPU(riscv_env_get_cpu(env))); 727 env->satp = val; 728 } 729 } 730 return 0; 731 } 732 733 /* Physical Memory Protection */ 734 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 735 { 736 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 737 return 0; 738 } 739 740 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 741 { 742 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 743 return 0; 744 } 745 746 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 747 { 748 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 749 return 0; 750 } 751 752 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 753 { 754 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 755 return 0; 756 } 757 758 #endif 759 760 /* 761 * riscv_csrrw - read and/or update control and status register 762 * 763 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 764 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 765 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 766 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 767 */ 768 769 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 770 target_ulong new_value, target_ulong write_mask) 771 { 772 int ret; 773 target_ulong old_value; 774 775 /* check privileges and return -1 if check fails */ 776 #if !defined(CONFIG_USER_ONLY) 777 int csr_priv = get_field(csrno, 0x300); 778 int read_only = get_field(csrno, 0xC00) == 3; 779 if ((write_mask && read_only) || (env->priv < csr_priv)) { 780 return -1; 781 } 782 #endif 783 784 /* check predicate */ 785 if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { 786 return -1; 787 } 788 789 /* execute combined read/write operation if it exists */ 790 if (csr_ops[csrno].op) { 791 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 792 } 793 794 /* if no accessor exists then return failure */ 795 if (!csr_ops[csrno].read) { 796 return -1; 797 } 798 799 /* read old value */ 800 ret = csr_ops[csrno].read(env, csrno, &old_value); 801 if (ret < 0) { 802 return ret; 803 } 804 805 /* write value if writable and write mask set, otherwise drop writes */ 806 if (write_mask) { 807 new_value = (old_value & ~write_mask) | (new_value & write_mask); 808 if (csr_ops[csrno].write) { 809 ret = csr_ops[csrno].write(env, csrno, new_value); 810 if (ret < 0) { 811 return ret; 812 } 813 } 814 } 815 816 /* return old value */ 817 if (ret_value) { 818 *ret_value = old_value; 819 } 820 821 return 0; 822 } 823 824 /* Control and Status Register function table */ 825 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 826 /* User Floating-Point CSRs */ 827 [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, 828 [CSR_FRM] = { fs, read_frm, write_frm }, 829 [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, 830 831 /* User Timers and Counters */ 832 [CSR_CYCLE] = { ctr, read_instret }, 833 [CSR_INSTRET] = { ctr, read_instret }, 834 #if defined(TARGET_RISCV32) 835 [CSR_CYCLEH] = { ctr, read_instreth }, 836 [CSR_INSTRETH] = { ctr, read_instreth }, 837 #endif 838 839 /* User-level time CSRs are only available in linux-user 840 * In privileged mode, the monitor emulates these CSRs */ 841 #if defined(CONFIG_USER_ONLY) 842 [CSR_TIME] = { ctr, read_time }, 843 #if defined(TARGET_RISCV32) 844 [CSR_TIMEH] = { ctr, read_timeh }, 845 #endif 846 #endif 847 848 #if !defined(CONFIG_USER_ONLY) 849 /* Machine Timers and Counters */ 850 [CSR_MCYCLE] = { any, read_instret }, 851 [CSR_MINSTRET] = { any, read_instret }, 852 #if defined(TARGET_RISCV32) 853 [CSR_MCYCLEH] = { any, read_instreth }, 854 [CSR_MINSTRETH] = { any, read_instreth }, 855 #endif 856 857 /* Machine Information Registers */ 858 [CSR_MVENDORID] = { any, read_zero }, 859 [CSR_MARCHID] = { any, read_zero }, 860 [CSR_MIMPID] = { any, read_zero }, 861 [CSR_MHARTID] = { any, read_mhartid }, 862 863 /* Machine Trap Setup */ 864 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, 865 [CSR_MISA] = { any, read_misa, write_misa }, 866 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, 867 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, 868 [CSR_MIE] = { any, read_mie, write_mie }, 869 [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, 870 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, 871 872 /* Legacy Counter Setup (priv v1.9.1) */ 873 [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, 874 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, 875 876 /* Machine Trap Handling */ 877 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, 878 [CSR_MEPC] = { any, read_mepc, write_mepc }, 879 [CSR_MCAUSE] = { any, read_mcause, write_mcause }, 880 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, 881 [CSR_MIP] = { any, NULL, NULL, rmw_mip }, 882 883 /* Supervisor Trap Setup */ 884 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, 885 [CSR_SIE] = { smode, read_sie, write_sie }, 886 [CSR_STVEC] = { smode, read_stvec, write_stvec }, 887 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, 888 889 /* Supervisor Trap Handling */ 890 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, 891 [CSR_SEPC] = { smode, read_sepc, write_sepc }, 892 [CSR_SCAUSE] = { smode, read_scause, write_scause }, 893 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, 894 [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, 895 896 /* Supervisor Protection and Translation */ 897 [CSR_SATP] = { smode, read_satp, write_satp }, 898 899 /* Physical Memory Protection */ 900 [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, 901 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, 902 903 /* Performance Counters */ 904 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, 905 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, 906 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, 907 #if defined(TARGET_RISCV32) 908 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, 909 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, 910 #endif 911 #endif /* !CONFIG_USER_ONLY */ 912 }; 913