xref: /openbmc/qemu/target/riscv/csr.c (revision dceecac8) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 
26 /* CSR function table public API */
27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28 {
29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30 }
31 
32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33 {
34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35 }
36 
37 /* Predicates */
38 static RISCVException fs(CPURISCVState *env, int csrno)
39 {
40 #if !defined(CONFIG_USER_ONLY)
41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
42         return RISCV_EXCP_ILLEGAL_INST;
43     }
44 #endif
45     return RISCV_EXCP_NONE;
46 }
47 
48 static RISCVException vs(CPURISCVState *env, int csrno)
49 {
50     CPUState *cs = env_cpu(env);
51     RISCVCPU *cpu = RISCV_CPU(cs);
52 
53     if (env->misa_ext & RVV ||
54         cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
55 #if !defined(CONFIG_USER_ONLY)
56         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
57             return RISCV_EXCP_ILLEGAL_INST;
58         }
59 #endif
60         return RISCV_EXCP_NONE;
61     }
62     return RISCV_EXCP_ILLEGAL_INST;
63 }
64 
65 static RISCVException ctr(CPURISCVState *env, int csrno)
66 {
67 #if !defined(CONFIG_USER_ONLY)
68     CPUState *cs = env_cpu(env);
69     RISCVCPU *cpu = RISCV_CPU(cs);
70 
71     if (!cpu->cfg.ext_counters) {
72         /* The Counters extensions is not enabled */
73         return RISCV_EXCP_ILLEGAL_INST;
74     }
75 
76     if (riscv_cpu_virt_enabled(env)) {
77         switch (csrno) {
78         case CSR_CYCLE:
79             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
80                 get_field(env->mcounteren, COUNTEREN_CY)) {
81                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
82             }
83             break;
84         case CSR_TIME:
85             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
86                 get_field(env->mcounteren, COUNTEREN_TM)) {
87                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
88             }
89             break;
90         case CSR_INSTRET:
91             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
92                 get_field(env->mcounteren, COUNTEREN_IR)) {
93                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
94             }
95             break;
96         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
97             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
98                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
99                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
100             }
101             break;
102         }
103         if (riscv_cpu_mxl(env) == MXL_RV32) {
104             switch (csrno) {
105             case CSR_CYCLEH:
106                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
107                     get_field(env->mcounteren, COUNTEREN_CY)) {
108                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
109                 }
110                 break;
111             case CSR_TIMEH:
112                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
113                     get_field(env->mcounteren, COUNTEREN_TM)) {
114                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
115                 }
116                 break;
117             case CSR_INSTRETH:
118                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
119                     get_field(env->mcounteren, COUNTEREN_IR)) {
120                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
121                 }
122                 break;
123             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
124                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
125                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
126                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
127                 }
128                 break;
129             }
130         }
131     }
132 #endif
133     return RISCV_EXCP_NONE;
134 }
135 
136 static RISCVException ctr32(CPURISCVState *env, int csrno)
137 {
138     if (riscv_cpu_mxl(env) != MXL_RV32) {
139         return RISCV_EXCP_ILLEGAL_INST;
140     }
141 
142     return ctr(env, csrno);
143 }
144 
145 #if !defined(CONFIG_USER_ONLY)
146 static RISCVException any(CPURISCVState *env, int csrno)
147 {
148     return RISCV_EXCP_NONE;
149 }
150 
151 static RISCVException any32(CPURISCVState *env, int csrno)
152 {
153     if (riscv_cpu_mxl(env) != MXL_RV32) {
154         return RISCV_EXCP_ILLEGAL_INST;
155     }
156 
157     return any(env, csrno);
158 
159 }
160 
161 static RISCVException smode(CPURISCVState *env, int csrno)
162 {
163     if (riscv_has_ext(env, RVS)) {
164         return RISCV_EXCP_NONE;
165     }
166 
167     return RISCV_EXCP_ILLEGAL_INST;
168 }
169 
170 static RISCVException hmode(CPURISCVState *env, int csrno)
171 {
172     if (riscv_has_ext(env, RVS) &&
173         riscv_has_ext(env, RVH)) {
174         /* Hypervisor extension is supported */
175         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
176             env->priv == PRV_M) {
177             return RISCV_EXCP_NONE;
178         } else {
179             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
180         }
181     }
182 
183     return RISCV_EXCP_ILLEGAL_INST;
184 }
185 
186 static RISCVException hmode32(CPURISCVState *env, int csrno)
187 {
188     if (riscv_cpu_mxl(env) != MXL_RV32) {
189         if (!riscv_cpu_virt_enabled(env)) {
190             return RISCV_EXCP_ILLEGAL_INST;
191         } else {
192             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
193         }
194     }
195 
196     return hmode(env, csrno);
197 
198 }
199 
200 /* Checks if PointerMasking registers could be accessed */
201 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
202 {
203     /* Check if j-ext is present */
204     if (riscv_has_ext(env, RVJ)) {
205         return RISCV_EXCP_NONE;
206     }
207     return RISCV_EXCP_ILLEGAL_INST;
208 }
209 
210 static RISCVException pmp(CPURISCVState *env, int csrno)
211 {
212     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
213         return RISCV_EXCP_NONE;
214     }
215 
216     return RISCV_EXCP_ILLEGAL_INST;
217 }
218 
219 static RISCVException epmp(CPURISCVState *env, int csrno)
220 {
221     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
222         return RISCV_EXCP_NONE;
223     }
224 
225     return RISCV_EXCP_ILLEGAL_INST;
226 }
227 #endif
228 
229 /* User Floating-Point CSRs */
230 static RISCVException read_fflags(CPURISCVState *env, int csrno,
231                                   target_ulong *val)
232 {
233     *val = riscv_cpu_get_fflags(env);
234     return RISCV_EXCP_NONE;
235 }
236 
237 static RISCVException write_fflags(CPURISCVState *env, int csrno,
238                                    target_ulong val)
239 {
240 #if !defined(CONFIG_USER_ONLY)
241     env->mstatus |= MSTATUS_FS;
242 #endif
243     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
244     return RISCV_EXCP_NONE;
245 }
246 
247 static RISCVException read_frm(CPURISCVState *env, int csrno,
248                                target_ulong *val)
249 {
250     *val = env->frm;
251     return RISCV_EXCP_NONE;
252 }
253 
254 static RISCVException write_frm(CPURISCVState *env, int csrno,
255                                 target_ulong val)
256 {
257 #if !defined(CONFIG_USER_ONLY)
258     env->mstatus |= MSTATUS_FS;
259 #endif
260     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
261     return RISCV_EXCP_NONE;
262 }
263 
264 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
265                                 target_ulong *val)
266 {
267     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
268         | (env->frm << FSR_RD_SHIFT);
269     return RISCV_EXCP_NONE;
270 }
271 
272 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
273                                  target_ulong val)
274 {
275 #if !defined(CONFIG_USER_ONLY)
276     env->mstatus |= MSTATUS_FS;
277 #endif
278     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
279     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
280     return RISCV_EXCP_NONE;
281 }
282 
283 static RISCVException read_vtype(CPURISCVState *env, int csrno,
284                                  target_ulong *val)
285 {
286     uint64_t vill;
287     switch (env->xl) {
288     case MXL_RV32:
289         vill = (uint32_t)env->vill << 31;
290         break;
291     case MXL_RV64:
292         vill = (uint64_t)env->vill << 63;
293         break;
294     default:
295         g_assert_not_reached();
296     }
297     *val = (target_ulong)vill | env->vtype;
298     return RISCV_EXCP_NONE;
299 }
300 
301 static RISCVException read_vl(CPURISCVState *env, int csrno,
302                               target_ulong *val)
303 {
304     *val = env->vl;
305     return RISCV_EXCP_NONE;
306 }
307 
308 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
309 {
310     *val = env_archcpu(env)->cfg.vlen >> 3;
311     return RISCV_EXCP_NONE;
312 }
313 
314 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
315                                 target_ulong *val)
316 {
317     *val = env->vxrm;
318     return RISCV_EXCP_NONE;
319 }
320 
321 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
322                                  target_ulong val)
323 {
324 #if !defined(CONFIG_USER_ONLY)
325     env->mstatus |= MSTATUS_VS;
326 #endif
327     env->vxrm = val;
328     return RISCV_EXCP_NONE;
329 }
330 
331 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
332                                  target_ulong *val)
333 {
334     *val = env->vxsat;
335     return RISCV_EXCP_NONE;
336 }
337 
338 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
339                                   target_ulong val)
340 {
341 #if !defined(CONFIG_USER_ONLY)
342     env->mstatus |= MSTATUS_VS;
343 #endif
344     env->vxsat = val;
345     return RISCV_EXCP_NONE;
346 }
347 
348 static RISCVException read_vstart(CPURISCVState *env, int csrno,
349                                   target_ulong *val)
350 {
351     *val = env->vstart;
352     return RISCV_EXCP_NONE;
353 }
354 
355 static RISCVException write_vstart(CPURISCVState *env, int csrno,
356                                    target_ulong val)
357 {
358 #if !defined(CONFIG_USER_ONLY)
359     env->mstatus |= MSTATUS_VS;
360 #endif
361     /*
362      * The vstart CSR is defined to have only enough writable bits
363      * to hold the largest element index, i.e. lg2(VLEN) bits.
364      */
365     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
366     return RISCV_EXCP_NONE;
367 }
368 
369 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
370 {
371     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
372     return RISCV_EXCP_NONE;
373 }
374 
375 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
376 {
377 #if !defined(CONFIG_USER_ONLY)
378     env->mstatus |= MSTATUS_VS;
379 #endif
380     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
381     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
382     return RISCV_EXCP_NONE;
383 }
384 
385 /* User Timers and Counters */
386 static RISCVException read_instret(CPURISCVState *env, int csrno,
387                                    target_ulong *val)
388 {
389 #if !defined(CONFIG_USER_ONLY)
390     if (icount_enabled()) {
391         *val = icount_get();
392     } else {
393         *val = cpu_get_host_ticks();
394     }
395 #else
396     *val = cpu_get_host_ticks();
397 #endif
398     return RISCV_EXCP_NONE;
399 }
400 
401 static RISCVException read_instreth(CPURISCVState *env, int csrno,
402                                     target_ulong *val)
403 {
404 #if !defined(CONFIG_USER_ONLY)
405     if (icount_enabled()) {
406         *val = icount_get() >> 32;
407     } else {
408         *val = cpu_get_host_ticks() >> 32;
409     }
410 #else
411     *val = cpu_get_host_ticks() >> 32;
412 #endif
413     return RISCV_EXCP_NONE;
414 }
415 
416 #if defined(CONFIG_USER_ONLY)
417 static RISCVException read_time(CPURISCVState *env, int csrno,
418                                 target_ulong *val)
419 {
420     *val = cpu_get_host_ticks();
421     return RISCV_EXCP_NONE;
422 }
423 
424 static RISCVException read_timeh(CPURISCVState *env, int csrno,
425                                  target_ulong *val)
426 {
427     *val = cpu_get_host_ticks() >> 32;
428     return RISCV_EXCP_NONE;
429 }
430 
431 #else /* CONFIG_USER_ONLY */
432 
433 static RISCVException read_time(CPURISCVState *env, int csrno,
434                                 target_ulong *val)
435 {
436     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
437 
438     if (!env->rdtime_fn) {
439         return RISCV_EXCP_ILLEGAL_INST;
440     }
441 
442     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
443     return RISCV_EXCP_NONE;
444 }
445 
446 static RISCVException read_timeh(CPURISCVState *env, int csrno,
447                                  target_ulong *val)
448 {
449     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
450 
451     if (!env->rdtime_fn) {
452         return RISCV_EXCP_ILLEGAL_INST;
453     }
454 
455     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
456     return RISCV_EXCP_NONE;
457 }
458 
459 /* Machine constants */
460 
461 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
462 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
463 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
464 
465 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
466                                            VS_MODE_INTERRUPTS;
467 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
468 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
469                                      VS_MODE_INTERRUPTS;
470 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
471                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
472                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
473                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
474                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
475                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
476                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
477                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
478                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
479                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
480                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
481                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
482                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
483                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
484                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
485                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
486                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
487                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
488                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
489 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
490     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
491       (1ULL << (RISCV_EXCP_VS_ECALL)) |
492       (1ULL << (RISCV_EXCP_M_ECALL)) |
493       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
494       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
495       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
496       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
497 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
498     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
499     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
500 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
501 static const target_ulong hip_writable_mask = MIP_VSSIP;
502 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
503 static const target_ulong vsip_writable_mask = MIP_VSSIP;
504 
505 static const char valid_vm_1_10_32[16] = {
506     [VM_1_10_MBARE] = 1,
507     [VM_1_10_SV32] = 1
508 };
509 
510 static const char valid_vm_1_10_64[16] = {
511     [VM_1_10_MBARE] = 1,
512     [VM_1_10_SV39] = 1,
513     [VM_1_10_SV48] = 1,
514     [VM_1_10_SV57] = 1
515 };
516 
517 /* Machine Information Registers */
518 static RISCVException read_zero(CPURISCVState *env, int csrno,
519                                 target_ulong *val)
520 {
521     *val = 0;
522     return RISCV_EXCP_NONE;
523 }
524 
525 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
526                                    target_ulong *val)
527 {
528     *val = env->mhartid;
529     return RISCV_EXCP_NONE;
530 }
531 
532 /* Machine Trap Setup */
533 
534 /* We do not store SD explicitly, only compute it on demand. */
535 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
536 {
537     if ((status & MSTATUS_FS) == MSTATUS_FS ||
538         (status & MSTATUS_VS) == MSTATUS_VS ||
539         (status & MSTATUS_XS) == MSTATUS_XS) {
540         switch (xl) {
541         case MXL_RV32:
542             return status | MSTATUS32_SD;
543         case MXL_RV64:
544             return status | MSTATUS64_SD;
545         case MXL_RV128:
546             return MSTATUSH128_SD;
547         default:
548             g_assert_not_reached();
549         }
550     }
551     return status;
552 }
553 
554 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
555                                    target_ulong *val)
556 {
557     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
558     return RISCV_EXCP_NONE;
559 }
560 
561 static int validate_vm(CPURISCVState *env, target_ulong vm)
562 {
563     if (riscv_cpu_mxl(env) == MXL_RV32) {
564         return valid_vm_1_10_32[vm & 0xf];
565     } else {
566         return valid_vm_1_10_64[vm & 0xf];
567     }
568 }
569 
570 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
571                                     target_ulong val)
572 {
573     uint64_t mstatus = env->mstatus;
574     uint64_t mask = 0;
575     RISCVMXL xl = riscv_cpu_mxl(env);
576 
577     /* flush tlb on mstatus fields that affect VM */
578     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
579             MSTATUS_MPRV | MSTATUS_SUM)) {
580         tlb_flush(env_cpu(env));
581     }
582     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
583         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
584         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
585         MSTATUS_TW | MSTATUS_VS;
586 
587     if (xl != MXL_RV32 || env->debugger) {
588         /*
589          * RV32: MPV and GVA are not in mstatus. The current plan is to
590          * add them to mstatush. For now, we just don't support it.
591          */
592         mask |= MSTATUS_MPV | MSTATUS_GVA;
593         if ((val & MSTATUS64_UXL) != 0) {
594             mask |= MSTATUS64_UXL;
595         }
596     }
597 
598     mstatus = (mstatus & ~mask) | (val & mask);
599 
600     if (xl > MXL_RV32) {
601         /* SXL field is for now read only */
602         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
603     }
604     env->mstatus = mstatus;
605     env->xl = cpu_recompute_xl(env);
606 
607     return RISCV_EXCP_NONE;
608 }
609 
610 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
611                                     target_ulong *val)
612 {
613     *val = env->mstatus >> 32;
614     return RISCV_EXCP_NONE;
615 }
616 
617 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
618                                      target_ulong val)
619 {
620     uint64_t valh = (uint64_t)val << 32;
621     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
622 
623     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
624         tlb_flush(env_cpu(env));
625     }
626 
627     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
628 
629     return RISCV_EXCP_NONE;
630 }
631 
632 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
633                                         Int128 *val)
634 {
635     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
636     return RISCV_EXCP_NONE;
637 }
638 
639 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
640                                      Int128 *val)
641 {
642     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
643     return RISCV_EXCP_NONE;
644 }
645 
646 static RISCVException read_misa(CPURISCVState *env, int csrno,
647                                 target_ulong *val)
648 {
649     target_ulong misa;
650 
651     switch (env->misa_mxl) {
652     case MXL_RV32:
653         misa = (target_ulong)MXL_RV32 << 30;
654         break;
655 #ifdef TARGET_RISCV64
656     case MXL_RV64:
657         misa = (target_ulong)MXL_RV64 << 62;
658         break;
659 #endif
660     default:
661         g_assert_not_reached();
662     }
663 
664     *val = misa | env->misa_ext;
665     return RISCV_EXCP_NONE;
666 }
667 
668 static RISCVException write_misa(CPURISCVState *env, int csrno,
669                                  target_ulong val)
670 {
671     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
672         /* drop write to misa */
673         return RISCV_EXCP_NONE;
674     }
675 
676     /* 'I' or 'E' must be present */
677     if (!(val & (RVI | RVE))) {
678         /* It is not, drop write to misa */
679         return RISCV_EXCP_NONE;
680     }
681 
682     /* 'E' excludes all other extensions */
683     if (val & RVE) {
684         /* when we support 'E' we can do "val = RVE;" however
685          * for now we just drop writes if 'E' is present.
686          */
687         return RISCV_EXCP_NONE;
688     }
689 
690     /*
691      * misa.MXL writes are not supported by QEMU.
692      * Drop writes to those bits.
693      */
694 
695     /* Mask extensions that are not supported by this hart */
696     val &= env->misa_ext_mask;
697 
698     /* Mask extensions that are not supported by QEMU */
699     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
700 
701     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
702     if ((val & RVD) && !(val & RVF)) {
703         val &= ~RVD;
704     }
705 
706     /* Suppress 'C' if next instruction is not aligned
707      * TODO: this should check next_pc
708      */
709     if ((val & RVC) && (GETPC() & ~3) != 0) {
710         val &= ~RVC;
711     }
712 
713     /* If nothing changed, do nothing. */
714     if (val == env->misa_ext) {
715         return RISCV_EXCP_NONE;
716     }
717 
718     /* flush translation cache */
719     tb_flush(env_cpu(env));
720     env->misa_ext = val;
721     env->xl = riscv_cpu_mxl(env);
722     return RISCV_EXCP_NONE;
723 }
724 
725 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
726                                    target_ulong *val)
727 {
728     *val = env->medeleg;
729     return RISCV_EXCP_NONE;
730 }
731 
732 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
733                                     target_ulong val)
734 {
735     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
736     return RISCV_EXCP_NONE;
737 }
738 
739 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
740                                    target_ulong *val)
741 {
742     *val = env->mideleg;
743     return RISCV_EXCP_NONE;
744 }
745 
746 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
747                                     target_ulong val)
748 {
749     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
750     if (riscv_has_ext(env, RVH)) {
751         env->mideleg |= VS_MODE_INTERRUPTS;
752     }
753     return RISCV_EXCP_NONE;
754 }
755 
756 static RISCVException read_mie(CPURISCVState *env, int csrno,
757                                target_ulong *val)
758 {
759     *val = env->mie;
760     return RISCV_EXCP_NONE;
761 }
762 
763 static RISCVException write_mie(CPURISCVState *env, int csrno,
764                                 target_ulong val)
765 {
766     env->mie = (env->mie & ~all_ints) | (val & all_ints);
767     return RISCV_EXCP_NONE;
768 }
769 
770 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
771                                  target_ulong *val)
772 {
773     *val = env->mtvec;
774     return RISCV_EXCP_NONE;
775 }
776 
777 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
778                                   target_ulong val)
779 {
780     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
781     if ((val & 3) < 2) {
782         env->mtvec = val;
783     } else {
784         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
785     }
786     return RISCV_EXCP_NONE;
787 }
788 
789 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
790                                       target_ulong *val)
791 {
792     *val = env->mcounteren;
793     return RISCV_EXCP_NONE;
794 }
795 
796 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
797                                        target_ulong val)
798 {
799     env->mcounteren = val;
800     return RISCV_EXCP_NONE;
801 }
802 
803 /* Machine Trap Handling */
804 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
805                                          Int128 *val)
806 {
807     *val = int128_make128(env->mscratch, env->mscratchh);
808     return RISCV_EXCP_NONE;
809 }
810 
811 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
812                                           Int128 val)
813 {
814     env->mscratch = int128_getlo(val);
815     env->mscratchh = int128_gethi(val);
816     return RISCV_EXCP_NONE;
817 }
818 
819 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
820                                     target_ulong *val)
821 {
822     *val = env->mscratch;
823     return RISCV_EXCP_NONE;
824 }
825 
826 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
827                                      target_ulong val)
828 {
829     env->mscratch = val;
830     return RISCV_EXCP_NONE;
831 }
832 
833 static RISCVException read_mepc(CPURISCVState *env, int csrno,
834                                      target_ulong *val)
835 {
836     *val = env->mepc;
837     return RISCV_EXCP_NONE;
838 }
839 
840 static RISCVException write_mepc(CPURISCVState *env, int csrno,
841                                      target_ulong val)
842 {
843     env->mepc = val;
844     return RISCV_EXCP_NONE;
845 }
846 
847 static RISCVException read_mcause(CPURISCVState *env, int csrno,
848                                      target_ulong *val)
849 {
850     *val = env->mcause;
851     return RISCV_EXCP_NONE;
852 }
853 
854 static RISCVException write_mcause(CPURISCVState *env, int csrno,
855                                      target_ulong val)
856 {
857     env->mcause = val;
858     return RISCV_EXCP_NONE;
859 }
860 
861 static RISCVException read_mtval(CPURISCVState *env, int csrno,
862                                  target_ulong *val)
863 {
864     *val = env->mtval;
865     return RISCV_EXCP_NONE;
866 }
867 
868 static RISCVException write_mtval(CPURISCVState *env, int csrno,
869                                   target_ulong val)
870 {
871     env->mtval = val;
872     return RISCV_EXCP_NONE;
873 }
874 
875 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
876                               target_ulong *ret_value,
877                               target_ulong new_value, target_ulong write_mask)
878 {
879     RISCVCPU *cpu = env_archcpu(env);
880     /* Allow software control of delegable interrupts not claimed by hardware */
881     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
882     uint32_t old_mip;
883 
884     if (mask) {
885         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
886     } else {
887         old_mip = env->mip;
888     }
889 
890     if (ret_value) {
891         *ret_value = old_mip;
892     }
893 
894     return RISCV_EXCP_NONE;
895 }
896 
897 /* Supervisor Trap Setup */
898 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
899                                         Int128 *val)
900 {
901     uint64_t mask = sstatus_v1_10_mask;
902     uint64_t sstatus = env->mstatus & mask;
903     if (env->xl != MXL_RV32 || env->debugger) {
904         mask |= SSTATUS64_UXL;
905     }
906 
907     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
908     return RISCV_EXCP_NONE;
909 }
910 
911 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
912                                    target_ulong *val)
913 {
914     target_ulong mask = (sstatus_v1_10_mask);
915     if (env->xl != MXL_RV32 || env->debugger) {
916         mask |= SSTATUS64_UXL;
917     }
918     /* TODO: Use SXL not MXL. */
919     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
920     return RISCV_EXCP_NONE;
921 }
922 
923 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
924                                     target_ulong val)
925 {
926     target_ulong mask = (sstatus_v1_10_mask);
927 
928     if (env->xl != MXL_RV32 || env->debugger) {
929         if ((val & SSTATUS64_UXL) != 0) {
930             mask |= SSTATUS64_UXL;
931         }
932     }
933     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
934     return write_mstatus(env, CSR_MSTATUS, newval);
935 }
936 
937 static RISCVException read_vsie(CPURISCVState *env, int csrno,
938                                 target_ulong *val)
939 {
940     /* Shift the VS bits to their S bit location in vsie */
941     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
942     return RISCV_EXCP_NONE;
943 }
944 
945 static RISCVException read_sie(CPURISCVState *env, int csrno,
946                                target_ulong *val)
947 {
948     if (riscv_cpu_virt_enabled(env)) {
949         read_vsie(env, CSR_VSIE, val);
950     } else {
951         *val = env->mie & env->mideleg;
952     }
953     return RISCV_EXCP_NONE;
954 }
955 
956 static RISCVException write_vsie(CPURISCVState *env, int csrno,
957                                  target_ulong val)
958 {
959     /* Shift the S bits to their VS bit location in mie */
960     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
961                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
962     return write_mie(env, CSR_MIE, newval);
963 }
964 
965 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
966 {
967     if (riscv_cpu_virt_enabled(env)) {
968         write_vsie(env, CSR_VSIE, val);
969     } else {
970         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
971                               (val & S_MODE_INTERRUPTS);
972         write_mie(env, CSR_MIE, newval);
973     }
974 
975     return RISCV_EXCP_NONE;
976 }
977 
978 static RISCVException read_stvec(CPURISCVState *env, int csrno,
979                                  target_ulong *val)
980 {
981     *val = env->stvec;
982     return RISCV_EXCP_NONE;
983 }
984 
985 static RISCVException write_stvec(CPURISCVState *env, int csrno,
986                                   target_ulong val)
987 {
988     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
989     if ((val & 3) < 2) {
990         env->stvec = val;
991     } else {
992         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
993     }
994     return RISCV_EXCP_NONE;
995 }
996 
997 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
998                                       target_ulong *val)
999 {
1000     *val = env->scounteren;
1001     return RISCV_EXCP_NONE;
1002 }
1003 
1004 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
1005                                        target_ulong val)
1006 {
1007     env->scounteren = val;
1008     return RISCV_EXCP_NONE;
1009 }
1010 
1011 /* Supervisor Trap Handling */
1012 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
1013                                          Int128 *val)
1014 {
1015     *val = int128_make128(env->sscratch, env->sscratchh);
1016     return RISCV_EXCP_NONE;
1017 }
1018 
1019 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
1020                                           Int128 val)
1021 {
1022     env->sscratch = int128_getlo(val);
1023     env->sscratchh = int128_gethi(val);
1024     return RISCV_EXCP_NONE;
1025 }
1026 
1027 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
1028                                     target_ulong *val)
1029 {
1030     *val = env->sscratch;
1031     return RISCV_EXCP_NONE;
1032 }
1033 
1034 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1035                                      target_ulong val)
1036 {
1037     env->sscratch = val;
1038     return RISCV_EXCP_NONE;
1039 }
1040 
1041 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1042                                 target_ulong *val)
1043 {
1044     *val = env->sepc;
1045     return RISCV_EXCP_NONE;
1046 }
1047 
1048 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1049                                  target_ulong val)
1050 {
1051     env->sepc = val;
1052     return RISCV_EXCP_NONE;
1053 }
1054 
1055 static RISCVException read_scause(CPURISCVState *env, int csrno,
1056                                   target_ulong *val)
1057 {
1058     *val = env->scause;
1059     return RISCV_EXCP_NONE;
1060 }
1061 
1062 static RISCVException write_scause(CPURISCVState *env, int csrno,
1063                                    target_ulong val)
1064 {
1065     env->scause = val;
1066     return RISCV_EXCP_NONE;
1067 }
1068 
1069 static RISCVException read_stval(CPURISCVState *env, int csrno,
1070                                  target_ulong *val)
1071 {
1072     *val = env->stval;
1073     return RISCV_EXCP_NONE;
1074 }
1075 
1076 static RISCVException write_stval(CPURISCVState *env, int csrno,
1077                                   target_ulong val)
1078 {
1079     env->stval = val;
1080     return RISCV_EXCP_NONE;
1081 }
1082 
1083 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1084                                target_ulong *ret_value,
1085                                target_ulong new_value, target_ulong write_mask)
1086 {
1087     /* Shift the S bits to their VS bit location in mip */
1088     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
1089                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
1090 
1091     if (ret_value) {
1092         *ret_value &= VS_MODE_INTERRUPTS;
1093         /* Shift the VS bits to their S bit location in vsip */
1094         *ret_value >>= 1;
1095     }
1096     return ret;
1097 }
1098 
1099 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1100                               target_ulong *ret_value,
1101                               target_ulong new_value, target_ulong write_mask)
1102 {
1103     int ret;
1104 
1105     if (riscv_cpu_virt_enabled(env)) {
1106         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
1107     } else {
1108         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
1109                       write_mask & env->mideleg & sip_writable_mask);
1110     }
1111 
1112     if (ret_value) {
1113         *ret_value &= env->mideleg;
1114     }
1115     return ret;
1116 }
1117 
1118 /* Supervisor Protection and Translation */
1119 static RISCVException read_satp(CPURISCVState *env, int csrno,
1120                                 target_ulong *val)
1121 {
1122     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1123         *val = 0;
1124         return RISCV_EXCP_NONE;
1125     }
1126 
1127     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1128         return RISCV_EXCP_ILLEGAL_INST;
1129     } else {
1130         *val = env->satp;
1131     }
1132 
1133     return RISCV_EXCP_NONE;
1134 }
1135 
1136 static RISCVException write_satp(CPURISCVState *env, int csrno,
1137                                  target_ulong val)
1138 {
1139     target_ulong vm, mask, asid;
1140 
1141     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1142         return RISCV_EXCP_NONE;
1143     }
1144 
1145     if (riscv_cpu_mxl(env) == MXL_RV32) {
1146         vm = validate_vm(env, get_field(val, SATP32_MODE));
1147         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1148         asid = (val ^ env->satp) & SATP32_ASID;
1149     } else {
1150         vm = validate_vm(env, get_field(val, SATP64_MODE));
1151         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1152         asid = (val ^ env->satp) & SATP64_ASID;
1153     }
1154 
1155     if (vm && mask) {
1156         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1157             return RISCV_EXCP_ILLEGAL_INST;
1158         } else {
1159             if (asid) {
1160                 tlb_flush(env_cpu(env));
1161             }
1162             env->satp = val;
1163         }
1164     }
1165     return RISCV_EXCP_NONE;
1166 }
1167 
1168 /* Hypervisor Extensions */
1169 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1170                                    target_ulong *val)
1171 {
1172     *val = env->hstatus;
1173     if (riscv_cpu_mxl(env) != MXL_RV32) {
1174         /* We only support 64-bit VSXL */
1175         *val = set_field(*val, HSTATUS_VSXL, 2);
1176     }
1177     /* We only support little endian */
1178     *val = set_field(*val, HSTATUS_VSBE, 0);
1179     return RISCV_EXCP_NONE;
1180 }
1181 
1182 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1183                                     target_ulong val)
1184 {
1185     env->hstatus = val;
1186     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1187         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1188     }
1189     if (get_field(val, HSTATUS_VSBE) != 0) {
1190         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1191     }
1192     return RISCV_EXCP_NONE;
1193 }
1194 
1195 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1196                                    target_ulong *val)
1197 {
1198     *val = env->hedeleg;
1199     return RISCV_EXCP_NONE;
1200 }
1201 
1202 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1203                                     target_ulong val)
1204 {
1205     env->hedeleg = val & vs_delegable_excps;
1206     return RISCV_EXCP_NONE;
1207 }
1208 
1209 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1210                                    target_ulong *val)
1211 {
1212     *val = env->hideleg;
1213     return RISCV_EXCP_NONE;
1214 }
1215 
1216 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1217                                     target_ulong val)
1218 {
1219     env->hideleg = val & vs_delegable_ints;
1220     return RISCV_EXCP_NONE;
1221 }
1222 
1223 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1224                                target_ulong *ret_value,
1225                                target_ulong new_value, target_ulong write_mask)
1226 {
1227     int ret = rmw_mip(env, 0, ret_value, new_value,
1228                       write_mask & hvip_writable_mask);
1229 
1230     if (ret_value) {
1231         *ret_value &= hvip_writable_mask;
1232     }
1233     return ret;
1234 }
1235 
1236 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1237                               target_ulong *ret_value,
1238                               target_ulong new_value, target_ulong write_mask)
1239 {
1240     int ret = rmw_mip(env, 0, ret_value, new_value,
1241                       write_mask & hip_writable_mask);
1242 
1243     if (ret_value) {
1244         *ret_value &= hip_writable_mask;
1245     }
1246     return ret;
1247 }
1248 
1249 static RISCVException read_hie(CPURISCVState *env, int csrno,
1250                                target_ulong *val)
1251 {
1252     *val = env->mie & VS_MODE_INTERRUPTS;
1253     return RISCV_EXCP_NONE;
1254 }
1255 
1256 static RISCVException write_hie(CPURISCVState *env, int csrno,
1257                                 target_ulong val)
1258 {
1259     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1260     return write_mie(env, CSR_MIE, newval);
1261 }
1262 
1263 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1264                                       target_ulong *val)
1265 {
1266     *val = env->hcounteren;
1267     return RISCV_EXCP_NONE;
1268 }
1269 
1270 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1271                                        target_ulong val)
1272 {
1273     env->hcounteren = val;
1274     return RISCV_EXCP_NONE;
1275 }
1276 
1277 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1278                                   target_ulong val)
1279 {
1280     if (val) {
1281         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1282     }
1283     return RISCV_EXCP_NONE;
1284 }
1285 
1286 static RISCVException read_htval(CPURISCVState *env, int csrno,
1287                                  target_ulong *val)
1288 {
1289     *val = env->htval;
1290     return RISCV_EXCP_NONE;
1291 }
1292 
1293 static RISCVException write_htval(CPURISCVState *env, int csrno,
1294                                   target_ulong val)
1295 {
1296     env->htval = val;
1297     return RISCV_EXCP_NONE;
1298 }
1299 
1300 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1301                                   target_ulong *val)
1302 {
1303     *val = env->htinst;
1304     return RISCV_EXCP_NONE;
1305 }
1306 
1307 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1308                                    target_ulong val)
1309 {
1310     return RISCV_EXCP_NONE;
1311 }
1312 
1313 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1314                                   target_ulong val)
1315 {
1316     if (val) {
1317         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1318     }
1319     return RISCV_EXCP_NONE;
1320 }
1321 
1322 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1323                                  target_ulong *val)
1324 {
1325     *val = env->hgatp;
1326     return RISCV_EXCP_NONE;
1327 }
1328 
1329 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1330                                   target_ulong val)
1331 {
1332     env->hgatp = val;
1333     return RISCV_EXCP_NONE;
1334 }
1335 
1336 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1337                                       target_ulong *val)
1338 {
1339     if (!env->rdtime_fn) {
1340         return RISCV_EXCP_ILLEGAL_INST;
1341     }
1342 
1343     *val = env->htimedelta;
1344     return RISCV_EXCP_NONE;
1345 }
1346 
1347 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1348                                        target_ulong val)
1349 {
1350     if (!env->rdtime_fn) {
1351         return RISCV_EXCP_ILLEGAL_INST;
1352     }
1353 
1354     if (riscv_cpu_mxl(env) == MXL_RV32) {
1355         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1356     } else {
1357         env->htimedelta = val;
1358     }
1359     return RISCV_EXCP_NONE;
1360 }
1361 
1362 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1363                                        target_ulong *val)
1364 {
1365     if (!env->rdtime_fn) {
1366         return RISCV_EXCP_ILLEGAL_INST;
1367     }
1368 
1369     *val = env->htimedelta >> 32;
1370     return RISCV_EXCP_NONE;
1371 }
1372 
1373 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1374                                         target_ulong val)
1375 {
1376     if (!env->rdtime_fn) {
1377         return RISCV_EXCP_ILLEGAL_INST;
1378     }
1379 
1380     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1381     return RISCV_EXCP_NONE;
1382 }
1383 
1384 /* Virtual CSR Registers */
1385 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1386                                     target_ulong *val)
1387 {
1388     *val = env->vsstatus;
1389     return RISCV_EXCP_NONE;
1390 }
1391 
1392 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1393                                      target_ulong val)
1394 {
1395     uint64_t mask = (target_ulong)-1;
1396     if ((val & VSSTATUS64_UXL) == 0) {
1397         mask &= ~VSSTATUS64_UXL;
1398     }
1399     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1400     return RISCV_EXCP_NONE;
1401 }
1402 
1403 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1404 {
1405     *val = env->vstvec;
1406     return RISCV_EXCP_NONE;
1407 }
1408 
1409 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1410                                    target_ulong val)
1411 {
1412     env->vstvec = val;
1413     return RISCV_EXCP_NONE;
1414 }
1415 
1416 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1417                                      target_ulong *val)
1418 {
1419     *val = env->vsscratch;
1420     return RISCV_EXCP_NONE;
1421 }
1422 
1423 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1424                                       target_ulong val)
1425 {
1426     env->vsscratch = val;
1427     return RISCV_EXCP_NONE;
1428 }
1429 
1430 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1431                                  target_ulong *val)
1432 {
1433     *val = env->vsepc;
1434     return RISCV_EXCP_NONE;
1435 }
1436 
1437 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1438                                   target_ulong val)
1439 {
1440     env->vsepc = val;
1441     return RISCV_EXCP_NONE;
1442 }
1443 
1444 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1445                                    target_ulong *val)
1446 {
1447     *val = env->vscause;
1448     return RISCV_EXCP_NONE;
1449 }
1450 
1451 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1452                                     target_ulong val)
1453 {
1454     env->vscause = val;
1455     return RISCV_EXCP_NONE;
1456 }
1457 
1458 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1459                                   target_ulong *val)
1460 {
1461     *val = env->vstval;
1462     return RISCV_EXCP_NONE;
1463 }
1464 
1465 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1466                                    target_ulong val)
1467 {
1468     env->vstval = val;
1469     return RISCV_EXCP_NONE;
1470 }
1471 
1472 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1473                                  target_ulong *val)
1474 {
1475     *val = env->vsatp;
1476     return RISCV_EXCP_NONE;
1477 }
1478 
1479 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1480                                   target_ulong val)
1481 {
1482     env->vsatp = val;
1483     return RISCV_EXCP_NONE;
1484 }
1485 
1486 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1487                                   target_ulong *val)
1488 {
1489     *val = env->mtval2;
1490     return RISCV_EXCP_NONE;
1491 }
1492 
1493 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1494                                    target_ulong val)
1495 {
1496     env->mtval2 = val;
1497     return RISCV_EXCP_NONE;
1498 }
1499 
1500 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1501                                   target_ulong *val)
1502 {
1503     *val = env->mtinst;
1504     return RISCV_EXCP_NONE;
1505 }
1506 
1507 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1508                                    target_ulong val)
1509 {
1510     env->mtinst = val;
1511     return RISCV_EXCP_NONE;
1512 }
1513 
1514 /* Physical Memory Protection */
1515 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1516                                    target_ulong *val)
1517 {
1518     *val = mseccfg_csr_read(env);
1519     return RISCV_EXCP_NONE;
1520 }
1521 
1522 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1523                          target_ulong val)
1524 {
1525     mseccfg_csr_write(env, val);
1526     return RISCV_EXCP_NONE;
1527 }
1528 
1529 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
1530 {
1531     /* TODO: RV128 restriction check */
1532     if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
1533         return false;
1534     }
1535     return true;
1536 }
1537 
1538 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1539                                   target_ulong *val)
1540 {
1541     uint32_t reg_index = csrno - CSR_PMPCFG0;
1542 
1543     if (!check_pmp_reg_index(env, reg_index)) {
1544         return RISCV_EXCP_ILLEGAL_INST;
1545     }
1546     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1547     return RISCV_EXCP_NONE;
1548 }
1549 
1550 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1551                                    target_ulong val)
1552 {
1553     uint32_t reg_index = csrno - CSR_PMPCFG0;
1554 
1555     if (!check_pmp_reg_index(env, reg_index)) {
1556         return RISCV_EXCP_ILLEGAL_INST;
1557     }
1558     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1559     return RISCV_EXCP_NONE;
1560 }
1561 
1562 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1563                                    target_ulong *val)
1564 {
1565     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1566     return RISCV_EXCP_NONE;
1567 }
1568 
1569 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1570                                     target_ulong val)
1571 {
1572     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1573     return RISCV_EXCP_NONE;
1574 }
1575 
1576 /*
1577  * Functions to access Pointer Masking feature registers
1578  * We have to check if current priv lvl could modify
1579  * csr in given mode
1580  */
1581 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1582 {
1583     int csr_priv = get_field(csrno, 0x300);
1584     int pm_current;
1585 
1586     if (env->debugger) {
1587         return false;
1588     }
1589     /*
1590      * If priv lvls differ that means we're accessing csr from higher priv lvl,
1591      * so allow the access
1592      */
1593     if (env->priv != csr_priv) {
1594         return false;
1595     }
1596     switch (env->priv) {
1597     case PRV_M:
1598         pm_current = get_field(env->mmte, M_PM_CURRENT);
1599         break;
1600     case PRV_S:
1601         pm_current = get_field(env->mmte, S_PM_CURRENT);
1602         break;
1603     case PRV_U:
1604         pm_current = get_field(env->mmte, U_PM_CURRENT);
1605         break;
1606     default:
1607         g_assert_not_reached();
1608     }
1609     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
1610     return !pm_current;
1611 }
1612 
1613 static RISCVException read_mmte(CPURISCVState *env, int csrno,
1614                                 target_ulong *val)
1615 {
1616     *val = env->mmte & MMTE_MASK;
1617     return RISCV_EXCP_NONE;
1618 }
1619 
1620 static RISCVException write_mmte(CPURISCVState *env, int csrno,
1621                                  target_ulong val)
1622 {
1623     uint64_t mstatus;
1624     target_ulong wpri_val = val & MMTE_MASK;
1625 
1626     if (val != wpri_val) {
1627         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1628                       "MMTE: WPRI violation written 0x", val,
1629                       "vs expected 0x", wpri_val);
1630     }
1631     /* for machine mode pm.current is hardwired to 1 */
1632     wpri_val |= MMTE_M_PM_CURRENT;
1633 
1634     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
1635     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1636     env->mmte = wpri_val | PM_EXT_DIRTY;
1637     riscv_cpu_update_mask(env);
1638 
1639     /* Set XS and SD bits, since PM CSRs are dirty */
1640     mstatus = env->mstatus | MSTATUS_XS;
1641     write_mstatus(env, csrno, mstatus);
1642     return RISCV_EXCP_NONE;
1643 }
1644 
1645 static RISCVException read_smte(CPURISCVState *env, int csrno,
1646                                 target_ulong *val)
1647 {
1648     *val = env->mmte & SMTE_MASK;
1649     return RISCV_EXCP_NONE;
1650 }
1651 
1652 static RISCVException write_smte(CPURISCVState *env, int csrno,
1653                                  target_ulong val)
1654 {
1655     target_ulong wpri_val = val & SMTE_MASK;
1656 
1657     if (val != wpri_val) {
1658         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1659                       "SMTE: WPRI violation written 0x", val,
1660                       "vs expected 0x", wpri_val);
1661     }
1662 
1663     /* if pm.current==0 we can't modify current PM CSRs */
1664     if (check_pm_current_disabled(env, csrno)) {
1665         return RISCV_EXCP_NONE;
1666     }
1667 
1668     wpri_val |= (env->mmte & ~SMTE_MASK);
1669     write_mmte(env, csrno, wpri_val);
1670     return RISCV_EXCP_NONE;
1671 }
1672 
1673 static RISCVException read_umte(CPURISCVState *env, int csrno,
1674                                 target_ulong *val)
1675 {
1676     *val = env->mmte & UMTE_MASK;
1677     return RISCV_EXCP_NONE;
1678 }
1679 
1680 static RISCVException write_umte(CPURISCVState *env, int csrno,
1681                                  target_ulong val)
1682 {
1683     target_ulong wpri_val = val & UMTE_MASK;
1684 
1685     if (val != wpri_val) {
1686         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1687                       "UMTE: WPRI violation written 0x", val,
1688                       "vs expected 0x", wpri_val);
1689     }
1690 
1691     if (check_pm_current_disabled(env, csrno)) {
1692         return RISCV_EXCP_NONE;
1693     }
1694 
1695     wpri_val |= (env->mmte & ~UMTE_MASK);
1696     write_mmte(env, csrno, wpri_val);
1697     return RISCV_EXCP_NONE;
1698 }
1699 
1700 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1701                                    target_ulong *val)
1702 {
1703     *val = env->mpmmask;
1704     return RISCV_EXCP_NONE;
1705 }
1706 
1707 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1708                                     target_ulong val)
1709 {
1710     uint64_t mstatus;
1711 
1712     env->mpmmask = val;
1713     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1714         env->cur_pmmask = val;
1715     }
1716     env->mmte |= PM_EXT_DIRTY;
1717 
1718     /* Set XS and SD bits, since PM CSRs are dirty */
1719     mstatus = env->mstatus | MSTATUS_XS;
1720     write_mstatus(env, csrno, mstatus);
1721     return RISCV_EXCP_NONE;
1722 }
1723 
1724 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1725                                    target_ulong *val)
1726 {
1727     *val = env->spmmask;
1728     return RISCV_EXCP_NONE;
1729 }
1730 
1731 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1732                                     target_ulong val)
1733 {
1734     uint64_t mstatus;
1735 
1736     /* if pm.current==0 we can't modify current PM CSRs */
1737     if (check_pm_current_disabled(env, csrno)) {
1738         return RISCV_EXCP_NONE;
1739     }
1740     env->spmmask = val;
1741     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1742         env->cur_pmmask = val;
1743     }
1744     env->mmte |= PM_EXT_DIRTY;
1745 
1746     /* Set XS and SD bits, since PM CSRs are dirty */
1747     mstatus = env->mstatus | MSTATUS_XS;
1748     write_mstatus(env, csrno, mstatus);
1749     return RISCV_EXCP_NONE;
1750 }
1751 
1752 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1753                                    target_ulong *val)
1754 {
1755     *val = env->upmmask;
1756     return RISCV_EXCP_NONE;
1757 }
1758 
1759 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1760                                     target_ulong val)
1761 {
1762     uint64_t mstatus;
1763 
1764     /* if pm.current==0 we can't modify current PM CSRs */
1765     if (check_pm_current_disabled(env, csrno)) {
1766         return RISCV_EXCP_NONE;
1767     }
1768     env->upmmask = val;
1769     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1770         env->cur_pmmask = val;
1771     }
1772     env->mmte |= PM_EXT_DIRTY;
1773 
1774     /* Set XS and SD bits, since PM CSRs are dirty */
1775     mstatus = env->mstatus | MSTATUS_XS;
1776     write_mstatus(env, csrno, mstatus);
1777     return RISCV_EXCP_NONE;
1778 }
1779 
1780 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1781                                    target_ulong *val)
1782 {
1783     *val = env->mpmbase;
1784     return RISCV_EXCP_NONE;
1785 }
1786 
1787 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1788                                     target_ulong val)
1789 {
1790     uint64_t mstatus;
1791 
1792     env->mpmbase = val;
1793     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1794         env->cur_pmbase = val;
1795     }
1796     env->mmte |= PM_EXT_DIRTY;
1797 
1798     /* Set XS and SD bits, since PM CSRs are dirty */
1799     mstatus = env->mstatus | MSTATUS_XS;
1800     write_mstatus(env, csrno, mstatus);
1801     return RISCV_EXCP_NONE;
1802 }
1803 
1804 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1805                                    target_ulong *val)
1806 {
1807     *val = env->spmbase;
1808     return RISCV_EXCP_NONE;
1809 }
1810 
1811 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1812                                     target_ulong val)
1813 {
1814     uint64_t mstatus;
1815 
1816     /* if pm.current==0 we can't modify current PM CSRs */
1817     if (check_pm_current_disabled(env, csrno)) {
1818         return RISCV_EXCP_NONE;
1819     }
1820     env->spmbase = val;
1821     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1822         env->cur_pmbase = val;
1823     }
1824     env->mmte |= PM_EXT_DIRTY;
1825 
1826     /* Set XS and SD bits, since PM CSRs are dirty */
1827     mstatus = env->mstatus | MSTATUS_XS;
1828     write_mstatus(env, csrno, mstatus);
1829     return RISCV_EXCP_NONE;
1830 }
1831 
1832 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1833                                    target_ulong *val)
1834 {
1835     *val = env->upmbase;
1836     return RISCV_EXCP_NONE;
1837 }
1838 
1839 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1840                                     target_ulong val)
1841 {
1842     uint64_t mstatus;
1843 
1844     /* if pm.current==0 we can't modify current PM CSRs */
1845     if (check_pm_current_disabled(env, csrno)) {
1846         return RISCV_EXCP_NONE;
1847     }
1848     env->upmbase = val;
1849     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1850         env->cur_pmbase = val;
1851     }
1852     env->mmte |= PM_EXT_DIRTY;
1853 
1854     /* Set XS and SD bits, since PM CSRs are dirty */
1855     mstatus = env->mstatus | MSTATUS_XS;
1856     write_mstatus(env, csrno, mstatus);
1857     return RISCV_EXCP_NONE;
1858 }
1859 
1860 #endif
1861 
1862 /*
1863  * riscv_csrrw - read and/or update control and status register
1864  *
1865  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1866  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1867  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1868  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1869  */
1870 
1871 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
1872                                                int csrno,
1873                                                bool write_mask,
1874                                                RISCVCPU *cpu)
1875 {
1876     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
1877     int read_only = get_field(csrno, 0xC00) == 3;
1878 #if !defined(CONFIG_USER_ONLY)
1879     int effective_priv = env->priv;
1880 
1881     if (riscv_has_ext(env, RVH) &&
1882         env->priv == PRV_S &&
1883         !riscv_cpu_virt_enabled(env)) {
1884         /*
1885          * We are in S mode without virtualisation, therefore we are in HS Mode.
1886          * Add 1 to the effective privledge level to allow us to access the
1887          * Hypervisor CSRs.
1888          */
1889         effective_priv++;
1890     }
1891 
1892     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1893         return RISCV_EXCP_ILLEGAL_INST;
1894     }
1895 #endif
1896     if (write_mask && read_only) {
1897         return RISCV_EXCP_ILLEGAL_INST;
1898     }
1899 
1900     /* ensure the CSR extension is enabled. */
1901     if (!cpu->cfg.ext_icsr) {
1902         return RISCV_EXCP_ILLEGAL_INST;
1903     }
1904 
1905     /* check predicate */
1906     if (!csr_ops[csrno].predicate) {
1907         return RISCV_EXCP_ILLEGAL_INST;
1908     }
1909 
1910     return csr_ops[csrno].predicate(env, csrno);
1911 }
1912 
1913 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
1914                                        target_ulong *ret_value,
1915                                        target_ulong new_value,
1916                                        target_ulong write_mask)
1917 {
1918     RISCVException ret;
1919     target_ulong old_value;
1920 
1921     /* execute combined read/write operation if it exists */
1922     if (csr_ops[csrno].op) {
1923         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1924     }
1925 
1926     /* if no accessor exists then return failure */
1927     if (!csr_ops[csrno].read) {
1928         return RISCV_EXCP_ILLEGAL_INST;
1929     }
1930     /* read old value */
1931     ret = csr_ops[csrno].read(env, csrno, &old_value);
1932     if (ret != RISCV_EXCP_NONE) {
1933         return ret;
1934     }
1935 
1936     /* write value if writable and write mask set, otherwise drop writes */
1937     if (write_mask) {
1938         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1939         if (csr_ops[csrno].write) {
1940             ret = csr_ops[csrno].write(env, csrno, new_value);
1941             if (ret != RISCV_EXCP_NONE) {
1942                 return ret;
1943             }
1944         }
1945     }
1946 
1947     /* return old value */
1948     if (ret_value) {
1949         *ret_value = old_value;
1950     }
1951 
1952     return RISCV_EXCP_NONE;
1953 }
1954 
1955 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1956                            target_ulong *ret_value,
1957                            target_ulong new_value, target_ulong write_mask)
1958 {
1959     RISCVCPU *cpu = env_archcpu(env);
1960 
1961     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
1962     if (ret != RISCV_EXCP_NONE) {
1963         return ret;
1964     }
1965 
1966     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
1967 }
1968 
1969 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
1970                                         Int128 *ret_value,
1971                                         Int128 new_value,
1972                                         Int128 write_mask)
1973 {
1974     RISCVException ret;
1975     Int128 old_value;
1976 
1977     /* read old value */
1978     ret = csr_ops[csrno].read128(env, csrno, &old_value);
1979     if (ret != RISCV_EXCP_NONE) {
1980         return ret;
1981     }
1982 
1983     /* write value if writable and write mask set, otherwise drop writes */
1984     if (int128_nz(write_mask)) {
1985         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
1986                               int128_and(new_value, write_mask));
1987         if (csr_ops[csrno].write128) {
1988             ret = csr_ops[csrno].write128(env, csrno, new_value);
1989             if (ret != RISCV_EXCP_NONE) {
1990                 return ret;
1991             }
1992         } else if (csr_ops[csrno].write) {
1993             /* avoids having to write wrappers for all registers */
1994             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
1995             if (ret != RISCV_EXCP_NONE) {
1996                 return ret;
1997             }
1998         }
1999     }
2000 
2001     /* return old value */
2002     if (ret_value) {
2003         *ret_value = old_value;
2004     }
2005 
2006     return RISCV_EXCP_NONE;
2007 }
2008 
2009 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
2010                                 Int128 *ret_value,
2011                                 Int128 new_value, Int128 write_mask)
2012 {
2013     RISCVException ret;
2014     RISCVCPU *cpu = env_archcpu(env);
2015 
2016     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
2017     if (ret != RISCV_EXCP_NONE) {
2018         return ret;
2019     }
2020 
2021     if (csr_ops[csrno].read128) {
2022         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
2023     }
2024 
2025     /*
2026      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
2027      * at all defined.
2028      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
2029      * significant), for those, this fallback is correctly handling the accesses
2030      */
2031     target_ulong old_value;
2032     ret = riscv_csrrw_do64(env, csrno, &old_value,
2033                            int128_getlo(new_value),
2034                            int128_getlo(write_mask));
2035     if (ret == RISCV_EXCP_NONE && ret_value) {
2036         *ret_value = int128_make64(old_value);
2037     }
2038     return ret;
2039 }
2040 
2041 /*
2042  * Debugger support.  If not in user mode, set env->debugger before the
2043  * riscv_csrrw call and clear it after the call.
2044  */
2045 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
2046                                  target_ulong *ret_value,
2047                                  target_ulong new_value,
2048                                  target_ulong write_mask)
2049 {
2050     RISCVException ret;
2051 #if !defined(CONFIG_USER_ONLY)
2052     env->debugger = true;
2053 #endif
2054     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
2055 #if !defined(CONFIG_USER_ONLY)
2056     env->debugger = false;
2057 #endif
2058     return ret;
2059 }
2060 
2061 /* Control and Status Register function table */
2062 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
2063     /* User Floating-Point CSRs */
2064     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
2065     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
2066     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
2067     /* Vector CSRs */
2068     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
2069     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
2070     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
2071     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
2072     [CSR_VL]       = { "vl",       vs,     read_vl                    },
2073     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2074     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2075     /* User Timers and Counters */
2076     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2077     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2078     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2079     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2080 
2081     /*
2082      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2083      * rdtime callback is not provided by machine/platform emulation.
2084      */
2085     [CSR_TIME]  = { "time",  ctr,   read_time  },
2086     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2087 
2088 #if !defined(CONFIG_USER_ONLY)
2089     /* Machine Timers and Counters */
2090     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2091     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2092     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2093     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2094 
2095     /* Machine Information Registers */
2096     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2097     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2098     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2099     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2100 
2101     /* Machine Trap Setup */
2102     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2103                                                read_mstatus_i128                   },
2104     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2105                                                read_misa_i128                      },
2106     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
2107     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2108     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
2109     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2110     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2111 
2112     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2113 
2114     /* Machine Trap Handling */
2115     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2116                                          read_mscratch_i128, write_mscratch_i128   },
2117     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2118     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2119     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2120     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2121 
2122     /* Supervisor Trap Setup */
2123     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2124                                               read_sstatus_i128                 },
2125     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
2126     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2127     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2128 
2129     /* Supervisor Trap Handling */
2130     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2131                                           read_sscratch_i128, write_sscratch_i128  },
2132     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2133     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2134     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2135     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2136 
2137     /* Supervisor Protection and Translation */
2138     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2139 
2140     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2141     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2142     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
2143     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2144     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2145     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
2146     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2147     [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
2148     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2149     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2150     [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
2151     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2152     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2153     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2154 
2155     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2156     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2157     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
2158     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2159     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2160     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2161     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2162     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2163     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2164 
2165     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2166     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2167 
2168     /* Physical Memory Protection */
2169     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2170     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2171     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2172     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2173     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2174     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2175     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2176     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2177     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2178     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2179     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2180     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2181     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2182     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2183     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2184     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2185     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2186     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2187     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2188     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2189     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2190 
2191     /* User Pointer Masking */
2192     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2193     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2194     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2195     /* Machine Pointer Masking */
2196     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2197     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2198     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2199     /* Supervisor Pointer Masking */
2200     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2201     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2202     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2203 
2204     /* Performance Counters */
2205     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2206     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2207     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2208     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2209     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2210     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2211     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2212     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2213     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2214     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2215     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2216     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2217     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2218     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2219     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2220     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2221     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2222     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2223     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2224     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2225     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2226     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2227     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2228     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2229     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2230     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2231     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2232     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2233     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2234 
2235     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2236     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2237     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2238     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2239     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2240     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2241     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2242     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2243     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2244     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2245     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2246     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2247     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2248     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2249     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2250     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2251     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2252     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2253     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2254     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2255     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2256     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2257     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2258     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2259     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2260     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2261     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2262     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2263     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2264 
2265     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2266     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2267     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2268     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2269     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2270     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2271     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2272     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2273     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2274     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2275     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2276     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2277     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2278     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2279     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2280     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2281     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2282     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2283     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2284     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2285     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2286     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2287     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2288     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2289     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2290     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2291     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2292     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2293     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2294 
2295     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2296     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2297     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2298     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2299     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2300     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2301     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2302     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2303     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2304     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2305     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2306     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2307     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2308     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2309     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2310     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2311     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2312     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2313     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2314     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2315     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2316     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2317     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2318     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2319     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2320     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2321     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2322     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2323     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2324 
2325     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2326     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2327     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2328     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2329     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2330     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2331     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2332     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2333     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2334     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2335     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2336     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2337     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2338     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2339     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2340     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2341     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2342     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2343     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2344     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2345     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2346     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2347     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2348     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2349     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2350     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2351     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2352     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2353     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2354 #endif /* !CONFIG_USER_ONLY */
2355 };
2356