xref: /openbmc/qemu/target/riscv/csr.c (revision d96a271a) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 
26 /* CSR function table public API */
27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28 {
29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30 }
31 
32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33 {
34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35 }
36 
37 /* Predicates */
38 static RISCVException fs(CPURISCVState *env, int csrno)
39 {
40 #if !defined(CONFIG_USER_ONLY)
41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
42         return RISCV_EXCP_ILLEGAL_INST;
43     }
44 #endif
45     return RISCV_EXCP_NONE;
46 }
47 
48 static RISCVException vs(CPURISCVState *env, int csrno)
49 {
50     CPUState *cs = env_cpu(env);
51     RISCVCPU *cpu = RISCV_CPU(cs);
52 
53     if (env->misa_ext & RVV ||
54         cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
55 #if !defined(CONFIG_USER_ONLY)
56         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
57             return RISCV_EXCP_ILLEGAL_INST;
58         }
59 #endif
60         return RISCV_EXCP_NONE;
61     }
62     return RISCV_EXCP_ILLEGAL_INST;
63 }
64 
65 static RISCVException ctr(CPURISCVState *env, int csrno)
66 {
67 #if !defined(CONFIG_USER_ONLY)
68     CPUState *cs = env_cpu(env);
69     RISCVCPU *cpu = RISCV_CPU(cs);
70 
71     if (!cpu->cfg.ext_counters) {
72         /* The Counters extensions is not enabled */
73         return RISCV_EXCP_ILLEGAL_INST;
74     }
75 
76     if (riscv_cpu_virt_enabled(env)) {
77         switch (csrno) {
78         case CSR_CYCLE:
79             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
80                 get_field(env->mcounteren, COUNTEREN_CY)) {
81                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
82             }
83             break;
84         case CSR_TIME:
85             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
86                 get_field(env->mcounteren, COUNTEREN_TM)) {
87                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
88             }
89             break;
90         case CSR_INSTRET:
91             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
92                 get_field(env->mcounteren, COUNTEREN_IR)) {
93                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
94             }
95             break;
96         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
97             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
98                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
99                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
100             }
101             break;
102         }
103         if (riscv_cpu_mxl(env) == MXL_RV32) {
104             switch (csrno) {
105             case CSR_CYCLEH:
106                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
107                     get_field(env->mcounteren, COUNTEREN_CY)) {
108                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
109                 }
110                 break;
111             case CSR_TIMEH:
112                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
113                     get_field(env->mcounteren, COUNTEREN_TM)) {
114                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
115                 }
116                 break;
117             case CSR_INSTRETH:
118                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
119                     get_field(env->mcounteren, COUNTEREN_IR)) {
120                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
121                 }
122                 break;
123             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
124                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
125                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
126                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
127                 }
128                 break;
129             }
130         }
131     }
132 #endif
133     return RISCV_EXCP_NONE;
134 }
135 
136 static RISCVException ctr32(CPURISCVState *env, int csrno)
137 {
138     if (riscv_cpu_mxl(env) != MXL_RV32) {
139         return RISCV_EXCP_ILLEGAL_INST;
140     }
141 
142     return ctr(env, csrno);
143 }
144 
145 #if !defined(CONFIG_USER_ONLY)
146 static RISCVException any(CPURISCVState *env, int csrno)
147 {
148     return RISCV_EXCP_NONE;
149 }
150 
151 static RISCVException any32(CPURISCVState *env, int csrno)
152 {
153     if (riscv_cpu_mxl(env) != MXL_RV32) {
154         return RISCV_EXCP_ILLEGAL_INST;
155     }
156 
157     return any(env, csrno);
158 
159 }
160 
161 static RISCVException smode(CPURISCVState *env, int csrno)
162 {
163     if (riscv_has_ext(env, RVS)) {
164         return RISCV_EXCP_NONE;
165     }
166 
167     return RISCV_EXCP_ILLEGAL_INST;
168 }
169 
170 static RISCVException hmode(CPURISCVState *env, int csrno)
171 {
172     if (riscv_has_ext(env, RVS) &&
173         riscv_has_ext(env, RVH)) {
174         /* Hypervisor extension is supported */
175         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
176             env->priv == PRV_M) {
177             return RISCV_EXCP_NONE;
178         } else {
179             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
180         }
181     }
182 
183     return RISCV_EXCP_ILLEGAL_INST;
184 }
185 
186 static RISCVException hmode32(CPURISCVState *env, int csrno)
187 {
188     if (riscv_cpu_mxl(env) != MXL_RV32) {
189         if (riscv_cpu_virt_enabled(env)) {
190             return RISCV_EXCP_ILLEGAL_INST;
191         } else {
192             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
193         }
194     }
195 
196     return hmode(env, csrno);
197 
198 }
199 
200 /* Checks if PointerMasking registers could be accessed */
201 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
202 {
203     /* Check if j-ext is present */
204     if (riscv_has_ext(env, RVJ)) {
205         return RISCV_EXCP_NONE;
206     }
207     return RISCV_EXCP_ILLEGAL_INST;
208 }
209 
210 static RISCVException pmp(CPURISCVState *env, int csrno)
211 {
212     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
213         return RISCV_EXCP_NONE;
214     }
215 
216     return RISCV_EXCP_ILLEGAL_INST;
217 }
218 
219 static RISCVException epmp(CPURISCVState *env, int csrno)
220 {
221     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
222         return RISCV_EXCP_NONE;
223     }
224 
225     return RISCV_EXCP_ILLEGAL_INST;
226 }
227 #endif
228 
229 /* User Floating-Point CSRs */
230 static RISCVException read_fflags(CPURISCVState *env, int csrno,
231                                   target_ulong *val)
232 {
233     *val = riscv_cpu_get_fflags(env);
234     return RISCV_EXCP_NONE;
235 }
236 
237 static RISCVException write_fflags(CPURISCVState *env, int csrno,
238                                    target_ulong val)
239 {
240 #if !defined(CONFIG_USER_ONLY)
241     env->mstatus |= MSTATUS_FS;
242 #endif
243     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
244     return RISCV_EXCP_NONE;
245 }
246 
247 static RISCVException read_frm(CPURISCVState *env, int csrno,
248                                target_ulong *val)
249 {
250     *val = env->frm;
251     return RISCV_EXCP_NONE;
252 }
253 
254 static RISCVException write_frm(CPURISCVState *env, int csrno,
255                                 target_ulong val)
256 {
257 #if !defined(CONFIG_USER_ONLY)
258     env->mstatus |= MSTATUS_FS;
259 #endif
260     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
261     return RISCV_EXCP_NONE;
262 }
263 
264 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
265                                 target_ulong *val)
266 {
267     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
268         | (env->frm << FSR_RD_SHIFT);
269     return RISCV_EXCP_NONE;
270 }
271 
272 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
273                                  target_ulong val)
274 {
275 #if !defined(CONFIG_USER_ONLY)
276     env->mstatus |= MSTATUS_FS;
277 #endif
278     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
279     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
280     return RISCV_EXCP_NONE;
281 }
282 
283 static RISCVException read_vtype(CPURISCVState *env, int csrno,
284                                  target_ulong *val)
285 {
286     uint64_t vill;
287     switch (env->xl) {
288     case MXL_RV32:
289         vill = (uint32_t)env->vill << 31;
290         break;
291     case MXL_RV64:
292         vill = (uint64_t)env->vill << 63;
293         break;
294     default:
295         g_assert_not_reached();
296     }
297     *val = (target_ulong)vill | env->vtype;
298     return RISCV_EXCP_NONE;
299 }
300 
301 static RISCVException read_vl(CPURISCVState *env, int csrno,
302                               target_ulong *val)
303 {
304     *val = env->vl;
305     return RISCV_EXCP_NONE;
306 }
307 
308 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
309 {
310     *val = env_archcpu(env)->cfg.vlen >> 3;
311     return RISCV_EXCP_NONE;
312 }
313 
314 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
315                                 target_ulong *val)
316 {
317     *val = env->vxrm;
318     return RISCV_EXCP_NONE;
319 }
320 
321 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
322                                  target_ulong val)
323 {
324 #if !defined(CONFIG_USER_ONLY)
325     env->mstatus |= MSTATUS_VS;
326 #endif
327     env->vxrm = val;
328     return RISCV_EXCP_NONE;
329 }
330 
331 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
332                                  target_ulong *val)
333 {
334     *val = env->vxsat;
335     return RISCV_EXCP_NONE;
336 }
337 
338 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
339                                   target_ulong val)
340 {
341 #if !defined(CONFIG_USER_ONLY)
342     env->mstatus |= MSTATUS_VS;
343 #endif
344     env->vxsat = val;
345     return RISCV_EXCP_NONE;
346 }
347 
348 static RISCVException read_vstart(CPURISCVState *env, int csrno,
349                                   target_ulong *val)
350 {
351     *val = env->vstart;
352     return RISCV_EXCP_NONE;
353 }
354 
355 static RISCVException write_vstart(CPURISCVState *env, int csrno,
356                                    target_ulong val)
357 {
358 #if !defined(CONFIG_USER_ONLY)
359     env->mstatus |= MSTATUS_VS;
360 #endif
361     /*
362      * The vstart CSR is defined to have only enough writable bits
363      * to hold the largest element index, i.e. lg2(VLEN) bits.
364      */
365     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
366     return RISCV_EXCP_NONE;
367 }
368 
369 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
370 {
371     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
372     return RISCV_EXCP_NONE;
373 }
374 
375 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
376 {
377 #if !defined(CONFIG_USER_ONLY)
378     env->mstatus |= MSTATUS_VS;
379 #endif
380     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
381     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
382     return RISCV_EXCP_NONE;
383 }
384 
385 /* User Timers and Counters */
386 static RISCVException read_instret(CPURISCVState *env, int csrno,
387                                    target_ulong *val)
388 {
389 #if !defined(CONFIG_USER_ONLY)
390     if (icount_enabled()) {
391         *val = icount_get();
392     } else {
393         *val = cpu_get_host_ticks();
394     }
395 #else
396     *val = cpu_get_host_ticks();
397 #endif
398     return RISCV_EXCP_NONE;
399 }
400 
401 static RISCVException read_instreth(CPURISCVState *env, int csrno,
402                                     target_ulong *val)
403 {
404 #if !defined(CONFIG_USER_ONLY)
405     if (icount_enabled()) {
406         *val = icount_get() >> 32;
407     } else {
408         *val = cpu_get_host_ticks() >> 32;
409     }
410 #else
411     *val = cpu_get_host_ticks() >> 32;
412 #endif
413     return RISCV_EXCP_NONE;
414 }
415 
416 #if defined(CONFIG_USER_ONLY)
417 static RISCVException read_time(CPURISCVState *env, int csrno,
418                                 target_ulong *val)
419 {
420     *val = cpu_get_host_ticks();
421     return RISCV_EXCP_NONE;
422 }
423 
424 static RISCVException read_timeh(CPURISCVState *env, int csrno,
425                                  target_ulong *val)
426 {
427     *val = cpu_get_host_ticks() >> 32;
428     return RISCV_EXCP_NONE;
429 }
430 
431 #else /* CONFIG_USER_ONLY */
432 
433 static RISCVException read_time(CPURISCVState *env, int csrno,
434                                 target_ulong *val)
435 {
436     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
437 
438     if (!env->rdtime_fn) {
439         return RISCV_EXCP_ILLEGAL_INST;
440     }
441 
442     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
443     return RISCV_EXCP_NONE;
444 }
445 
446 static RISCVException read_timeh(CPURISCVState *env, int csrno,
447                                  target_ulong *val)
448 {
449     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
450 
451     if (!env->rdtime_fn) {
452         return RISCV_EXCP_ILLEGAL_INST;
453     }
454 
455     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
456     return RISCV_EXCP_NONE;
457 }
458 
459 /* Machine constants */
460 
461 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
462 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
463 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
464 
465 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
466                                            VS_MODE_INTERRUPTS;
467 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
468 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
469                                      VS_MODE_INTERRUPTS;
470 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
471                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
472                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
473                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
474                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
475                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
476                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
477                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
478                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
479                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
480                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
481                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
482                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
483                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
484                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
485                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
486                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
487                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
488                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
489 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
490     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
491       (1ULL << (RISCV_EXCP_VS_ECALL)) |
492       (1ULL << (RISCV_EXCP_M_ECALL)) |
493       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
494       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
495       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
496       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
497 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
498     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
499     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
500 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
501 static const target_ulong hip_writable_mask = MIP_VSSIP;
502 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
503 static const target_ulong vsip_writable_mask = MIP_VSSIP;
504 
505 static const char valid_vm_1_10_32[16] = {
506     [VM_1_10_MBARE] = 1,
507     [VM_1_10_SV32] = 1
508 };
509 
510 static const char valid_vm_1_10_64[16] = {
511     [VM_1_10_MBARE] = 1,
512     [VM_1_10_SV39] = 1,
513     [VM_1_10_SV48] = 1,
514     [VM_1_10_SV57] = 1
515 };
516 
517 /* Machine Information Registers */
518 static RISCVException read_zero(CPURISCVState *env, int csrno,
519                                 target_ulong *val)
520 {
521     *val = 0;
522     return RISCV_EXCP_NONE;
523 }
524 
525 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
526                                    target_ulong *val)
527 {
528     *val = env->mhartid;
529     return RISCV_EXCP_NONE;
530 }
531 
532 /* Machine Trap Setup */
533 
534 /* We do not store SD explicitly, only compute it on demand. */
535 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
536 {
537     if ((status & MSTATUS_FS) == MSTATUS_FS ||
538         (status & MSTATUS_VS) == MSTATUS_VS ||
539         (status & MSTATUS_XS) == MSTATUS_XS) {
540         switch (xl) {
541         case MXL_RV32:
542             return status | MSTATUS32_SD;
543         case MXL_RV64:
544             return status | MSTATUS64_SD;
545         case MXL_RV128:
546             return MSTATUSH128_SD;
547         default:
548             g_assert_not_reached();
549         }
550     }
551     return status;
552 }
553 
554 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
555                                    target_ulong *val)
556 {
557     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
558     return RISCV_EXCP_NONE;
559 }
560 
561 static int validate_vm(CPURISCVState *env, target_ulong vm)
562 {
563     if (riscv_cpu_mxl(env) == MXL_RV32) {
564         return valid_vm_1_10_32[vm & 0xf];
565     } else {
566         return valid_vm_1_10_64[vm & 0xf];
567     }
568 }
569 
570 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
571                                     target_ulong val)
572 {
573     uint64_t mstatus = env->mstatus;
574     uint64_t mask = 0;
575 
576     /* flush tlb on mstatus fields that affect VM */
577     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
578             MSTATUS_MPRV | MSTATUS_SUM)) {
579         tlb_flush(env_cpu(env));
580     }
581     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
582         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
583         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
584         MSTATUS_TW | MSTATUS_VS;
585 
586     if (riscv_cpu_mxl(env) != MXL_RV32) {
587         /*
588          * RV32: MPV and GVA are not in mstatus. The current plan is to
589          * add them to mstatush. For now, we just don't support it.
590          */
591         mask |= MSTATUS_MPV | MSTATUS_GVA;
592     }
593 
594     mstatus = (mstatus & ~mask) | (val & mask);
595 
596     RISCVMXL xl = riscv_cpu_mxl(env);
597     if (xl > MXL_RV32) {
598         /* SXL and UXL fields are for now read only */
599         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
600         mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
601     }
602     env->mstatus = mstatus;
603     env->xl = cpu_recompute_xl(env);
604 
605     return RISCV_EXCP_NONE;
606 }
607 
608 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
609                                     target_ulong *val)
610 {
611     *val = env->mstatus >> 32;
612     return RISCV_EXCP_NONE;
613 }
614 
615 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
616                                      target_ulong val)
617 {
618     uint64_t valh = (uint64_t)val << 32;
619     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
620 
621     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
622         tlb_flush(env_cpu(env));
623     }
624 
625     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
626 
627     return RISCV_EXCP_NONE;
628 }
629 
630 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
631                                         Int128 *val)
632 {
633     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
634     return RISCV_EXCP_NONE;
635 }
636 
637 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
638                                      Int128 *val)
639 {
640     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
641     return RISCV_EXCP_NONE;
642 }
643 
644 static RISCVException read_misa(CPURISCVState *env, int csrno,
645                                 target_ulong *val)
646 {
647     target_ulong misa;
648 
649     switch (env->misa_mxl) {
650     case MXL_RV32:
651         misa = (target_ulong)MXL_RV32 << 30;
652         break;
653 #ifdef TARGET_RISCV64
654     case MXL_RV64:
655         misa = (target_ulong)MXL_RV64 << 62;
656         break;
657 #endif
658     default:
659         g_assert_not_reached();
660     }
661 
662     *val = misa | env->misa_ext;
663     return RISCV_EXCP_NONE;
664 }
665 
666 static RISCVException write_misa(CPURISCVState *env, int csrno,
667                                  target_ulong val)
668 {
669     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
670         /* drop write to misa */
671         return RISCV_EXCP_NONE;
672     }
673 
674     /* 'I' or 'E' must be present */
675     if (!(val & (RVI | RVE))) {
676         /* It is not, drop write to misa */
677         return RISCV_EXCP_NONE;
678     }
679 
680     /* 'E' excludes all other extensions */
681     if (val & RVE) {
682         /* when we support 'E' we can do "val = RVE;" however
683          * for now we just drop writes if 'E' is present.
684          */
685         return RISCV_EXCP_NONE;
686     }
687 
688     /*
689      * misa.MXL writes are not supported by QEMU.
690      * Drop writes to those bits.
691      */
692 
693     /* Mask extensions that are not supported by this hart */
694     val &= env->misa_ext_mask;
695 
696     /* Mask extensions that are not supported by QEMU */
697     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
698 
699     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
700     if ((val & RVD) && !(val & RVF)) {
701         val &= ~RVD;
702     }
703 
704     /* Suppress 'C' if next instruction is not aligned
705      * TODO: this should check next_pc
706      */
707     if ((val & RVC) && (GETPC() & ~3) != 0) {
708         val &= ~RVC;
709     }
710 
711     /* If nothing changed, do nothing. */
712     if (val == env->misa_ext) {
713         return RISCV_EXCP_NONE;
714     }
715 
716     /* flush translation cache */
717     tb_flush(env_cpu(env));
718     env->misa_ext = val;
719     env->xl = riscv_cpu_mxl(env);
720     return RISCV_EXCP_NONE;
721 }
722 
723 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
724                                    target_ulong *val)
725 {
726     *val = env->medeleg;
727     return RISCV_EXCP_NONE;
728 }
729 
730 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
731                                     target_ulong val)
732 {
733     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
734     return RISCV_EXCP_NONE;
735 }
736 
737 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
738                                    target_ulong *val)
739 {
740     *val = env->mideleg;
741     return RISCV_EXCP_NONE;
742 }
743 
744 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
745                                     target_ulong val)
746 {
747     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
748     if (riscv_has_ext(env, RVH)) {
749         env->mideleg |= VS_MODE_INTERRUPTS;
750     }
751     return RISCV_EXCP_NONE;
752 }
753 
754 static RISCVException read_mie(CPURISCVState *env, int csrno,
755                                target_ulong *val)
756 {
757     *val = env->mie;
758     return RISCV_EXCP_NONE;
759 }
760 
761 static RISCVException write_mie(CPURISCVState *env, int csrno,
762                                 target_ulong val)
763 {
764     env->mie = (env->mie & ~all_ints) | (val & all_ints);
765     return RISCV_EXCP_NONE;
766 }
767 
768 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
769                                  target_ulong *val)
770 {
771     *val = env->mtvec;
772     return RISCV_EXCP_NONE;
773 }
774 
775 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
776                                   target_ulong val)
777 {
778     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
779     if ((val & 3) < 2) {
780         env->mtvec = val;
781     } else {
782         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
783     }
784     return RISCV_EXCP_NONE;
785 }
786 
787 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
788                                       target_ulong *val)
789 {
790     *val = env->mcounteren;
791     return RISCV_EXCP_NONE;
792 }
793 
794 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
795                                        target_ulong val)
796 {
797     env->mcounteren = val;
798     return RISCV_EXCP_NONE;
799 }
800 
801 /* Machine Trap Handling */
802 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
803                                          Int128 *val)
804 {
805     *val = int128_make128(env->mscratch, env->mscratchh);
806     return RISCV_EXCP_NONE;
807 }
808 
809 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
810                                           Int128 val)
811 {
812     env->mscratch = int128_getlo(val);
813     env->mscratchh = int128_gethi(val);
814     return RISCV_EXCP_NONE;
815 }
816 
817 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
818                                     target_ulong *val)
819 {
820     *val = env->mscratch;
821     return RISCV_EXCP_NONE;
822 }
823 
824 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
825                                      target_ulong val)
826 {
827     env->mscratch = val;
828     return RISCV_EXCP_NONE;
829 }
830 
831 static RISCVException read_mepc(CPURISCVState *env, int csrno,
832                                      target_ulong *val)
833 {
834     *val = env->mepc;
835     return RISCV_EXCP_NONE;
836 }
837 
838 static RISCVException write_mepc(CPURISCVState *env, int csrno,
839                                      target_ulong val)
840 {
841     env->mepc = val;
842     return RISCV_EXCP_NONE;
843 }
844 
845 static RISCVException read_mcause(CPURISCVState *env, int csrno,
846                                      target_ulong *val)
847 {
848     *val = env->mcause;
849     return RISCV_EXCP_NONE;
850 }
851 
852 static RISCVException write_mcause(CPURISCVState *env, int csrno,
853                                      target_ulong val)
854 {
855     env->mcause = val;
856     return RISCV_EXCP_NONE;
857 }
858 
859 static RISCVException read_mtval(CPURISCVState *env, int csrno,
860                                  target_ulong *val)
861 {
862     *val = env->mtval;
863     return RISCV_EXCP_NONE;
864 }
865 
866 static RISCVException write_mtval(CPURISCVState *env, int csrno,
867                                   target_ulong val)
868 {
869     env->mtval = val;
870     return RISCV_EXCP_NONE;
871 }
872 
873 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
874                               target_ulong *ret_value,
875                               target_ulong new_value, target_ulong write_mask)
876 {
877     RISCVCPU *cpu = env_archcpu(env);
878     /* Allow software control of delegable interrupts not claimed by hardware */
879     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
880     uint32_t old_mip;
881 
882     if (mask) {
883         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
884     } else {
885         old_mip = env->mip;
886     }
887 
888     if (ret_value) {
889         *ret_value = old_mip;
890     }
891 
892     return RISCV_EXCP_NONE;
893 }
894 
895 /* Supervisor Trap Setup */
896 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
897                                         Int128 *val)
898 {
899     uint64_t mask = sstatus_v1_10_mask;
900     uint64_t sstatus = env->mstatus & mask;
901 
902     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
903     return RISCV_EXCP_NONE;
904 }
905 
906 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
907                                    target_ulong *val)
908 {
909     target_ulong mask = (sstatus_v1_10_mask);
910 
911     /* TODO: Use SXL not MXL. */
912     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
913     return RISCV_EXCP_NONE;
914 }
915 
916 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
917                                     target_ulong val)
918 {
919     target_ulong mask = (sstatus_v1_10_mask);
920     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
921     return write_mstatus(env, CSR_MSTATUS, newval);
922 }
923 
924 static RISCVException read_vsie(CPURISCVState *env, int csrno,
925                                 target_ulong *val)
926 {
927     /* Shift the VS bits to their S bit location in vsie */
928     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
929     return RISCV_EXCP_NONE;
930 }
931 
932 static RISCVException read_sie(CPURISCVState *env, int csrno,
933                                target_ulong *val)
934 {
935     if (riscv_cpu_virt_enabled(env)) {
936         read_vsie(env, CSR_VSIE, val);
937     } else {
938         *val = env->mie & env->mideleg;
939     }
940     return RISCV_EXCP_NONE;
941 }
942 
943 static RISCVException write_vsie(CPURISCVState *env, int csrno,
944                                  target_ulong val)
945 {
946     /* Shift the S bits to their VS bit location in mie */
947     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
948                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
949     return write_mie(env, CSR_MIE, newval);
950 }
951 
952 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
953 {
954     if (riscv_cpu_virt_enabled(env)) {
955         write_vsie(env, CSR_VSIE, val);
956     } else {
957         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
958                               (val & S_MODE_INTERRUPTS);
959         write_mie(env, CSR_MIE, newval);
960     }
961 
962     return RISCV_EXCP_NONE;
963 }
964 
965 static RISCVException read_stvec(CPURISCVState *env, int csrno,
966                                  target_ulong *val)
967 {
968     *val = env->stvec;
969     return RISCV_EXCP_NONE;
970 }
971 
972 static RISCVException write_stvec(CPURISCVState *env, int csrno,
973                                   target_ulong val)
974 {
975     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
976     if ((val & 3) < 2) {
977         env->stvec = val;
978     } else {
979         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
980     }
981     return RISCV_EXCP_NONE;
982 }
983 
984 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
985                                       target_ulong *val)
986 {
987     *val = env->scounteren;
988     return RISCV_EXCP_NONE;
989 }
990 
991 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
992                                        target_ulong val)
993 {
994     env->scounteren = val;
995     return RISCV_EXCP_NONE;
996 }
997 
998 /* Supervisor Trap Handling */
999 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
1000                                          Int128 *val)
1001 {
1002     *val = int128_make128(env->sscratch, env->sscratchh);
1003     return RISCV_EXCP_NONE;
1004 }
1005 
1006 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
1007                                           Int128 val)
1008 {
1009     env->sscratch = int128_getlo(val);
1010     env->sscratchh = int128_gethi(val);
1011     return RISCV_EXCP_NONE;
1012 }
1013 
1014 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
1015                                     target_ulong *val)
1016 {
1017     *val = env->sscratch;
1018     return RISCV_EXCP_NONE;
1019 }
1020 
1021 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1022                                      target_ulong val)
1023 {
1024     env->sscratch = val;
1025     return RISCV_EXCP_NONE;
1026 }
1027 
1028 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1029                                 target_ulong *val)
1030 {
1031     *val = env->sepc;
1032     return RISCV_EXCP_NONE;
1033 }
1034 
1035 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1036                                  target_ulong val)
1037 {
1038     env->sepc = val;
1039     return RISCV_EXCP_NONE;
1040 }
1041 
1042 static RISCVException read_scause(CPURISCVState *env, int csrno,
1043                                   target_ulong *val)
1044 {
1045     *val = env->scause;
1046     return RISCV_EXCP_NONE;
1047 }
1048 
1049 static RISCVException write_scause(CPURISCVState *env, int csrno,
1050                                    target_ulong val)
1051 {
1052     env->scause = val;
1053     return RISCV_EXCP_NONE;
1054 }
1055 
1056 static RISCVException read_stval(CPURISCVState *env, int csrno,
1057                                  target_ulong *val)
1058 {
1059     *val = env->stval;
1060     return RISCV_EXCP_NONE;
1061 }
1062 
1063 static RISCVException write_stval(CPURISCVState *env, int csrno,
1064                                   target_ulong val)
1065 {
1066     env->stval = val;
1067     return RISCV_EXCP_NONE;
1068 }
1069 
1070 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1071                                target_ulong *ret_value,
1072                                target_ulong new_value, target_ulong write_mask)
1073 {
1074     /* Shift the S bits to their VS bit location in mip */
1075     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
1076                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
1077 
1078     if (ret_value) {
1079         *ret_value &= VS_MODE_INTERRUPTS;
1080         /* Shift the VS bits to their S bit location in vsip */
1081         *ret_value >>= 1;
1082     }
1083     return ret;
1084 }
1085 
1086 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1087                               target_ulong *ret_value,
1088                               target_ulong new_value, target_ulong write_mask)
1089 {
1090     int ret;
1091 
1092     if (riscv_cpu_virt_enabled(env)) {
1093         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
1094     } else {
1095         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
1096                       write_mask & env->mideleg & sip_writable_mask);
1097     }
1098 
1099     if (ret_value) {
1100         *ret_value &= env->mideleg;
1101     }
1102     return ret;
1103 }
1104 
1105 /* Supervisor Protection and Translation */
1106 static RISCVException read_satp(CPURISCVState *env, int csrno,
1107                                 target_ulong *val)
1108 {
1109     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1110         *val = 0;
1111         return RISCV_EXCP_NONE;
1112     }
1113 
1114     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1115         return RISCV_EXCP_ILLEGAL_INST;
1116     } else {
1117         *val = env->satp;
1118     }
1119 
1120     return RISCV_EXCP_NONE;
1121 }
1122 
1123 static RISCVException write_satp(CPURISCVState *env, int csrno,
1124                                  target_ulong val)
1125 {
1126     target_ulong vm, mask, asid;
1127 
1128     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1129         return RISCV_EXCP_NONE;
1130     }
1131 
1132     if (riscv_cpu_mxl(env) == MXL_RV32) {
1133         vm = validate_vm(env, get_field(val, SATP32_MODE));
1134         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1135         asid = (val ^ env->satp) & SATP32_ASID;
1136     } else {
1137         vm = validate_vm(env, get_field(val, SATP64_MODE));
1138         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1139         asid = (val ^ env->satp) & SATP64_ASID;
1140     }
1141 
1142     if (vm && mask) {
1143         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1144             return RISCV_EXCP_ILLEGAL_INST;
1145         } else {
1146             if (asid) {
1147                 tlb_flush(env_cpu(env));
1148             }
1149             env->satp = val;
1150         }
1151     }
1152     return RISCV_EXCP_NONE;
1153 }
1154 
1155 /* Hypervisor Extensions */
1156 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1157                                    target_ulong *val)
1158 {
1159     *val = env->hstatus;
1160     if (riscv_cpu_mxl(env) != MXL_RV32) {
1161         /* We only support 64-bit VSXL */
1162         *val = set_field(*val, HSTATUS_VSXL, 2);
1163     }
1164     /* We only support little endian */
1165     *val = set_field(*val, HSTATUS_VSBE, 0);
1166     return RISCV_EXCP_NONE;
1167 }
1168 
1169 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1170                                     target_ulong val)
1171 {
1172     env->hstatus = val;
1173     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1174         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1175     }
1176     if (get_field(val, HSTATUS_VSBE) != 0) {
1177         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1178     }
1179     return RISCV_EXCP_NONE;
1180 }
1181 
1182 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1183                                    target_ulong *val)
1184 {
1185     *val = env->hedeleg;
1186     return RISCV_EXCP_NONE;
1187 }
1188 
1189 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1190                                     target_ulong val)
1191 {
1192     env->hedeleg = val & vs_delegable_excps;
1193     return RISCV_EXCP_NONE;
1194 }
1195 
1196 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1197                                    target_ulong *val)
1198 {
1199     *val = env->hideleg;
1200     return RISCV_EXCP_NONE;
1201 }
1202 
1203 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1204                                     target_ulong val)
1205 {
1206     env->hideleg = val & vs_delegable_ints;
1207     return RISCV_EXCP_NONE;
1208 }
1209 
1210 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1211                                target_ulong *ret_value,
1212                                target_ulong new_value, target_ulong write_mask)
1213 {
1214     int ret = rmw_mip(env, 0, ret_value, new_value,
1215                       write_mask & hvip_writable_mask);
1216 
1217     if (ret_value) {
1218         *ret_value &= hvip_writable_mask;
1219     }
1220     return ret;
1221 }
1222 
1223 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1224                               target_ulong *ret_value,
1225                               target_ulong new_value, target_ulong write_mask)
1226 {
1227     int ret = rmw_mip(env, 0, ret_value, new_value,
1228                       write_mask & hip_writable_mask);
1229 
1230     if (ret_value) {
1231         *ret_value &= hip_writable_mask;
1232     }
1233     return ret;
1234 }
1235 
1236 static RISCVException read_hie(CPURISCVState *env, int csrno,
1237                                target_ulong *val)
1238 {
1239     *val = env->mie & VS_MODE_INTERRUPTS;
1240     return RISCV_EXCP_NONE;
1241 }
1242 
1243 static RISCVException write_hie(CPURISCVState *env, int csrno,
1244                                 target_ulong val)
1245 {
1246     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1247     return write_mie(env, CSR_MIE, newval);
1248 }
1249 
1250 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1251                                       target_ulong *val)
1252 {
1253     *val = env->hcounteren;
1254     return RISCV_EXCP_NONE;
1255 }
1256 
1257 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1258                                        target_ulong val)
1259 {
1260     env->hcounteren = val;
1261     return RISCV_EXCP_NONE;
1262 }
1263 
1264 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1265                                   target_ulong val)
1266 {
1267     if (val) {
1268         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1269     }
1270     return RISCV_EXCP_NONE;
1271 }
1272 
1273 static RISCVException read_htval(CPURISCVState *env, int csrno,
1274                                  target_ulong *val)
1275 {
1276     *val = env->htval;
1277     return RISCV_EXCP_NONE;
1278 }
1279 
1280 static RISCVException write_htval(CPURISCVState *env, int csrno,
1281                                   target_ulong val)
1282 {
1283     env->htval = val;
1284     return RISCV_EXCP_NONE;
1285 }
1286 
1287 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1288                                   target_ulong *val)
1289 {
1290     *val = env->htinst;
1291     return RISCV_EXCP_NONE;
1292 }
1293 
1294 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1295                                    target_ulong val)
1296 {
1297     return RISCV_EXCP_NONE;
1298 }
1299 
1300 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1301                                   target_ulong val)
1302 {
1303     if (val) {
1304         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1305     }
1306     return RISCV_EXCP_NONE;
1307 }
1308 
1309 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1310                                  target_ulong *val)
1311 {
1312     *val = env->hgatp;
1313     return RISCV_EXCP_NONE;
1314 }
1315 
1316 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1317                                   target_ulong val)
1318 {
1319     env->hgatp = val;
1320     return RISCV_EXCP_NONE;
1321 }
1322 
1323 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1324                                       target_ulong *val)
1325 {
1326     if (!env->rdtime_fn) {
1327         return RISCV_EXCP_ILLEGAL_INST;
1328     }
1329 
1330     *val = env->htimedelta;
1331     return RISCV_EXCP_NONE;
1332 }
1333 
1334 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1335                                        target_ulong val)
1336 {
1337     if (!env->rdtime_fn) {
1338         return RISCV_EXCP_ILLEGAL_INST;
1339     }
1340 
1341     if (riscv_cpu_mxl(env) == MXL_RV32) {
1342         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1343     } else {
1344         env->htimedelta = val;
1345     }
1346     return RISCV_EXCP_NONE;
1347 }
1348 
1349 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1350                                        target_ulong *val)
1351 {
1352     if (!env->rdtime_fn) {
1353         return RISCV_EXCP_ILLEGAL_INST;
1354     }
1355 
1356     *val = env->htimedelta >> 32;
1357     return RISCV_EXCP_NONE;
1358 }
1359 
1360 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1361                                         target_ulong val)
1362 {
1363     if (!env->rdtime_fn) {
1364         return RISCV_EXCP_ILLEGAL_INST;
1365     }
1366 
1367     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1368     return RISCV_EXCP_NONE;
1369 }
1370 
1371 /* Virtual CSR Registers */
1372 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1373                                     target_ulong *val)
1374 {
1375     *val = env->vsstatus;
1376     return RISCV_EXCP_NONE;
1377 }
1378 
1379 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1380                                      target_ulong val)
1381 {
1382     uint64_t mask = (target_ulong)-1;
1383     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1384     return RISCV_EXCP_NONE;
1385 }
1386 
1387 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1388 {
1389     *val = env->vstvec;
1390     return RISCV_EXCP_NONE;
1391 }
1392 
1393 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1394                                    target_ulong val)
1395 {
1396     env->vstvec = val;
1397     return RISCV_EXCP_NONE;
1398 }
1399 
1400 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1401                                      target_ulong *val)
1402 {
1403     *val = env->vsscratch;
1404     return RISCV_EXCP_NONE;
1405 }
1406 
1407 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1408                                       target_ulong val)
1409 {
1410     env->vsscratch = val;
1411     return RISCV_EXCP_NONE;
1412 }
1413 
1414 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1415                                  target_ulong *val)
1416 {
1417     *val = env->vsepc;
1418     return RISCV_EXCP_NONE;
1419 }
1420 
1421 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1422                                   target_ulong val)
1423 {
1424     env->vsepc = val;
1425     return RISCV_EXCP_NONE;
1426 }
1427 
1428 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1429                                    target_ulong *val)
1430 {
1431     *val = env->vscause;
1432     return RISCV_EXCP_NONE;
1433 }
1434 
1435 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1436                                     target_ulong val)
1437 {
1438     env->vscause = val;
1439     return RISCV_EXCP_NONE;
1440 }
1441 
1442 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1443                                   target_ulong *val)
1444 {
1445     *val = env->vstval;
1446     return RISCV_EXCP_NONE;
1447 }
1448 
1449 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1450                                    target_ulong val)
1451 {
1452     env->vstval = val;
1453     return RISCV_EXCP_NONE;
1454 }
1455 
1456 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1457                                  target_ulong *val)
1458 {
1459     *val = env->vsatp;
1460     return RISCV_EXCP_NONE;
1461 }
1462 
1463 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1464                                   target_ulong val)
1465 {
1466     env->vsatp = val;
1467     return RISCV_EXCP_NONE;
1468 }
1469 
1470 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1471                                   target_ulong *val)
1472 {
1473     *val = env->mtval2;
1474     return RISCV_EXCP_NONE;
1475 }
1476 
1477 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1478                                    target_ulong val)
1479 {
1480     env->mtval2 = val;
1481     return RISCV_EXCP_NONE;
1482 }
1483 
1484 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1485                                   target_ulong *val)
1486 {
1487     *val = env->mtinst;
1488     return RISCV_EXCP_NONE;
1489 }
1490 
1491 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1492                                    target_ulong val)
1493 {
1494     env->mtinst = val;
1495     return RISCV_EXCP_NONE;
1496 }
1497 
1498 /* Physical Memory Protection */
1499 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1500                                    target_ulong *val)
1501 {
1502     *val = mseccfg_csr_read(env);
1503     return RISCV_EXCP_NONE;
1504 }
1505 
1506 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1507                          target_ulong val)
1508 {
1509     mseccfg_csr_write(env, val);
1510     return RISCV_EXCP_NONE;
1511 }
1512 
1513 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
1514 {
1515     /* TODO: RV128 restriction check */
1516     if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
1517         return false;
1518     }
1519     return true;
1520 }
1521 
1522 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1523                                   target_ulong *val)
1524 {
1525     uint32_t reg_index = csrno - CSR_PMPCFG0;
1526 
1527     if (!check_pmp_reg_index(env, reg_index)) {
1528         return RISCV_EXCP_ILLEGAL_INST;
1529     }
1530     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1531     return RISCV_EXCP_NONE;
1532 }
1533 
1534 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1535                                    target_ulong val)
1536 {
1537     uint32_t reg_index = csrno - CSR_PMPCFG0;
1538 
1539     if (!check_pmp_reg_index(env, reg_index)) {
1540         return RISCV_EXCP_ILLEGAL_INST;
1541     }
1542     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1543     return RISCV_EXCP_NONE;
1544 }
1545 
1546 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1547                                    target_ulong *val)
1548 {
1549     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1550     return RISCV_EXCP_NONE;
1551 }
1552 
1553 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1554                                     target_ulong val)
1555 {
1556     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1557     return RISCV_EXCP_NONE;
1558 }
1559 
1560 /*
1561  * Functions to access Pointer Masking feature registers
1562  * We have to check if current priv lvl could modify
1563  * csr in given mode
1564  */
1565 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1566 {
1567     int csr_priv = get_field(csrno, 0x300);
1568     int pm_current;
1569 
1570     if (env->debugger) {
1571         return false;
1572     }
1573     /*
1574      * If priv lvls differ that means we're accessing csr from higher priv lvl,
1575      * so allow the access
1576      */
1577     if (env->priv != csr_priv) {
1578         return false;
1579     }
1580     switch (env->priv) {
1581     case PRV_M:
1582         pm_current = get_field(env->mmte, M_PM_CURRENT);
1583         break;
1584     case PRV_S:
1585         pm_current = get_field(env->mmte, S_PM_CURRENT);
1586         break;
1587     case PRV_U:
1588         pm_current = get_field(env->mmte, U_PM_CURRENT);
1589         break;
1590     default:
1591         g_assert_not_reached();
1592     }
1593     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
1594     return !pm_current;
1595 }
1596 
1597 static RISCVException read_mmte(CPURISCVState *env, int csrno,
1598                                 target_ulong *val)
1599 {
1600     *val = env->mmte & MMTE_MASK;
1601     return RISCV_EXCP_NONE;
1602 }
1603 
1604 static RISCVException write_mmte(CPURISCVState *env, int csrno,
1605                                  target_ulong val)
1606 {
1607     uint64_t mstatus;
1608     target_ulong wpri_val = val & MMTE_MASK;
1609 
1610     if (val != wpri_val) {
1611         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1612                       "MMTE: WPRI violation written 0x", val,
1613                       "vs expected 0x", wpri_val);
1614     }
1615     /* for machine mode pm.current is hardwired to 1 */
1616     wpri_val |= MMTE_M_PM_CURRENT;
1617 
1618     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
1619     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1620     env->mmte = wpri_val | PM_EXT_DIRTY;
1621     riscv_cpu_update_mask(env);
1622 
1623     /* Set XS and SD bits, since PM CSRs are dirty */
1624     mstatus = env->mstatus | MSTATUS_XS;
1625     write_mstatus(env, csrno, mstatus);
1626     return RISCV_EXCP_NONE;
1627 }
1628 
1629 static RISCVException read_smte(CPURISCVState *env, int csrno,
1630                                 target_ulong *val)
1631 {
1632     *val = env->mmte & SMTE_MASK;
1633     return RISCV_EXCP_NONE;
1634 }
1635 
1636 static RISCVException write_smte(CPURISCVState *env, int csrno,
1637                                  target_ulong val)
1638 {
1639     target_ulong wpri_val = val & SMTE_MASK;
1640 
1641     if (val != wpri_val) {
1642         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1643                       "SMTE: WPRI violation written 0x", val,
1644                       "vs expected 0x", wpri_val);
1645     }
1646 
1647     /* if pm.current==0 we can't modify current PM CSRs */
1648     if (check_pm_current_disabled(env, csrno)) {
1649         return RISCV_EXCP_NONE;
1650     }
1651 
1652     wpri_val |= (env->mmte & ~SMTE_MASK);
1653     write_mmte(env, csrno, wpri_val);
1654     return RISCV_EXCP_NONE;
1655 }
1656 
1657 static RISCVException read_umte(CPURISCVState *env, int csrno,
1658                                 target_ulong *val)
1659 {
1660     *val = env->mmte & UMTE_MASK;
1661     return RISCV_EXCP_NONE;
1662 }
1663 
1664 static RISCVException write_umte(CPURISCVState *env, int csrno,
1665                                  target_ulong val)
1666 {
1667     target_ulong wpri_val = val & UMTE_MASK;
1668 
1669     if (val != wpri_val) {
1670         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1671                       "UMTE: WPRI violation written 0x", val,
1672                       "vs expected 0x", wpri_val);
1673     }
1674 
1675     if (check_pm_current_disabled(env, csrno)) {
1676         return RISCV_EXCP_NONE;
1677     }
1678 
1679     wpri_val |= (env->mmte & ~UMTE_MASK);
1680     write_mmte(env, csrno, wpri_val);
1681     return RISCV_EXCP_NONE;
1682 }
1683 
1684 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1685                                    target_ulong *val)
1686 {
1687     *val = env->mpmmask;
1688     return RISCV_EXCP_NONE;
1689 }
1690 
1691 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1692                                     target_ulong val)
1693 {
1694     uint64_t mstatus;
1695 
1696     env->mpmmask = val;
1697     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1698         env->cur_pmmask = val;
1699     }
1700     env->mmte |= PM_EXT_DIRTY;
1701 
1702     /* Set XS and SD bits, since PM CSRs are dirty */
1703     mstatus = env->mstatus | MSTATUS_XS;
1704     write_mstatus(env, csrno, mstatus);
1705     return RISCV_EXCP_NONE;
1706 }
1707 
1708 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1709                                    target_ulong *val)
1710 {
1711     *val = env->spmmask;
1712     return RISCV_EXCP_NONE;
1713 }
1714 
1715 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1716                                     target_ulong val)
1717 {
1718     uint64_t mstatus;
1719 
1720     /* if pm.current==0 we can't modify current PM CSRs */
1721     if (check_pm_current_disabled(env, csrno)) {
1722         return RISCV_EXCP_NONE;
1723     }
1724     env->spmmask = val;
1725     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1726         env->cur_pmmask = val;
1727     }
1728     env->mmte |= PM_EXT_DIRTY;
1729 
1730     /* Set XS and SD bits, since PM CSRs are dirty */
1731     mstatus = env->mstatus | MSTATUS_XS;
1732     write_mstatus(env, csrno, mstatus);
1733     return RISCV_EXCP_NONE;
1734 }
1735 
1736 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1737                                    target_ulong *val)
1738 {
1739     *val = env->upmmask;
1740     return RISCV_EXCP_NONE;
1741 }
1742 
1743 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1744                                     target_ulong val)
1745 {
1746     uint64_t mstatus;
1747 
1748     /* if pm.current==0 we can't modify current PM CSRs */
1749     if (check_pm_current_disabled(env, csrno)) {
1750         return RISCV_EXCP_NONE;
1751     }
1752     env->upmmask = val;
1753     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1754         env->cur_pmmask = val;
1755     }
1756     env->mmte |= PM_EXT_DIRTY;
1757 
1758     /* Set XS and SD bits, since PM CSRs are dirty */
1759     mstatus = env->mstatus | MSTATUS_XS;
1760     write_mstatus(env, csrno, mstatus);
1761     return RISCV_EXCP_NONE;
1762 }
1763 
1764 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1765                                    target_ulong *val)
1766 {
1767     *val = env->mpmbase;
1768     return RISCV_EXCP_NONE;
1769 }
1770 
1771 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1772                                     target_ulong val)
1773 {
1774     uint64_t mstatus;
1775 
1776     env->mpmbase = val;
1777     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1778         env->cur_pmbase = val;
1779     }
1780     env->mmte |= PM_EXT_DIRTY;
1781 
1782     /* Set XS and SD bits, since PM CSRs are dirty */
1783     mstatus = env->mstatus | MSTATUS_XS;
1784     write_mstatus(env, csrno, mstatus);
1785     return RISCV_EXCP_NONE;
1786 }
1787 
1788 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1789                                    target_ulong *val)
1790 {
1791     *val = env->spmbase;
1792     return RISCV_EXCP_NONE;
1793 }
1794 
1795 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1796                                     target_ulong val)
1797 {
1798     uint64_t mstatus;
1799 
1800     /* if pm.current==0 we can't modify current PM CSRs */
1801     if (check_pm_current_disabled(env, csrno)) {
1802         return RISCV_EXCP_NONE;
1803     }
1804     env->spmbase = val;
1805     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1806         env->cur_pmbase = val;
1807     }
1808     env->mmte |= PM_EXT_DIRTY;
1809 
1810     /* Set XS and SD bits, since PM CSRs are dirty */
1811     mstatus = env->mstatus | MSTATUS_XS;
1812     write_mstatus(env, csrno, mstatus);
1813     return RISCV_EXCP_NONE;
1814 }
1815 
1816 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1817                                    target_ulong *val)
1818 {
1819     *val = env->upmbase;
1820     return RISCV_EXCP_NONE;
1821 }
1822 
1823 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1824                                     target_ulong val)
1825 {
1826     uint64_t mstatus;
1827 
1828     /* if pm.current==0 we can't modify current PM CSRs */
1829     if (check_pm_current_disabled(env, csrno)) {
1830         return RISCV_EXCP_NONE;
1831     }
1832     env->upmbase = val;
1833     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1834         env->cur_pmbase = val;
1835     }
1836     env->mmte |= PM_EXT_DIRTY;
1837 
1838     /* Set XS and SD bits, since PM CSRs are dirty */
1839     mstatus = env->mstatus | MSTATUS_XS;
1840     write_mstatus(env, csrno, mstatus);
1841     return RISCV_EXCP_NONE;
1842 }
1843 
1844 #endif
1845 
1846 /*
1847  * riscv_csrrw - read and/or update control and status register
1848  *
1849  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1850  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1851  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1852  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1853  */
1854 
1855 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
1856                                                int csrno,
1857                                                bool write_mask,
1858                                                RISCVCPU *cpu)
1859 {
1860     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
1861     int read_only = get_field(csrno, 0xC00) == 3;
1862 #if !defined(CONFIG_USER_ONLY)
1863     int effective_priv = env->priv;
1864 
1865     if (riscv_has_ext(env, RVH) &&
1866         env->priv == PRV_S &&
1867         !riscv_cpu_virt_enabled(env)) {
1868         /*
1869          * We are in S mode without virtualisation, therefore we are in HS Mode.
1870          * Add 1 to the effective privledge level to allow us to access the
1871          * Hypervisor CSRs.
1872          */
1873         effective_priv++;
1874     }
1875 
1876     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1877         return RISCV_EXCP_ILLEGAL_INST;
1878     }
1879 #endif
1880     if (write_mask && read_only) {
1881         return RISCV_EXCP_ILLEGAL_INST;
1882     }
1883 
1884     /* ensure the CSR extension is enabled. */
1885     if (!cpu->cfg.ext_icsr) {
1886         return RISCV_EXCP_ILLEGAL_INST;
1887     }
1888 
1889     /* check predicate */
1890     if (!csr_ops[csrno].predicate) {
1891         return RISCV_EXCP_ILLEGAL_INST;
1892     }
1893 
1894     return csr_ops[csrno].predicate(env, csrno);
1895 }
1896 
1897 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
1898                                        target_ulong *ret_value,
1899                                        target_ulong new_value,
1900                                        target_ulong write_mask)
1901 {
1902     RISCVException ret;
1903     target_ulong old_value;
1904 
1905     /* execute combined read/write operation if it exists */
1906     if (csr_ops[csrno].op) {
1907         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1908     }
1909 
1910     /* if no accessor exists then return failure */
1911     if (!csr_ops[csrno].read) {
1912         return RISCV_EXCP_ILLEGAL_INST;
1913     }
1914     /* read old value */
1915     ret = csr_ops[csrno].read(env, csrno, &old_value);
1916     if (ret != RISCV_EXCP_NONE) {
1917         return ret;
1918     }
1919 
1920     /* write value if writable and write mask set, otherwise drop writes */
1921     if (write_mask) {
1922         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1923         if (csr_ops[csrno].write) {
1924             ret = csr_ops[csrno].write(env, csrno, new_value);
1925             if (ret != RISCV_EXCP_NONE) {
1926                 return ret;
1927             }
1928         }
1929     }
1930 
1931     /* return old value */
1932     if (ret_value) {
1933         *ret_value = old_value;
1934     }
1935 
1936     return RISCV_EXCP_NONE;
1937 }
1938 
1939 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1940                            target_ulong *ret_value,
1941                            target_ulong new_value, target_ulong write_mask)
1942 {
1943     RISCVCPU *cpu = env_archcpu(env);
1944 
1945     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
1946     if (ret != RISCV_EXCP_NONE) {
1947         return ret;
1948     }
1949 
1950     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
1951 }
1952 
1953 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
1954                                         Int128 *ret_value,
1955                                         Int128 new_value,
1956                                         Int128 write_mask)
1957 {
1958     RISCVException ret;
1959     Int128 old_value;
1960 
1961     /* read old value */
1962     ret = csr_ops[csrno].read128(env, csrno, &old_value);
1963     if (ret != RISCV_EXCP_NONE) {
1964         return ret;
1965     }
1966 
1967     /* write value if writable and write mask set, otherwise drop writes */
1968     if (int128_nz(write_mask)) {
1969         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
1970                               int128_and(new_value, write_mask));
1971         if (csr_ops[csrno].write128) {
1972             ret = csr_ops[csrno].write128(env, csrno, new_value);
1973             if (ret != RISCV_EXCP_NONE) {
1974                 return ret;
1975             }
1976         } else if (csr_ops[csrno].write) {
1977             /* avoids having to write wrappers for all registers */
1978             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
1979             if (ret != RISCV_EXCP_NONE) {
1980                 return ret;
1981             }
1982         }
1983     }
1984 
1985     /* return old value */
1986     if (ret_value) {
1987         *ret_value = old_value;
1988     }
1989 
1990     return RISCV_EXCP_NONE;
1991 }
1992 
1993 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
1994                                 Int128 *ret_value,
1995                                 Int128 new_value, Int128 write_mask)
1996 {
1997     RISCVException ret;
1998     RISCVCPU *cpu = env_archcpu(env);
1999 
2000     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
2001     if (ret != RISCV_EXCP_NONE) {
2002         return ret;
2003     }
2004 
2005     if (csr_ops[csrno].read128) {
2006         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
2007     }
2008 
2009     /*
2010      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
2011      * at all defined.
2012      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
2013      * significant), for those, this fallback is correctly handling the accesses
2014      */
2015     target_ulong old_value;
2016     ret = riscv_csrrw_do64(env, csrno, &old_value,
2017                            int128_getlo(new_value),
2018                            int128_getlo(write_mask));
2019     if (ret == RISCV_EXCP_NONE && ret_value) {
2020         *ret_value = int128_make64(old_value);
2021     }
2022     return ret;
2023 }
2024 
2025 /*
2026  * Debugger support.  If not in user mode, set env->debugger before the
2027  * riscv_csrrw call and clear it after the call.
2028  */
2029 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
2030                                  target_ulong *ret_value,
2031                                  target_ulong new_value,
2032                                  target_ulong write_mask)
2033 {
2034     RISCVException ret;
2035 #if !defined(CONFIG_USER_ONLY)
2036     env->debugger = true;
2037 #endif
2038     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
2039 #if !defined(CONFIG_USER_ONLY)
2040     env->debugger = false;
2041 #endif
2042     return ret;
2043 }
2044 
2045 /* Control and Status Register function table */
2046 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
2047     /* User Floating-Point CSRs */
2048     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
2049     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
2050     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
2051     /* Vector CSRs */
2052     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
2053     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
2054     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
2055     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
2056     [CSR_VL]       = { "vl",       vs,     read_vl                    },
2057     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2058     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2059     /* User Timers and Counters */
2060     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2061     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2062     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2063     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2064 
2065     /*
2066      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2067      * rdtime callback is not provided by machine/platform emulation.
2068      */
2069     [CSR_TIME]  = { "time",  ctr,   read_time  },
2070     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2071 
2072 #if !defined(CONFIG_USER_ONLY)
2073     /* Machine Timers and Counters */
2074     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2075     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2076     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2077     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2078 
2079     /* Machine Information Registers */
2080     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2081     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2082     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2083     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2084 
2085     /* Machine Trap Setup */
2086     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2087                                                read_mstatus_i128                   },
2088     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2089                                                read_misa_i128                      },
2090     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
2091     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2092     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
2093     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2094     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2095 
2096     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2097 
2098     /* Machine Trap Handling */
2099     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2100                                          read_mscratch_i128, write_mscratch_i128   },
2101     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2102     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2103     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2104     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2105 
2106     /* Supervisor Trap Setup */
2107     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2108                                               read_sstatus_i128                 },
2109     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
2110     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2111     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2112 
2113     /* Supervisor Trap Handling */
2114     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2115                                           read_sscratch_i128, write_sscratch_i128  },
2116     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2117     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2118     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2119     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2120 
2121     /* Supervisor Protection and Translation */
2122     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2123 
2124     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2125     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2126     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
2127     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2128     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2129     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
2130     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2131     [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
2132     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2133     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2134     [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
2135     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2136     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2137     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2138 
2139     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2140     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2141     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
2142     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2143     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2144     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2145     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2146     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2147     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2148 
2149     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2150     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2151 
2152     /* Physical Memory Protection */
2153     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2154     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2155     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2156     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2157     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2158     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2159     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2160     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2161     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2162     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2163     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2164     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2165     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2166     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2167     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2168     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2169     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2170     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2171     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2172     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2173     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2174 
2175     /* User Pointer Masking */
2176     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2177     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2178     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2179     /* Machine Pointer Masking */
2180     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2181     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2182     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2183     /* Supervisor Pointer Masking */
2184     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2185     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2186     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2187 
2188     /* Performance Counters */
2189     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2190     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2191     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2192     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2193     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2194     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2195     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2196     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2197     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2198     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2199     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2200     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2201     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2202     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2203     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2204     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2205     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2206     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2207     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2208     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2209     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2210     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2211     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2212     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2213     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2214     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2215     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2216     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2217     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2218 
2219     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2220     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2221     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2222     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2223     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2224     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2225     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2226     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2227     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2228     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2229     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2230     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2231     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2232     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2233     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2234     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2235     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2236     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2237     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2238     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2239     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2240     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2241     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2242     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2243     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2244     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2245     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2246     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2247     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2248 
2249     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2250     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2251     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2252     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2253     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2254     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2255     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2256     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2257     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2258     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2259     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2260     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2261     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2262     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2263     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2264     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2265     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2266     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2267     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2268     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2269     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2270     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2271     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2272     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2273     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2274     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2275     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2276     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2277     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2278 
2279     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2280     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2281     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2282     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2283     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2284     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2285     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2286     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2287     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2288     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2289     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2290     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2291     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2292     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2293     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2294     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2295     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2296     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2297     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2298     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2299     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2300     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2301     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2302     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2303     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2304     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2305     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2306     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2307     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2308 
2309     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2310     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2311     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2312     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2313     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2314     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2315     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2316     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2317     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2318     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2319     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2320     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2321     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2322     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2323     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2324     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2325     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2326     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2327     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2328     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2329     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2330     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2331     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2332     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2333     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2334     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2335     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2336     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2337     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2338 #endif /* !CONFIG_USER_ONLY */
2339 };
2340