1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "cpu.h" 23 #include "qemu/main-loop.h" 24 #include "exec/exec-all.h" 25 26 /* CSR function table */ 27 static riscv_csr_operations csr_ops[]; 28 29 /* CSR function table constants */ 30 enum { 31 CSR_TABLE_SIZE = 0x1000 32 }; 33 34 /* CSR function table public API */ 35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 36 { 37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 38 } 39 40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 41 { 42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 43 } 44 45 /* Predicates */ 46 static int fs(CPURISCVState *env, int csrno) 47 { 48 #if !defined(CONFIG_USER_ONLY) 49 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 50 return -1; 51 } 52 #endif 53 return 0; 54 } 55 56 static int ctr(CPURISCVState *env, int csrno) 57 { 58 #if !defined(CONFIG_USER_ONLY) 59 CPUState *cs = env_cpu(env); 60 RISCVCPU *cpu = RISCV_CPU(cs); 61 uint32_t ctr_en = ~0u; 62 63 if (!cpu->cfg.ext_counters) { 64 /* The Counters extensions is not enabled */ 65 return -1; 66 } 67 68 /* 69 * The counters are always enabled at run time on newer priv specs, as the 70 * CSR has changed from controlling that the counters can be read to 71 * controlling that the counters increment. 72 */ 73 if (env->priv_ver > PRIV_VERSION_1_09_1) { 74 return 0; 75 } 76 77 if (env->priv < PRV_M) { 78 ctr_en &= env->mcounteren; 79 } 80 if (env->priv < PRV_S) { 81 ctr_en &= env->scounteren; 82 } 83 if (!(ctr_en & (1u << (csrno & 31)))) { 84 return -1; 85 } 86 #endif 87 return 0; 88 } 89 90 #if !defined(CONFIG_USER_ONLY) 91 static int any(CPURISCVState *env, int csrno) 92 { 93 return 0; 94 } 95 96 static int smode(CPURISCVState *env, int csrno) 97 { 98 return -!riscv_has_ext(env, RVS); 99 } 100 101 static int hmode(CPURISCVState *env, int csrno) 102 { 103 if (riscv_has_ext(env, RVS) && 104 riscv_has_ext(env, RVH)) { 105 /* Hypervisor extension is supported */ 106 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 107 env->priv == PRV_M) { 108 return 0; 109 } 110 } 111 112 return -1; 113 } 114 115 static int pmp(CPURISCVState *env, int csrno) 116 { 117 return -!riscv_feature(env, RISCV_FEATURE_PMP); 118 } 119 #endif 120 121 /* User Floating-Point CSRs */ 122 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) 123 { 124 #if !defined(CONFIG_USER_ONLY) 125 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 126 return -1; 127 } 128 #endif 129 *val = riscv_cpu_get_fflags(env); 130 return 0; 131 } 132 133 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) 134 { 135 #if !defined(CONFIG_USER_ONLY) 136 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 137 return -1; 138 } 139 env->mstatus |= MSTATUS_FS; 140 #endif 141 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 142 return 0; 143 } 144 145 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) 146 { 147 #if !defined(CONFIG_USER_ONLY) 148 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 149 return -1; 150 } 151 #endif 152 *val = env->frm; 153 return 0; 154 } 155 156 static int write_frm(CPURISCVState *env, int csrno, target_ulong val) 157 { 158 #if !defined(CONFIG_USER_ONLY) 159 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 160 return -1; 161 } 162 env->mstatus |= MSTATUS_FS; 163 #endif 164 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 165 return 0; 166 } 167 168 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) 169 { 170 #if !defined(CONFIG_USER_ONLY) 171 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 172 return -1; 173 } 174 #endif 175 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 176 | (env->frm << FSR_RD_SHIFT); 177 return 0; 178 } 179 180 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) 181 { 182 #if !defined(CONFIG_USER_ONLY) 183 if (!env->debugger && !riscv_cpu_fp_enabled(env)) { 184 return -1; 185 } 186 env->mstatus |= MSTATUS_FS; 187 #endif 188 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 189 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 190 return 0; 191 } 192 193 /* User Timers and Counters */ 194 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) 195 { 196 #if !defined(CONFIG_USER_ONLY) 197 if (use_icount) { 198 *val = cpu_get_icount(); 199 } else { 200 *val = cpu_get_host_ticks(); 201 } 202 #else 203 *val = cpu_get_host_ticks(); 204 #endif 205 return 0; 206 } 207 208 #if defined(TARGET_RISCV32) 209 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val) 210 { 211 #if !defined(CONFIG_USER_ONLY) 212 if (use_icount) { 213 *val = cpu_get_icount() >> 32; 214 } else { 215 *val = cpu_get_host_ticks() >> 32; 216 } 217 #else 218 *val = cpu_get_host_ticks() >> 32; 219 #endif 220 return 0; 221 } 222 #endif /* TARGET_RISCV32 */ 223 224 #if defined(CONFIG_USER_ONLY) 225 static int read_time(CPURISCVState *env, int csrno, target_ulong *val) 226 { 227 *val = cpu_get_host_ticks(); 228 return 0; 229 } 230 231 #if defined(TARGET_RISCV32) 232 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val) 233 { 234 *val = cpu_get_host_ticks() >> 32; 235 return 0; 236 } 237 #endif 238 239 #else /* CONFIG_USER_ONLY */ 240 241 /* Machine constants */ 242 243 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) 244 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) 245 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) 246 247 static const target_ulong delegable_ints = S_MODE_INTERRUPTS | 248 VS_MODE_INTERRUPTS; 249 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 250 VS_MODE_INTERRUPTS; 251 static const target_ulong delegable_excps = 252 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | 253 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | 254 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | 255 (1ULL << (RISCV_EXCP_BREAKPOINT)) | 256 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | 257 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | 258 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | 259 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | 260 (1ULL << (RISCV_EXCP_U_ECALL)) | 261 (1ULL << (RISCV_EXCP_S_ECALL)) | 262 (1ULL << (RISCV_EXCP_VS_ECALL)) | 263 (1ULL << (RISCV_EXCP_M_ECALL)) | 264 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | 265 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | 266 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | 267 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 268 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 269 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); 270 static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE | 271 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 272 SSTATUS_SUM | SSTATUS_SD; 273 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 274 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 275 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; 276 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 277 static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 278 static const target_ulong vsip_writable_mask = MIP_VSSIP; 279 280 #if defined(TARGET_RISCV32) 281 static const char valid_vm_1_09[16] = { 282 [VM_1_09_MBARE] = 1, 283 [VM_1_09_SV32] = 1, 284 }; 285 static const char valid_vm_1_10[16] = { 286 [VM_1_10_MBARE] = 1, 287 [VM_1_10_SV32] = 1 288 }; 289 #elif defined(TARGET_RISCV64) 290 static const char valid_vm_1_09[16] = { 291 [VM_1_09_MBARE] = 1, 292 [VM_1_09_SV39] = 1, 293 [VM_1_09_SV48] = 1, 294 }; 295 static const char valid_vm_1_10[16] = { 296 [VM_1_10_MBARE] = 1, 297 [VM_1_10_SV39] = 1, 298 [VM_1_10_SV48] = 1, 299 [VM_1_10_SV57] = 1 300 }; 301 #endif /* CONFIG_USER_ONLY */ 302 303 /* Machine Information Registers */ 304 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val) 305 { 306 return *val = 0; 307 } 308 309 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) 310 { 311 *val = env->mhartid; 312 return 0; 313 } 314 315 /* Machine Trap Setup */ 316 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val) 317 { 318 *val = env->mstatus; 319 return 0; 320 } 321 322 static int validate_vm(CPURISCVState *env, target_ulong vm) 323 { 324 return (env->priv_ver >= PRIV_VERSION_1_10_0) ? 325 valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; 326 } 327 328 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 329 { 330 target_ulong mstatus = env->mstatus; 331 target_ulong mask = 0; 332 int dirty; 333 334 /* flush tlb on mstatus fields that affect VM */ 335 if (env->priv_ver <= PRIV_VERSION_1_09_1) { 336 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | 337 MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { 338 tlb_flush(env_cpu(env)); 339 } 340 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 341 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 342 MSTATUS_MPP | MSTATUS_MXR | 343 (validate_vm(env, get_field(val, MSTATUS_VM)) ? 344 MSTATUS_VM : 0); 345 } 346 if (env->priv_ver >= PRIV_VERSION_1_10_0) { 347 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 348 MSTATUS_MPRV | MSTATUS_SUM)) { 349 tlb_flush(env_cpu(env)); 350 } 351 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 352 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | 353 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 354 MSTATUS_TW; 355 #if defined(TARGET_RISCV64) 356 /* 357 * RV32: MPV and MTL are not in mstatus. The current plan is to 358 * add them to mstatush. For now, we just don't support it. 359 */ 360 mask |= MSTATUS_MTL | MSTATUS_MPV; 361 #endif 362 } 363 364 mstatus = (mstatus & ~mask) | (val & mask); 365 366 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | 367 ((mstatus & MSTATUS_XS) == MSTATUS_XS); 368 mstatus = set_field(mstatus, MSTATUS_SD, dirty); 369 env->mstatus = mstatus; 370 371 return 0; 372 } 373 374 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val) 375 { 376 *val = env->misa; 377 return 0; 378 } 379 380 static int write_misa(CPURISCVState *env, int csrno, target_ulong val) 381 { 382 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 383 /* drop write to misa */ 384 return 0; 385 } 386 387 /* 'I' or 'E' must be present */ 388 if (!(val & (RVI | RVE))) { 389 /* It is not, drop write to misa */ 390 return 0; 391 } 392 393 /* 'E' excludes all other extensions */ 394 if (val & RVE) { 395 /* when we support 'E' we can do "val = RVE;" however 396 * for now we just drop writes if 'E' is present. 397 */ 398 return 0; 399 } 400 401 /* Mask extensions that are not supported by this hart */ 402 val &= env->misa_mask; 403 404 /* Mask extensions that are not supported by QEMU */ 405 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 406 407 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 408 if ((val & RVD) && !(val & RVF)) { 409 val &= ~RVD; 410 } 411 412 /* Suppress 'C' if next instruction is not aligned 413 * TODO: this should check next_pc 414 */ 415 if ((val & RVC) && (GETPC() & ~3) != 0) { 416 val &= ~RVC; 417 } 418 419 /* misa.MXL writes are not supported by QEMU */ 420 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL); 421 422 /* flush translation cache */ 423 if (val != env->misa) { 424 tb_flush(env_cpu(env)); 425 } 426 427 env->misa = val; 428 429 return 0; 430 } 431 432 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val) 433 { 434 *val = env->medeleg; 435 return 0; 436 } 437 438 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val) 439 { 440 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); 441 return 0; 442 } 443 444 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) 445 { 446 *val = env->mideleg; 447 return 0; 448 } 449 450 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) 451 { 452 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); 453 if (riscv_has_ext(env, RVH)) { 454 env->mideleg |= VS_MODE_INTERRUPTS; 455 } 456 return 0; 457 } 458 459 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val) 460 { 461 *val = env->mie; 462 return 0; 463 } 464 465 static int write_mie(CPURISCVState *env, int csrno, target_ulong val) 466 { 467 env->mie = (env->mie & ~all_ints) | (val & all_ints); 468 return 0; 469 } 470 471 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) 472 { 473 *val = env->mtvec; 474 return 0; 475 } 476 477 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val) 478 { 479 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 480 if ((val & 3) < 2) { 481 env->mtvec = val; 482 } else { 483 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 484 } 485 return 0; 486 } 487 488 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) 489 { 490 if (env->priv_ver < PRIV_VERSION_1_10_0) { 491 return -1; 492 } 493 *val = env->mcounteren; 494 return 0; 495 } 496 497 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) 498 { 499 if (env->priv_ver < PRIV_VERSION_1_10_0) { 500 return -1; 501 } 502 env->mcounteren = val; 503 return 0; 504 } 505 506 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ 507 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val) 508 { 509 if (env->priv_ver > PRIV_VERSION_1_09_1 510 && env->priv_ver < PRIV_VERSION_1_11_0) { 511 return -1; 512 } 513 *val = env->mcounteren; 514 return 0; 515 } 516 517 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ 518 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val) 519 { 520 if (env->priv_ver > PRIV_VERSION_1_09_1 521 && env->priv_ver < PRIV_VERSION_1_11_0) { 522 return -1; 523 } 524 env->mcounteren = val; 525 return 0; 526 } 527 528 static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val) 529 { 530 if (env->priv_ver > PRIV_VERSION_1_09_1) { 531 return -1; 532 } 533 *val = env->scounteren; 534 return 0; 535 } 536 537 static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val) 538 { 539 if (env->priv_ver > PRIV_VERSION_1_09_1) { 540 return -1; 541 } 542 env->scounteren = val; 543 return 0; 544 } 545 546 /* Machine Trap Handling */ 547 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) 548 { 549 *val = env->mscratch; 550 return 0; 551 } 552 553 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val) 554 { 555 env->mscratch = val; 556 return 0; 557 } 558 559 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val) 560 { 561 *val = env->mepc; 562 return 0; 563 } 564 565 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val) 566 { 567 env->mepc = val; 568 return 0; 569 } 570 571 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val) 572 { 573 *val = env->mcause; 574 return 0; 575 } 576 577 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val) 578 { 579 env->mcause = val; 580 return 0; 581 } 582 583 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 584 { 585 *val = env->mbadaddr; 586 return 0; 587 } 588 589 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) 590 { 591 env->mbadaddr = val; 592 return 0; 593 } 594 595 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, 596 target_ulong new_value, target_ulong write_mask) 597 { 598 RISCVCPU *cpu = env_archcpu(env); 599 /* Allow software control of delegable interrupts not claimed by hardware */ 600 target_ulong mask = write_mask & delegable_ints & ~env->miclaim; 601 uint32_t old_mip; 602 603 if (mask) { 604 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); 605 } else { 606 old_mip = env->mip; 607 } 608 609 if (ret_value) { 610 *ret_value = old_mip; 611 } 612 613 return 0; 614 } 615 616 /* Supervisor Trap Setup */ 617 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) 618 { 619 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 620 sstatus_v1_10_mask : sstatus_v1_9_mask); 621 *val = env->mstatus & mask; 622 return 0; 623 } 624 625 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) 626 { 627 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ? 628 sstatus_v1_10_mask : sstatus_v1_9_mask); 629 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 630 return write_mstatus(env, CSR_MSTATUS, newval); 631 } 632 633 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val) 634 { 635 if (riscv_cpu_virt_enabled(env)) { 636 /* Tell the guest the VS bits, shifted to the S bit locations */ 637 *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1; 638 } else { 639 *val = env->mie & env->mideleg; 640 } 641 return 0; 642 } 643 644 static int write_sie(CPURISCVState *env, int csrno, target_ulong val) 645 { 646 target_ulong newval; 647 648 if (riscv_cpu_virt_enabled(env)) { 649 /* Shift the guests S bits to VS */ 650 newval = (env->mie & ~VS_MODE_INTERRUPTS) | 651 ((val << 1) & VS_MODE_INTERRUPTS); 652 } else { 653 newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS); 654 } 655 656 return write_mie(env, CSR_MIE, newval); 657 } 658 659 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val) 660 { 661 *val = env->stvec; 662 return 0; 663 } 664 665 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val) 666 { 667 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 668 if ((val & 3) < 2) { 669 env->stvec = val; 670 } else { 671 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 672 } 673 return 0; 674 } 675 676 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val) 677 { 678 if (env->priv_ver < PRIV_VERSION_1_10_0) { 679 return -1; 680 } 681 *val = env->scounteren; 682 return 0; 683 } 684 685 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val) 686 { 687 if (env->priv_ver < PRIV_VERSION_1_10_0) { 688 return -1; 689 } 690 env->scounteren = val; 691 return 0; 692 } 693 694 /* Supervisor Trap Handling */ 695 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val) 696 { 697 *val = env->sscratch; 698 return 0; 699 } 700 701 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val) 702 { 703 env->sscratch = val; 704 return 0; 705 } 706 707 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val) 708 { 709 *val = env->sepc; 710 return 0; 711 } 712 713 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val) 714 { 715 env->sepc = val; 716 return 0; 717 } 718 719 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val) 720 { 721 *val = env->scause; 722 return 0; 723 } 724 725 static int write_scause(CPURISCVState *env, int csrno, target_ulong val) 726 { 727 env->scause = val; 728 return 0; 729 } 730 731 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val) 732 { 733 *val = env->sbadaddr; 734 return 0; 735 } 736 737 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val) 738 { 739 env->sbadaddr = val; 740 return 0; 741 } 742 743 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, 744 target_ulong new_value, target_ulong write_mask) 745 { 746 int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, 747 write_mask & env->mideleg & sip_writable_mask); 748 *ret_value &= env->mideleg; 749 return ret; 750 } 751 752 /* Supervisor Protection and Translation */ 753 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val) 754 { 755 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 756 *val = 0; 757 } else if (env->priv_ver >= PRIV_VERSION_1_10_0) { 758 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 759 return -1; 760 } else { 761 *val = env->satp; 762 } 763 } else { 764 *val = env->sptbr; 765 } 766 return 0; 767 } 768 769 static int write_satp(CPURISCVState *env, int csrno, target_ulong val) 770 { 771 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 772 return 0; 773 } 774 if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { 775 tlb_flush(env_cpu(env)); 776 env->sptbr = val & (((target_ulong) 777 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); 778 } 779 if (env->priv_ver >= PRIV_VERSION_1_10_0 && 780 validate_vm(env, get_field(val, SATP_MODE)) && 781 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) 782 { 783 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 784 return -1; 785 } else { 786 if((val ^ env->satp) & SATP_ASID) { 787 tlb_flush(env_cpu(env)); 788 } 789 env->satp = val; 790 } 791 } 792 return 0; 793 } 794 795 /* Hypervisor Extensions */ 796 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) 797 { 798 *val = env->hstatus; 799 return 0; 800 } 801 802 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val) 803 { 804 env->hstatus = val; 805 return 0; 806 } 807 808 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val) 809 { 810 *val = env->hedeleg; 811 return 0; 812 } 813 814 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) 815 { 816 env->hedeleg = val; 817 return 0; 818 } 819 820 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val) 821 { 822 *val = env->hideleg; 823 return 0; 824 } 825 826 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val) 827 { 828 env->hideleg = val; 829 return 0; 830 } 831 832 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, 833 target_ulong new_value, target_ulong write_mask) 834 { 835 int ret = rmw_mip(env, 0, ret_value, new_value, 836 write_mask & hip_writable_mask); 837 838 return ret; 839 } 840 841 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val) 842 { 843 *val = env->mie & VS_MODE_INTERRUPTS; 844 return 0; 845 } 846 847 static int write_hie(CPURISCVState *env, int csrno, target_ulong val) 848 { 849 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); 850 return write_mie(env, CSR_MIE, newval); 851 } 852 853 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val) 854 { 855 *val = env->hcounteren; 856 return 0; 857 } 858 859 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val) 860 { 861 env->hcounteren = val; 862 return 0; 863 } 864 865 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) 866 { 867 *val = env->htval; 868 return 0; 869 } 870 871 static int write_htval(CPURISCVState *env, int csrno, target_ulong val) 872 { 873 env->htval = val; 874 return 0; 875 } 876 877 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val) 878 { 879 *val = env->htinst; 880 return 0; 881 } 882 883 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val) 884 { 885 env->htinst = val; 886 return 0; 887 } 888 889 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) 890 { 891 *val = env->hgatp; 892 return 0; 893 } 894 895 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val) 896 { 897 env->hgatp = val; 898 return 0; 899 } 900 901 /* Virtual CSR Registers */ 902 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) 903 { 904 *val = env->vsstatus; 905 return 0; 906 } 907 908 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) 909 { 910 env->vsstatus = val; 911 return 0; 912 } 913 914 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value, 915 target_ulong new_value, target_ulong write_mask) 916 { 917 int ret = rmw_mip(env, 0, ret_value, new_value, 918 write_mask & env->mideleg & vsip_writable_mask); 919 return ret; 920 } 921 922 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) 923 { 924 *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS; 925 return 0; 926 } 927 928 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) 929 { 930 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP); 931 return write_mie(env, CSR_MIE, newval); 932 } 933 934 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 935 { 936 *val = env->vstvec; 937 return 0; 938 } 939 940 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) 941 { 942 env->vstvec = val; 943 return 0; 944 } 945 946 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) 947 { 948 *val = env->vsscratch; 949 return 0; 950 } 951 952 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) 953 { 954 env->vsscratch = val; 955 return 0; 956 } 957 958 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) 959 { 960 *val = env->vsepc; 961 return 0; 962 } 963 964 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) 965 { 966 env->vsepc = val; 967 return 0; 968 } 969 970 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) 971 { 972 *val = env->vscause; 973 return 0; 974 } 975 976 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) 977 { 978 env->vscause = val; 979 return 0; 980 } 981 982 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) 983 { 984 *val = env->vstval; 985 return 0; 986 } 987 988 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) 989 { 990 env->vstval = val; 991 return 0; 992 } 993 994 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) 995 { 996 *val = env->vsatp; 997 return 0; 998 } 999 1000 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) 1001 { 1002 env->vsatp = val; 1003 return 0; 1004 } 1005 1006 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val) 1007 { 1008 *val = env->mtval2; 1009 return 0; 1010 } 1011 1012 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val) 1013 { 1014 env->mtval2 = val; 1015 return 0; 1016 } 1017 1018 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val) 1019 { 1020 *val = env->mtinst; 1021 return 0; 1022 } 1023 1024 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val) 1025 { 1026 env->mtinst = val; 1027 return 0; 1028 } 1029 1030 /* Physical Memory Protection */ 1031 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) 1032 { 1033 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 1034 return 0; 1035 } 1036 1037 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val) 1038 { 1039 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 1040 return 0; 1041 } 1042 1043 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val) 1044 { 1045 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 1046 return 0; 1047 } 1048 1049 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) 1050 { 1051 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 1052 return 0; 1053 } 1054 1055 #endif 1056 1057 /* 1058 * riscv_csrrw - read and/or update control and status register 1059 * 1060 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 1061 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 1062 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 1063 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 1064 */ 1065 1066 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 1067 target_ulong new_value, target_ulong write_mask) 1068 { 1069 int ret; 1070 target_ulong old_value; 1071 RISCVCPU *cpu = env_archcpu(env); 1072 1073 /* check privileges and return -1 if check fails */ 1074 #if !defined(CONFIG_USER_ONLY) 1075 int effective_priv = env->priv; 1076 int read_only = get_field(csrno, 0xC00) == 3; 1077 1078 if (riscv_has_ext(env, RVH) && 1079 env->priv == PRV_S && 1080 !riscv_cpu_virt_enabled(env)) { 1081 /* 1082 * We are in S mode without virtualisation, therefore we are in HS Mode. 1083 * Add 1 to the effective privledge level to allow us to access the 1084 * Hypervisor CSRs. 1085 */ 1086 effective_priv++; 1087 } 1088 1089 if ((write_mask && read_only) || 1090 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { 1091 return -1; 1092 } 1093 #endif 1094 1095 /* ensure the CSR extension is enabled. */ 1096 if (!cpu->cfg.ext_icsr) { 1097 return -1; 1098 } 1099 1100 /* check predicate */ 1101 if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) { 1102 return -1; 1103 } 1104 1105 /* execute combined read/write operation if it exists */ 1106 if (csr_ops[csrno].op) { 1107 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 1108 } 1109 1110 /* if no accessor exists then return failure */ 1111 if (!csr_ops[csrno].read) { 1112 return -1; 1113 } 1114 1115 /* read old value */ 1116 ret = csr_ops[csrno].read(env, csrno, &old_value); 1117 if (ret < 0) { 1118 return ret; 1119 } 1120 1121 /* write value if writable and write mask set, otherwise drop writes */ 1122 if (write_mask) { 1123 new_value = (old_value & ~write_mask) | (new_value & write_mask); 1124 if (csr_ops[csrno].write) { 1125 ret = csr_ops[csrno].write(env, csrno, new_value); 1126 if (ret < 0) { 1127 return ret; 1128 } 1129 } 1130 } 1131 1132 /* return old value */ 1133 if (ret_value) { 1134 *ret_value = old_value; 1135 } 1136 1137 return 0; 1138 } 1139 1140 /* 1141 * Debugger support. If not in user mode, set env->debugger before the 1142 * riscv_csrrw call and clear it after the call. 1143 */ 1144 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value, 1145 target_ulong new_value, target_ulong write_mask) 1146 { 1147 int ret; 1148 #if !defined(CONFIG_USER_ONLY) 1149 env->debugger = true; 1150 #endif 1151 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 1152 #if !defined(CONFIG_USER_ONLY) 1153 env->debugger = false; 1154 #endif 1155 return ret; 1156 } 1157 1158 /* Control and Status Register function table */ 1159 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 1160 /* User Floating-Point CSRs */ 1161 [CSR_FFLAGS] = { fs, read_fflags, write_fflags }, 1162 [CSR_FRM] = { fs, read_frm, write_frm }, 1163 [CSR_FCSR] = { fs, read_fcsr, write_fcsr }, 1164 1165 /* User Timers and Counters */ 1166 [CSR_CYCLE] = { ctr, read_instret }, 1167 [CSR_INSTRET] = { ctr, read_instret }, 1168 #if defined(TARGET_RISCV32) 1169 [CSR_CYCLEH] = { ctr, read_instreth }, 1170 [CSR_INSTRETH] = { ctr, read_instreth }, 1171 #endif 1172 1173 /* User-level time CSRs are only available in linux-user 1174 * In privileged mode, the monitor emulates these CSRs */ 1175 #if defined(CONFIG_USER_ONLY) 1176 [CSR_TIME] = { ctr, read_time }, 1177 #if defined(TARGET_RISCV32) 1178 [CSR_TIMEH] = { ctr, read_timeh }, 1179 #endif 1180 #endif 1181 1182 #if !defined(CONFIG_USER_ONLY) 1183 /* Machine Timers and Counters */ 1184 [CSR_MCYCLE] = { any, read_instret }, 1185 [CSR_MINSTRET] = { any, read_instret }, 1186 #if defined(TARGET_RISCV32) 1187 [CSR_MCYCLEH] = { any, read_instreth }, 1188 [CSR_MINSTRETH] = { any, read_instreth }, 1189 #endif 1190 1191 /* Machine Information Registers */ 1192 [CSR_MVENDORID] = { any, read_zero }, 1193 [CSR_MARCHID] = { any, read_zero }, 1194 [CSR_MIMPID] = { any, read_zero }, 1195 [CSR_MHARTID] = { any, read_mhartid }, 1196 1197 /* Machine Trap Setup */ 1198 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus }, 1199 [CSR_MISA] = { any, read_misa, write_misa }, 1200 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg }, 1201 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg }, 1202 [CSR_MIE] = { any, read_mie, write_mie }, 1203 [CSR_MTVEC] = { any, read_mtvec, write_mtvec }, 1204 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren }, 1205 1206 /* Legacy Counter Setup (priv v1.9.1) */ 1207 [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren }, 1208 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren }, 1209 1210 /* Machine Trap Handling */ 1211 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch }, 1212 [CSR_MEPC] = { any, read_mepc, write_mepc }, 1213 [CSR_MCAUSE] = { any, read_mcause, write_mcause }, 1214 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr }, 1215 [CSR_MIP] = { any, NULL, NULL, rmw_mip }, 1216 1217 /* Supervisor Trap Setup */ 1218 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus }, 1219 [CSR_SIE] = { smode, read_sie, write_sie }, 1220 [CSR_STVEC] = { smode, read_stvec, write_stvec }, 1221 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren }, 1222 1223 /* Supervisor Trap Handling */ 1224 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch }, 1225 [CSR_SEPC] = { smode, read_sepc, write_sepc }, 1226 [CSR_SCAUSE] = { smode, read_scause, write_scause }, 1227 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr }, 1228 [CSR_SIP] = { smode, NULL, NULL, rmw_sip }, 1229 1230 /* Supervisor Protection and Translation */ 1231 [CSR_SATP] = { smode, read_satp, write_satp }, 1232 1233 [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, 1234 [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, 1235 [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, 1236 [CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, 1237 [CSR_HIE] = { hmode, read_hie, write_hie }, 1238 [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, 1239 [CSR_HTVAL] = { hmode, read_htval, write_htval }, 1240 [CSR_HTINST] = { hmode, read_htinst, write_htinst }, 1241 [CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, 1242 1243 [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus }, 1244 [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip }, 1245 [CSR_VSIE] = { hmode, read_vsie, write_vsie }, 1246 [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec }, 1247 [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch }, 1248 [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc }, 1249 [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause }, 1250 [CSR_VSTVAL] = { hmode, read_vstval, write_vstval }, 1251 [CSR_VSATP] = { hmode, read_vsatp, write_vsatp }, 1252 1253 [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 }, 1254 [CSR_MTINST] = { hmode, read_mtinst, write_mtinst }, 1255 1256 /* Physical Memory Protection */ 1257 [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg }, 1258 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, 1259 1260 /* Performance Counters */ 1261 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, 1262 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero }, 1263 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero }, 1264 #if defined(TARGET_RISCV32) 1265 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero }, 1266 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero }, 1267 #endif 1268 #endif /* !CONFIG_USER_ONLY */ 1269 }; 1270