xref: /openbmc/qemu/target/riscv/csr.c (revision d0237b4d) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 
26 /* CSR function table public API */
27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28 {
29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30 }
31 
32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33 {
34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35 }
36 
37 /* Predicates */
38 static RISCVException fs(CPURISCVState *env, int csrno)
39 {
40 #if !defined(CONFIG_USER_ONLY)
41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
42         return RISCV_EXCP_ILLEGAL_INST;
43     }
44 #endif
45     return RISCV_EXCP_NONE;
46 }
47 
48 static RISCVException vs(CPURISCVState *env, int csrno)
49 {
50     CPUState *cs = env_cpu(env);
51     RISCVCPU *cpu = RISCV_CPU(cs);
52 
53     if (env->misa_ext & RVV ||
54         cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
55 #if !defined(CONFIG_USER_ONLY)
56         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
57             return RISCV_EXCP_ILLEGAL_INST;
58         }
59 #endif
60         return RISCV_EXCP_NONE;
61     }
62     return RISCV_EXCP_ILLEGAL_INST;
63 }
64 
65 static RISCVException ctr(CPURISCVState *env, int csrno)
66 {
67 #if !defined(CONFIG_USER_ONLY)
68     CPUState *cs = env_cpu(env);
69     RISCVCPU *cpu = RISCV_CPU(cs);
70 
71     if (!cpu->cfg.ext_counters) {
72         /* The Counters extensions is not enabled */
73         return RISCV_EXCP_ILLEGAL_INST;
74     }
75 
76     if (riscv_cpu_virt_enabled(env)) {
77         switch (csrno) {
78         case CSR_CYCLE:
79             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
80                 get_field(env->mcounteren, COUNTEREN_CY)) {
81                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
82             }
83             break;
84         case CSR_TIME:
85             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
86                 get_field(env->mcounteren, COUNTEREN_TM)) {
87                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
88             }
89             break;
90         case CSR_INSTRET:
91             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
92                 get_field(env->mcounteren, COUNTEREN_IR)) {
93                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
94             }
95             break;
96         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
97             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
98                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
99                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
100             }
101             break;
102         }
103         if (riscv_cpu_mxl(env) == MXL_RV32) {
104             switch (csrno) {
105             case CSR_CYCLEH:
106                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
107                     get_field(env->mcounteren, COUNTEREN_CY)) {
108                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
109                 }
110                 break;
111             case CSR_TIMEH:
112                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
113                     get_field(env->mcounteren, COUNTEREN_TM)) {
114                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
115                 }
116                 break;
117             case CSR_INSTRETH:
118                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
119                     get_field(env->mcounteren, COUNTEREN_IR)) {
120                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
121                 }
122                 break;
123             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
124                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
125                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
126                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
127                 }
128                 break;
129             }
130         }
131     }
132 #endif
133     return RISCV_EXCP_NONE;
134 }
135 
136 static RISCVException ctr32(CPURISCVState *env, int csrno)
137 {
138     if (riscv_cpu_mxl(env) != MXL_RV32) {
139         return RISCV_EXCP_ILLEGAL_INST;
140     }
141 
142     return ctr(env, csrno);
143 }
144 
145 #if !defined(CONFIG_USER_ONLY)
146 static RISCVException any(CPURISCVState *env, int csrno)
147 {
148     return RISCV_EXCP_NONE;
149 }
150 
151 static RISCVException any32(CPURISCVState *env, int csrno)
152 {
153     if (riscv_cpu_mxl(env) != MXL_RV32) {
154         return RISCV_EXCP_ILLEGAL_INST;
155     }
156 
157     return any(env, csrno);
158 
159 }
160 
161 static int aia_any(CPURISCVState *env, int csrno)
162 {
163     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
164         return RISCV_EXCP_ILLEGAL_INST;
165     }
166 
167     return any(env, csrno);
168 }
169 
170 static int aia_any32(CPURISCVState *env, int csrno)
171 {
172     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
173         return RISCV_EXCP_ILLEGAL_INST;
174     }
175 
176     return any32(env, csrno);
177 }
178 
179 static RISCVException smode(CPURISCVState *env, int csrno)
180 {
181     if (riscv_has_ext(env, RVS)) {
182         return RISCV_EXCP_NONE;
183     }
184 
185     return RISCV_EXCP_ILLEGAL_INST;
186 }
187 
188 static int smode32(CPURISCVState *env, int csrno)
189 {
190     if (riscv_cpu_mxl(env) != MXL_RV32) {
191         return RISCV_EXCP_ILLEGAL_INST;
192     }
193 
194     return smode(env, csrno);
195 }
196 
197 static int aia_smode32(CPURISCVState *env, int csrno)
198 {
199     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
200         return RISCV_EXCP_ILLEGAL_INST;
201     }
202 
203     return smode32(env, csrno);
204 }
205 
206 static RISCVException hmode(CPURISCVState *env, int csrno)
207 {
208     if (riscv_has_ext(env, RVS) &&
209         riscv_has_ext(env, RVH)) {
210         /* Hypervisor extension is supported */
211         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
212             env->priv == PRV_M) {
213             return RISCV_EXCP_NONE;
214         } else {
215             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
216         }
217     }
218 
219     return RISCV_EXCP_ILLEGAL_INST;
220 }
221 
222 static RISCVException hmode32(CPURISCVState *env, int csrno)
223 {
224     if (riscv_cpu_mxl(env) != MXL_RV32) {
225         if (!riscv_cpu_virt_enabled(env)) {
226             return RISCV_EXCP_ILLEGAL_INST;
227         } else {
228             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
229         }
230     }
231 
232     return hmode(env, csrno);
233 
234 }
235 
236 /* Checks if PointerMasking registers could be accessed */
237 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
238 {
239     /* Check if j-ext is present */
240     if (riscv_has_ext(env, RVJ)) {
241         return RISCV_EXCP_NONE;
242     }
243     return RISCV_EXCP_ILLEGAL_INST;
244 }
245 
246 static int aia_hmode(CPURISCVState *env, int csrno)
247 {
248     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
249         return RISCV_EXCP_ILLEGAL_INST;
250      }
251 
252      return hmode(env, csrno);
253 }
254 
255 static int aia_hmode32(CPURISCVState *env, int csrno)
256 {
257     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
258         return RISCV_EXCP_ILLEGAL_INST;
259     }
260 
261     return hmode32(env, csrno);
262 }
263 
264 static RISCVException pmp(CPURISCVState *env, int csrno)
265 {
266     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
267         return RISCV_EXCP_NONE;
268     }
269 
270     return RISCV_EXCP_ILLEGAL_INST;
271 }
272 
273 static RISCVException epmp(CPURISCVState *env, int csrno)
274 {
275     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
276         return RISCV_EXCP_NONE;
277     }
278 
279     return RISCV_EXCP_ILLEGAL_INST;
280 }
281 #endif
282 
283 /* User Floating-Point CSRs */
284 static RISCVException read_fflags(CPURISCVState *env, int csrno,
285                                   target_ulong *val)
286 {
287     *val = riscv_cpu_get_fflags(env);
288     return RISCV_EXCP_NONE;
289 }
290 
291 static RISCVException write_fflags(CPURISCVState *env, int csrno,
292                                    target_ulong val)
293 {
294 #if !defined(CONFIG_USER_ONLY)
295     env->mstatus |= MSTATUS_FS;
296 #endif
297     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
298     return RISCV_EXCP_NONE;
299 }
300 
301 static RISCVException read_frm(CPURISCVState *env, int csrno,
302                                target_ulong *val)
303 {
304     *val = env->frm;
305     return RISCV_EXCP_NONE;
306 }
307 
308 static RISCVException write_frm(CPURISCVState *env, int csrno,
309                                 target_ulong val)
310 {
311 #if !defined(CONFIG_USER_ONLY)
312     env->mstatus |= MSTATUS_FS;
313 #endif
314     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
315     return RISCV_EXCP_NONE;
316 }
317 
318 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
319                                 target_ulong *val)
320 {
321     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
322         | (env->frm << FSR_RD_SHIFT);
323     return RISCV_EXCP_NONE;
324 }
325 
326 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
327                                  target_ulong val)
328 {
329 #if !defined(CONFIG_USER_ONLY)
330     env->mstatus |= MSTATUS_FS;
331 #endif
332     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
333     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
334     return RISCV_EXCP_NONE;
335 }
336 
337 static RISCVException read_vtype(CPURISCVState *env, int csrno,
338                                  target_ulong *val)
339 {
340     uint64_t vill;
341     switch (env->xl) {
342     case MXL_RV32:
343         vill = (uint32_t)env->vill << 31;
344         break;
345     case MXL_RV64:
346         vill = (uint64_t)env->vill << 63;
347         break;
348     default:
349         g_assert_not_reached();
350     }
351     *val = (target_ulong)vill | env->vtype;
352     return RISCV_EXCP_NONE;
353 }
354 
355 static RISCVException read_vl(CPURISCVState *env, int csrno,
356                               target_ulong *val)
357 {
358     *val = env->vl;
359     return RISCV_EXCP_NONE;
360 }
361 
362 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
363 {
364     *val = env_archcpu(env)->cfg.vlen >> 3;
365     return RISCV_EXCP_NONE;
366 }
367 
368 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
369                                 target_ulong *val)
370 {
371     *val = env->vxrm;
372     return RISCV_EXCP_NONE;
373 }
374 
375 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
376                                  target_ulong val)
377 {
378 #if !defined(CONFIG_USER_ONLY)
379     env->mstatus |= MSTATUS_VS;
380 #endif
381     env->vxrm = val;
382     return RISCV_EXCP_NONE;
383 }
384 
385 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
386                                  target_ulong *val)
387 {
388     *val = env->vxsat;
389     return RISCV_EXCP_NONE;
390 }
391 
392 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
393                                   target_ulong val)
394 {
395 #if !defined(CONFIG_USER_ONLY)
396     env->mstatus |= MSTATUS_VS;
397 #endif
398     env->vxsat = val;
399     return RISCV_EXCP_NONE;
400 }
401 
402 static RISCVException read_vstart(CPURISCVState *env, int csrno,
403                                   target_ulong *val)
404 {
405     *val = env->vstart;
406     return RISCV_EXCP_NONE;
407 }
408 
409 static RISCVException write_vstart(CPURISCVState *env, int csrno,
410                                    target_ulong val)
411 {
412 #if !defined(CONFIG_USER_ONLY)
413     env->mstatus |= MSTATUS_VS;
414 #endif
415     /*
416      * The vstart CSR is defined to have only enough writable bits
417      * to hold the largest element index, i.e. lg2(VLEN) bits.
418      */
419     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
420     return RISCV_EXCP_NONE;
421 }
422 
423 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
424 {
425     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
426     return RISCV_EXCP_NONE;
427 }
428 
429 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
430 {
431 #if !defined(CONFIG_USER_ONLY)
432     env->mstatus |= MSTATUS_VS;
433 #endif
434     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
435     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
436     return RISCV_EXCP_NONE;
437 }
438 
439 /* User Timers and Counters */
440 static RISCVException read_instret(CPURISCVState *env, int csrno,
441                                    target_ulong *val)
442 {
443 #if !defined(CONFIG_USER_ONLY)
444     if (icount_enabled()) {
445         *val = icount_get();
446     } else {
447         *val = cpu_get_host_ticks();
448     }
449 #else
450     *val = cpu_get_host_ticks();
451 #endif
452     return RISCV_EXCP_NONE;
453 }
454 
455 static RISCVException read_instreth(CPURISCVState *env, int csrno,
456                                     target_ulong *val)
457 {
458 #if !defined(CONFIG_USER_ONLY)
459     if (icount_enabled()) {
460         *val = icount_get() >> 32;
461     } else {
462         *val = cpu_get_host_ticks() >> 32;
463     }
464 #else
465     *val = cpu_get_host_ticks() >> 32;
466 #endif
467     return RISCV_EXCP_NONE;
468 }
469 
470 #if defined(CONFIG_USER_ONLY)
471 static RISCVException read_time(CPURISCVState *env, int csrno,
472                                 target_ulong *val)
473 {
474     *val = cpu_get_host_ticks();
475     return RISCV_EXCP_NONE;
476 }
477 
478 static RISCVException read_timeh(CPURISCVState *env, int csrno,
479                                  target_ulong *val)
480 {
481     *val = cpu_get_host_ticks() >> 32;
482     return RISCV_EXCP_NONE;
483 }
484 
485 #else /* CONFIG_USER_ONLY */
486 
487 static RISCVException read_time(CPURISCVState *env, int csrno,
488                                 target_ulong *val)
489 {
490     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
491 
492     if (!env->rdtime_fn) {
493         return RISCV_EXCP_ILLEGAL_INST;
494     }
495 
496     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
497     return RISCV_EXCP_NONE;
498 }
499 
500 static RISCVException read_timeh(CPURISCVState *env, int csrno,
501                                  target_ulong *val)
502 {
503     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
504 
505     if (!env->rdtime_fn) {
506         return RISCV_EXCP_ILLEGAL_INST;
507     }
508 
509     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
510     return RISCV_EXCP_NONE;
511 }
512 
513 /* Machine constants */
514 
515 #define M_MODE_INTERRUPTS  ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
516 #define S_MODE_INTERRUPTS  ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP))
517 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
518 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
519 
520 static const uint64_t delegable_ints = S_MODE_INTERRUPTS |
521                                            VS_MODE_INTERRUPTS;
522 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS;
523 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
524                                      HS_MODE_INTERRUPTS;
525 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
526                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
527                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
528                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
529                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
530                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
531                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
532                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
533                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
534                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
535                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
536                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
537                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
538                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
539                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
540                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
541                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
542                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
543                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
544 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
545     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
546       (1ULL << (RISCV_EXCP_VS_ECALL)) |
547       (1ULL << (RISCV_EXCP_M_ECALL)) |
548       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
549       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
550       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
551       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
552 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
553     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
554     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
555 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
556 static const target_ulong hip_writable_mask = MIP_VSSIP;
557 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
558 static const target_ulong vsip_writable_mask = MIP_VSSIP;
559 
560 static const char valid_vm_1_10_32[16] = {
561     [VM_1_10_MBARE] = 1,
562     [VM_1_10_SV32] = 1
563 };
564 
565 static const char valid_vm_1_10_64[16] = {
566     [VM_1_10_MBARE] = 1,
567     [VM_1_10_SV39] = 1,
568     [VM_1_10_SV48] = 1,
569     [VM_1_10_SV57] = 1
570 };
571 
572 /* Machine Information Registers */
573 static RISCVException read_zero(CPURISCVState *env, int csrno,
574                                 target_ulong *val)
575 {
576     *val = 0;
577     return RISCV_EXCP_NONE;
578 }
579 
580 static RISCVException write_ignore(CPURISCVState *env, int csrno,
581                                    target_ulong val)
582 {
583     return RISCV_EXCP_NONE;
584 }
585 
586 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
587                                    target_ulong *val)
588 {
589     *val = env->mhartid;
590     return RISCV_EXCP_NONE;
591 }
592 
593 /* Machine Trap Setup */
594 
595 /* We do not store SD explicitly, only compute it on demand. */
596 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
597 {
598     if ((status & MSTATUS_FS) == MSTATUS_FS ||
599         (status & MSTATUS_VS) == MSTATUS_VS ||
600         (status & MSTATUS_XS) == MSTATUS_XS) {
601         switch (xl) {
602         case MXL_RV32:
603             return status | MSTATUS32_SD;
604         case MXL_RV64:
605             return status | MSTATUS64_SD;
606         case MXL_RV128:
607             return MSTATUSH128_SD;
608         default:
609             g_assert_not_reached();
610         }
611     }
612     return status;
613 }
614 
615 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
616                                    target_ulong *val)
617 {
618     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
619     return RISCV_EXCP_NONE;
620 }
621 
622 static int validate_vm(CPURISCVState *env, target_ulong vm)
623 {
624     if (riscv_cpu_mxl(env) == MXL_RV32) {
625         return valid_vm_1_10_32[vm & 0xf];
626     } else {
627         return valid_vm_1_10_64[vm & 0xf];
628     }
629 }
630 
631 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
632                                     target_ulong val)
633 {
634     uint64_t mstatus = env->mstatus;
635     uint64_t mask = 0;
636     RISCVMXL xl = riscv_cpu_mxl(env);
637 
638     /* flush tlb on mstatus fields that affect VM */
639     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
640             MSTATUS_MPRV | MSTATUS_SUM)) {
641         tlb_flush(env_cpu(env));
642     }
643     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
644         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
645         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
646         MSTATUS_TW | MSTATUS_VS;
647 
648     if (xl != MXL_RV32 || env->debugger) {
649         /*
650          * RV32: MPV and GVA are not in mstatus. The current plan is to
651          * add them to mstatush. For now, we just don't support it.
652          */
653         mask |= MSTATUS_MPV | MSTATUS_GVA;
654         if ((val & MSTATUS64_UXL) != 0) {
655             mask |= MSTATUS64_UXL;
656         }
657     }
658 
659     mstatus = (mstatus & ~mask) | (val & mask);
660 
661     if (xl > MXL_RV32) {
662         /* SXL field is for now read only */
663         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
664     }
665     env->mstatus = mstatus;
666     env->xl = cpu_recompute_xl(env);
667 
668     return RISCV_EXCP_NONE;
669 }
670 
671 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
672                                     target_ulong *val)
673 {
674     *val = env->mstatus >> 32;
675     return RISCV_EXCP_NONE;
676 }
677 
678 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
679                                      target_ulong val)
680 {
681     uint64_t valh = (uint64_t)val << 32;
682     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
683 
684     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
685         tlb_flush(env_cpu(env));
686     }
687 
688     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
689 
690     return RISCV_EXCP_NONE;
691 }
692 
693 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
694                                         Int128 *val)
695 {
696     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
697     return RISCV_EXCP_NONE;
698 }
699 
700 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
701                                      Int128 *val)
702 {
703     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
704     return RISCV_EXCP_NONE;
705 }
706 
707 static RISCVException read_misa(CPURISCVState *env, int csrno,
708                                 target_ulong *val)
709 {
710     target_ulong misa;
711 
712     switch (env->misa_mxl) {
713     case MXL_RV32:
714         misa = (target_ulong)MXL_RV32 << 30;
715         break;
716 #ifdef TARGET_RISCV64
717     case MXL_RV64:
718         misa = (target_ulong)MXL_RV64 << 62;
719         break;
720 #endif
721     default:
722         g_assert_not_reached();
723     }
724 
725     *val = misa | env->misa_ext;
726     return RISCV_EXCP_NONE;
727 }
728 
729 static RISCVException write_misa(CPURISCVState *env, int csrno,
730                                  target_ulong val)
731 {
732     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
733         /* drop write to misa */
734         return RISCV_EXCP_NONE;
735     }
736 
737     /* 'I' or 'E' must be present */
738     if (!(val & (RVI | RVE))) {
739         /* It is not, drop write to misa */
740         return RISCV_EXCP_NONE;
741     }
742 
743     /* 'E' excludes all other extensions */
744     if (val & RVE) {
745         /* when we support 'E' we can do "val = RVE;" however
746          * for now we just drop writes if 'E' is present.
747          */
748         return RISCV_EXCP_NONE;
749     }
750 
751     /*
752      * misa.MXL writes are not supported by QEMU.
753      * Drop writes to those bits.
754      */
755 
756     /* Mask extensions that are not supported by this hart */
757     val &= env->misa_ext_mask;
758 
759     /* Mask extensions that are not supported by QEMU */
760     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
761 
762     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
763     if ((val & RVD) && !(val & RVF)) {
764         val &= ~RVD;
765     }
766 
767     /* Suppress 'C' if next instruction is not aligned
768      * TODO: this should check next_pc
769      */
770     if ((val & RVC) && (GETPC() & ~3) != 0) {
771         val &= ~RVC;
772     }
773 
774     /* If nothing changed, do nothing. */
775     if (val == env->misa_ext) {
776         return RISCV_EXCP_NONE;
777     }
778 
779     /* flush translation cache */
780     tb_flush(env_cpu(env));
781     env->misa_ext = val;
782     env->xl = riscv_cpu_mxl(env);
783     return RISCV_EXCP_NONE;
784 }
785 
786 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
787                                    target_ulong *val)
788 {
789     *val = env->medeleg;
790     return RISCV_EXCP_NONE;
791 }
792 
793 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
794                                     target_ulong val)
795 {
796     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
797     return RISCV_EXCP_NONE;
798 }
799 
800 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno,
801                                     uint64_t *ret_val,
802                                     uint64_t new_val, uint64_t wr_mask)
803 {
804     uint64_t mask = wr_mask & delegable_ints;
805 
806     if (ret_val) {
807         *ret_val = env->mideleg;
808     }
809 
810     env->mideleg = (env->mideleg & ~mask) | (new_val & mask);
811 
812     if (riscv_has_ext(env, RVH)) {
813         env->mideleg |= HS_MODE_INTERRUPTS;
814     }
815 
816     return RISCV_EXCP_NONE;
817 }
818 
819 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno,
820                                   target_ulong *ret_val,
821                                   target_ulong new_val, target_ulong wr_mask)
822 {
823     uint64_t rval;
824     RISCVException ret;
825 
826     ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask);
827     if (ret_val) {
828         *ret_val = rval;
829     }
830 
831     return ret;
832 }
833 
834 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno,
835                                    target_ulong *ret_val,
836                                    target_ulong new_val,
837                                    target_ulong wr_mask)
838 {
839     uint64_t rval;
840     RISCVException ret;
841 
842     ret = rmw_mideleg64(env, csrno, &rval,
843         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
844     if (ret_val) {
845         *ret_val = rval >> 32;
846     }
847 
848     return ret;
849 }
850 
851 static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
852                                 uint64_t *ret_val,
853                                 uint64_t new_val, uint64_t wr_mask)
854 {
855     uint64_t mask = wr_mask & all_ints;
856 
857     if (ret_val) {
858         *ret_val = env->mie;
859     }
860 
861     env->mie = (env->mie & ~mask) | (new_val & mask);
862 
863     if (!riscv_has_ext(env, RVH)) {
864         env->mie &= ~((uint64_t)MIP_SGEIP);
865     }
866 
867     return RISCV_EXCP_NONE;
868 }
869 
870 static RISCVException rmw_mie(CPURISCVState *env, int csrno,
871                               target_ulong *ret_val,
872                               target_ulong new_val, target_ulong wr_mask)
873 {
874     uint64_t rval;
875     RISCVException ret;
876 
877     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask);
878     if (ret_val) {
879         *ret_val = rval;
880     }
881 
882     return ret;
883 }
884 
885 static RISCVException rmw_mieh(CPURISCVState *env, int csrno,
886                                target_ulong *ret_val,
887                                target_ulong new_val, target_ulong wr_mask)
888 {
889     uint64_t rval;
890     RISCVException ret;
891 
892     ret = rmw_mie64(env, csrno, &rval,
893         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
894     if (ret_val) {
895         *ret_val = rval >> 32;
896     }
897 
898     return ret;
899 }
900 
901 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
902                                  target_ulong *val)
903 {
904     *val = env->mtvec;
905     return RISCV_EXCP_NONE;
906 }
907 
908 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
909                                   target_ulong val)
910 {
911     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
912     if ((val & 3) < 2) {
913         env->mtvec = val;
914     } else {
915         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
916     }
917     return RISCV_EXCP_NONE;
918 }
919 
920 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
921                                       target_ulong *val)
922 {
923     *val = env->mcounteren;
924     return RISCV_EXCP_NONE;
925 }
926 
927 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
928                                        target_ulong val)
929 {
930     env->mcounteren = val;
931     return RISCV_EXCP_NONE;
932 }
933 
934 /* Machine Trap Handling */
935 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
936                                          Int128 *val)
937 {
938     *val = int128_make128(env->mscratch, env->mscratchh);
939     return RISCV_EXCP_NONE;
940 }
941 
942 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
943                                           Int128 val)
944 {
945     env->mscratch = int128_getlo(val);
946     env->mscratchh = int128_gethi(val);
947     return RISCV_EXCP_NONE;
948 }
949 
950 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
951                                     target_ulong *val)
952 {
953     *val = env->mscratch;
954     return RISCV_EXCP_NONE;
955 }
956 
957 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
958                                      target_ulong val)
959 {
960     env->mscratch = val;
961     return RISCV_EXCP_NONE;
962 }
963 
964 static RISCVException read_mepc(CPURISCVState *env, int csrno,
965                                      target_ulong *val)
966 {
967     *val = env->mepc;
968     return RISCV_EXCP_NONE;
969 }
970 
971 static RISCVException write_mepc(CPURISCVState *env, int csrno,
972                                      target_ulong val)
973 {
974     env->mepc = val;
975     return RISCV_EXCP_NONE;
976 }
977 
978 static RISCVException read_mcause(CPURISCVState *env, int csrno,
979                                      target_ulong *val)
980 {
981     *val = env->mcause;
982     return RISCV_EXCP_NONE;
983 }
984 
985 static RISCVException write_mcause(CPURISCVState *env, int csrno,
986                                      target_ulong val)
987 {
988     env->mcause = val;
989     return RISCV_EXCP_NONE;
990 }
991 
992 static RISCVException read_mtval(CPURISCVState *env, int csrno,
993                                  target_ulong *val)
994 {
995     *val = env->mtval;
996     return RISCV_EXCP_NONE;
997 }
998 
999 static RISCVException write_mtval(CPURISCVState *env, int csrno,
1000                                   target_ulong val)
1001 {
1002     env->mtval = val;
1003     return RISCV_EXCP_NONE;
1004 }
1005 
1006 static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
1007                                 uint64_t *ret_val,
1008                                 uint64_t new_val, uint64_t wr_mask)
1009 {
1010     RISCVCPU *cpu = env_archcpu(env);
1011     /* Allow software control of delegable interrupts not claimed by hardware */
1012     uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
1013     uint32_t gin;
1014 
1015     if (mask) {
1016         old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
1017     } else {
1018         old_mip = env->mip;
1019     }
1020 
1021     if (csrno != CSR_HVIP) {
1022         gin = get_field(env->hstatus, HSTATUS_VGEIN);
1023         old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
1024     }
1025 
1026     if (ret_val) {
1027         *ret_val = old_mip;
1028     }
1029 
1030     return RISCV_EXCP_NONE;
1031 }
1032 
1033 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
1034                               target_ulong *ret_val,
1035                               target_ulong new_val, target_ulong wr_mask)
1036 {
1037     uint64_t rval;
1038     RISCVException ret;
1039 
1040     ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask);
1041     if (ret_val) {
1042         *ret_val = rval;
1043     }
1044 
1045     return ret;
1046 }
1047 
1048 static RISCVException rmw_miph(CPURISCVState *env, int csrno,
1049                                target_ulong *ret_val,
1050                                target_ulong new_val, target_ulong wr_mask)
1051 {
1052     uint64_t rval;
1053     RISCVException ret;
1054 
1055     ret = rmw_mip64(env, csrno, &rval,
1056         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1057     if (ret_val) {
1058         *ret_val = rval >> 32;
1059     }
1060 
1061     return ret;
1062 }
1063 
1064 /* Supervisor Trap Setup */
1065 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
1066                                         Int128 *val)
1067 {
1068     uint64_t mask = sstatus_v1_10_mask;
1069     uint64_t sstatus = env->mstatus & mask;
1070     if (env->xl != MXL_RV32 || env->debugger) {
1071         mask |= SSTATUS64_UXL;
1072     }
1073 
1074     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
1075     return RISCV_EXCP_NONE;
1076 }
1077 
1078 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
1079                                    target_ulong *val)
1080 {
1081     target_ulong mask = (sstatus_v1_10_mask);
1082     if (env->xl != MXL_RV32 || env->debugger) {
1083         mask |= SSTATUS64_UXL;
1084     }
1085     /* TODO: Use SXL not MXL. */
1086     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
1087     return RISCV_EXCP_NONE;
1088 }
1089 
1090 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
1091                                     target_ulong val)
1092 {
1093     target_ulong mask = (sstatus_v1_10_mask);
1094 
1095     if (env->xl != MXL_RV32 || env->debugger) {
1096         if ((val & SSTATUS64_UXL) != 0) {
1097             mask |= SSTATUS64_UXL;
1098         }
1099     }
1100     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
1101     return write_mstatus(env, CSR_MSTATUS, newval);
1102 }
1103 
1104 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
1105                                  uint64_t *ret_val,
1106                                  uint64_t new_val, uint64_t wr_mask)
1107 {
1108     RISCVException ret;
1109     uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
1110 
1111     /* Bring VS-level bits to correct position */
1112     vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
1113     new_val &= ~(VS_MODE_INTERRUPTS >> 1);
1114     new_val |= vsbits << 1;
1115     vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
1116     wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
1117     wr_mask |= vsbits << 1;
1118 
1119     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
1120     if (ret_val) {
1121         rval &= mask;
1122         vsbits = rval & VS_MODE_INTERRUPTS;
1123         rval &= ~VS_MODE_INTERRUPTS;
1124         *ret_val = rval | (vsbits >> 1);
1125     }
1126 
1127     return ret;
1128 }
1129 
1130 static RISCVException rmw_vsie(CPURISCVState *env, int csrno,
1131                                target_ulong *ret_val,
1132                                target_ulong new_val, target_ulong wr_mask)
1133 {
1134     uint64_t rval;
1135     RISCVException ret;
1136 
1137     ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask);
1138     if (ret_val) {
1139         *ret_val = rval;
1140     }
1141 
1142     return ret;
1143 }
1144 
1145 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno,
1146                                 target_ulong *ret_val,
1147                                 target_ulong new_val, target_ulong wr_mask)
1148 {
1149     uint64_t rval;
1150     RISCVException ret;
1151 
1152     ret = rmw_vsie64(env, csrno, &rval,
1153         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1154     if (ret_val) {
1155         *ret_val = rval >> 32;
1156     }
1157 
1158     return ret;
1159 }
1160 
1161 static RISCVException rmw_sie64(CPURISCVState *env, int csrno,
1162                                 uint64_t *ret_val,
1163                                 uint64_t new_val, uint64_t wr_mask)
1164 {
1165     RISCVException ret;
1166     uint64_t mask = env->mideleg & S_MODE_INTERRUPTS;
1167 
1168     if (riscv_cpu_virt_enabled(env)) {
1169         if (env->hvictl & HVICTL_VTI) {
1170             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1171         }
1172         ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask);
1173     } else {
1174         ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask);
1175     }
1176 
1177     if (ret_val) {
1178         *ret_val &= mask;
1179     }
1180 
1181     return ret;
1182 }
1183 
1184 static RISCVException rmw_sie(CPURISCVState *env, int csrno,
1185                               target_ulong *ret_val,
1186                               target_ulong new_val, target_ulong wr_mask)
1187 {
1188     uint64_t rval;
1189     RISCVException ret;
1190 
1191     ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask);
1192     if (ret == RISCV_EXCP_NONE && ret_val) {
1193         *ret_val = rval;
1194     }
1195 
1196     return ret;
1197 }
1198 
1199 static RISCVException rmw_sieh(CPURISCVState *env, int csrno,
1200                                target_ulong *ret_val,
1201                                target_ulong new_val, target_ulong wr_mask)
1202 {
1203     uint64_t rval;
1204     RISCVException ret;
1205 
1206     ret = rmw_sie64(env, csrno, &rval,
1207         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1208     if (ret_val) {
1209         *ret_val = rval >> 32;
1210     }
1211 
1212     return ret;
1213 }
1214 
1215 static RISCVException read_stvec(CPURISCVState *env, int csrno,
1216                                  target_ulong *val)
1217 {
1218     *val = env->stvec;
1219     return RISCV_EXCP_NONE;
1220 }
1221 
1222 static RISCVException write_stvec(CPURISCVState *env, int csrno,
1223                                   target_ulong val)
1224 {
1225     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1226     if ((val & 3) < 2) {
1227         env->stvec = val;
1228     } else {
1229         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
1230     }
1231     return RISCV_EXCP_NONE;
1232 }
1233 
1234 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
1235                                       target_ulong *val)
1236 {
1237     *val = env->scounteren;
1238     return RISCV_EXCP_NONE;
1239 }
1240 
1241 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
1242                                        target_ulong val)
1243 {
1244     env->scounteren = val;
1245     return RISCV_EXCP_NONE;
1246 }
1247 
1248 /* Supervisor Trap Handling */
1249 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
1250                                          Int128 *val)
1251 {
1252     *val = int128_make128(env->sscratch, env->sscratchh);
1253     return RISCV_EXCP_NONE;
1254 }
1255 
1256 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
1257                                           Int128 val)
1258 {
1259     env->sscratch = int128_getlo(val);
1260     env->sscratchh = int128_gethi(val);
1261     return RISCV_EXCP_NONE;
1262 }
1263 
1264 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
1265                                     target_ulong *val)
1266 {
1267     *val = env->sscratch;
1268     return RISCV_EXCP_NONE;
1269 }
1270 
1271 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1272                                      target_ulong val)
1273 {
1274     env->sscratch = val;
1275     return RISCV_EXCP_NONE;
1276 }
1277 
1278 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1279                                 target_ulong *val)
1280 {
1281     *val = env->sepc;
1282     return RISCV_EXCP_NONE;
1283 }
1284 
1285 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1286                                  target_ulong val)
1287 {
1288     env->sepc = val;
1289     return RISCV_EXCP_NONE;
1290 }
1291 
1292 static RISCVException read_scause(CPURISCVState *env, int csrno,
1293                                   target_ulong *val)
1294 {
1295     *val = env->scause;
1296     return RISCV_EXCP_NONE;
1297 }
1298 
1299 static RISCVException write_scause(CPURISCVState *env, int csrno,
1300                                    target_ulong val)
1301 {
1302     env->scause = val;
1303     return RISCV_EXCP_NONE;
1304 }
1305 
1306 static RISCVException read_stval(CPURISCVState *env, int csrno,
1307                                  target_ulong *val)
1308 {
1309     *val = env->stval;
1310     return RISCV_EXCP_NONE;
1311 }
1312 
1313 static RISCVException write_stval(CPURISCVState *env, int csrno,
1314                                   target_ulong val)
1315 {
1316     env->stval = val;
1317     return RISCV_EXCP_NONE;
1318 }
1319 
1320 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
1321                                  uint64_t *ret_val,
1322                                  uint64_t new_val, uint64_t wr_mask)
1323 {
1324     RISCVException ret;
1325     uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
1326 
1327     /* Bring VS-level bits to correct position */
1328     vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
1329     new_val &= ~(VS_MODE_INTERRUPTS >> 1);
1330     new_val |= vsbits << 1;
1331     vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
1332     wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
1333     wr_mask |= vsbits << 1;
1334 
1335     ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
1336     if (ret_val) {
1337         rval &= mask;
1338         vsbits = rval & VS_MODE_INTERRUPTS;
1339         rval &= ~VS_MODE_INTERRUPTS;
1340         *ret_val = rval | (vsbits >> 1);
1341     }
1342 
1343     return ret;
1344 }
1345 
1346 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1347                                target_ulong *ret_val,
1348                                target_ulong new_val, target_ulong wr_mask)
1349 {
1350     uint64_t rval;
1351     RISCVException ret;
1352 
1353     ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask);
1354     if (ret_val) {
1355         *ret_val = rval;
1356     }
1357 
1358     return ret;
1359 }
1360 
1361 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno,
1362                                 target_ulong *ret_val,
1363                                 target_ulong new_val, target_ulong wr_mask)
1364 {
1365     uint64_t rval;
1366     RISCVException ret;
1367 
1368     ret = rmw_vsip64(env, csrno, &rval,
1369         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1370     if (ret_val) {
1371         *ret_val = rval >> 32;
1372     }
1373 
1374     return ret;
1375 }
1376 
1377 static RISCVException rmw_sip64(CPURISCVState *env, int csrno,
1378                                 uint64_t *ret_val,
1379                                 uint64_t new_val, uint64_t wr_mask)
1380 {
1381     RISCVException ret;
1382     uint64_t mask = env->mideleg & sip_writable_mask;
1383 
1384     if (riscv_cpu_virt_enabled(env)) {
1385         if (env->hvictl & HVICTL_VTI) {
1386             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
1387         }
1388         ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask);
1389     } else {
1390         ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask);
1391     }
1392 
1393     if (ret_val) {
1394         *ret_val &= env->mideleg & S_MODE_INTERRUPTS;
1395     }
1396 
1397     return ret;
1398 }
1399 
1400 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1401                               target_ulong *ret_val,
1402                               target_ulong new_val, target_ulong wr_mask)
1403 {
1404     uint64_t rval;
1405     RISCVException ret;
1406 
1407     ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask);
1408     if (ret_val) {
1409         *ret_val = rval;
1410     }
1411 
1412     return ret;
1413 }
1414 
1415 static RISCVException rmw_siph(CPURISCVState *env, int csrno,
1416                                target_ulong *ret_val,
1417                                target_ulong new_val, target_ulong wr_mask)
1418 {
1419     uint64_t rval;
1420     RISCVException ret;
1421 
1422     ret = rmw_sip64(env, csrno, &rval,
1423         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1424     if (ret_val) {
1425         *ret_val = rval >> 32;
1426     }
1427 
1428     return ret;
1429 }
1430 
1431 /* Supervisor Protection and Translation */
1432 static RISCVException read_satp(CPURISCVState *env, int csrno,
1433                                 target_ulong *val)
1434 {
1435     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1436         *val = 0;
1437         return RISCV_EXCP_NONE;
1438     }
1439 
1440     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1441         return RISCV_EXCP_ILLEGAL_INST;
1442     } else {
1443         *val = env->satp;
1444     }
1445 
1446     return RISCV_EXCP_NONE;
1447 }
1448 
1449 static RISCVException write_satp(CPURISCVState *env, int csrno,
1450                                  target_ulong val)
1451 {
1452     target_ulong vm, mask, asid;
1453 
1454     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1455         return RISCV_EXCP_NONE;
1456     }
1457 
1458     if (riscv_cpu_mxl(env) == MXL_RV32) {
1459         vm = validate_vm(env, get_field(val, SATP32_MODE));
1460         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1461         asid = (val ^ env->satp) & SATP32_ASID;
1462     } else {
1463         vm = validate_vm(env, get_field(val, SATP64_MODE));
1464         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1465         asid = (val ^ env->satp) & SATP64_ASID;
1466     }
1467 
1468     if (vm && mask) {
1469         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1470             return RISCV_EXCP_ILLEGAL_INST;
1471         } else {
1472             if (asid) {
1473                 tlb_flush(env_cpu(env));
1474             }
1475             env->satp = val;
1476         }
1477     }
1478     return RISCV_EXCP_NONE;
1479 }
1480 
1481 /* Hypervisor Extensions */
1482 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1483                                    target_ulong *val)
1484 {
1485     *val = env->hstatus;
1486     if (riscv_cpu_mxl(env) != MXL_RV32) {
1487         /* We only support 64-bit VSXL */
1488         *val = set_field(*val, HSTATUS_VSXL, 2);
1489     }
1490     /* We only support little endian */
1491     *val = set_field(*val, HSTATUS_VSBE, 0);
1492     return RISCV_EXCP_NONE;
1493 }
1494 
1495 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1496                                     target_ulong val)
1497 {
1498     env->hstatus = val;
1499     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1500         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1501     }
1502     if (get_field(val, HSTATUS_VSBE) != 0) {
1503         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1504     }
1505     return RISCV_EXCP_NONE;
1506 }
1507 
1508 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1509                                    target_ulong *val)
1510 {
1511     *val = env->hedeleg;
1512     return RISCV_EXCP_NONE;
1513 }
1514 
1515 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1516                                     target_ulong val)
1517 {
1518     env->hedeleg = val & vs_delegable_excps;
1519     return RISCV_EXCP_NONE;
1520 }
1521 
1522 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno,
1523                                     uint64_t *ret_val,
1524                                     uint64_t new_val, uint64_t wr_mask)
1525 {
1526     uint64_t mask = wr_mask & vs_delegable_ints;
1527 
1528     if (ret_val) {
1529         *ret_val = env->hideleg & vs_delegable_ints;
1530     }
1531 
1532     env->hideleg = (env->hideleg & ~mask) | (new_val & mask);
1533     return RISCV_EXCP_NONE;
1534 }
1535 
1536 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno,
1537                                   target_ulong *ret_val,
1538                                   target_ulong new_val, target_ulong wr_mask)
1539 {
1540     uint64_t rval;
1541     RISCVException ret;
1542 
1543     ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask);
1544     if (ret_val) {
1545         *ret_val = rval;
1546     }
1547 
1548     return ret;
1549 }
1550 
1551 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno,
1552                                    target_ulong *ret_val,
1553                                    target_ulong new_val, target_ulong wr_mask)
1554 {
1555     uint64_t rval;
1556     RISCVException ret;
1557 
1558     ret = rmw_hideleg64(env, csrno, &rval,
1559         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1560     if (ret_val) {
1561         *ret_val = rval >> 32;
1562     }
1563 
1564     return ret;
1565 }
1566 
1567 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno,
1568                                  uint64_t *ret_val,
1569                                  uint64_t new_val, uint64_t wr_mask)
1570 {
1571     RISCVException ret;
1572 
1573     ret = rmw_mip64(env, csrno, ret_val, new_val,
1574                     wr_mask & hvip_writable_mask);
1575     if (ret_val) {
1576         *ret_val &= VS_MODE_INTERRUPTS;
1577     }
1578 
1579     return ret;
1580 }
1581 
1582 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1583                                target_ulong *ret_val,
1584                                target_ulong new_val, target_ulong wr_mask)
1585 {
1586     uint64_t rval;
1587     RISCVException ret;
1588 
1589     ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask);
1590     if (ret_val) {
1591         *ret_val = rval;
1592     }
1593 
1594     return ret;
1595 }
1596 
1597 static RISCVException rmw_hviph(CPURISCVState *env, int csrno,
1598                                 target_ulong *ret_val,
1599                                 target_ulong new_val, target_ulong wr_mask)
1600 {
1601     uint64_t rval;
1602     RISCVException ret;
1603 
1604     ret = rmw_hvip64(env, csrno, &rval,
1605         ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32);
1606     if (ret_val) {
1607         *ret_val = rval >> 32;
1608     }
1609 
1610     return ret;
1611 }
1612 
1613 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1614                               target_ulong *ret_value,
1615                               target_ulong new_value, target_ulong write_mask)
1616 {
1617     int ret = rmw_mip(env, csrno, ret_value, new_value,
1618                       write_mask & hip_writable_mask);
1619 
1620     if (ret_value) {
1621         *ret_value &= HS_MODE_INTERRUPTS;
1622     }
1623     return ret;
1624 }
1625 
1626 static RISCVException rmw_hie(CPURISCVState *env, int csrno,
1627                               target_ulong *ret_val,
1628                               target_ulong new_val, target_ulong wr_mask)
1629 {
1630     uint64_t rval;
1631     RISCVException ret;
1632 
1633     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS);
1634     if (ret_val) {
1635         *ret_val = rval & HS_MODE_INTERRUPTS;
1636     }
1637 
1638     return ret;
1639 }
1640 
1641 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1642                                       target_ulong *val)
1643 {
1644     *val = env->hcounteren;
1645     return RISCV_EXCP_NONE;
1646 }
1647 
1648 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1649                                        target_ulong val)
1650 {
1651     env->hcounteren = val;
1652     return RISCV_EXCP_NONE;
1653 }
1654 
1655 static RISCVException read_hgeie(CPURISCVState *env, int csrno,
1656                                  target_ulong *val)
1657 {
1658     if (val) {
1659         *val = env->hgeie;
1660     }
1661     return RISCV_EXCP_NONE;
1662 }
1663 
1664 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1665                                   target_ulong val)
1666 {
1667     /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
1668     val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
1669     env->hgeie = val;
1670     /* Update mip.SGEIP bit */
1671     riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
1672                          BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1673     return RISCV_EXCP_NONE;
1674 }
1675 
1676 static RISCVException read_htval(CPURISCVState *env, int csrno,
1677                                  target_ulong *val)
1678 {
1679     *val = env->htval;
1680     return RISCV_EXCP_NONE;
1681 }
1682 
1683 static RISCVException write_htval(CPURISCVState *env, int csrno,
1684                                   target_ulong val)
1685 {
1686     env->htval = val;
1687     return RISCV_EXCP_NONE;
1688 }
1689 
1690 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1691                                   target_ulong *val)
1692 {
1693     *val = env->htinst;
1694     return RISCV_EXCP_NONE;
1695 }
1696 
1697 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1698                                    target_ulong val)
1699 {
1700     return RISCV_EXCP_NONE;
1701 }
1702 
1703 static RISCVException read_hgeip(CPURISCVState *env, int csrno,
1704                                  target_ulong *val)
1705 {
1706     if (val) {
1707         *val = env->hgeip;
1708     }
1709     return RISCV_EXCP_NONE;
1710 }
1711 
1712 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1713                                  target_ulong *val)
1714 {
1715     *val = env->hgatp;
1716     return RISCV_EXCP_NONE;
1717 }
1718 
1719 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1720                                   target_ulong val)
1721 {
1722     env->hgatp = val;
1723     return RISCV_EXCP_NONE;
1724 }
1725 
1726 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1727                                       target_ulong *val)
1728 {
1729     if (!env->rdtime_fn) {
1730         return RISCV_EXCP_ILLEGAL_INST;
1731     }
1732 
1733     *val = env->htimedelta;
1734     return RISCV_EXCP_NONE;
1735 }
1736 
1737 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1738                                        target_ulong val)
1739 {
1740     if (!env->rdtime_fn) {
1741         return RISCV_EXCP_ILLEGAL_INST;
1742     }
1743 
1744     if (riscv_cpu_mxl(env) == MXL_RV32) {
1745         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1746     } else {
1747         env->htimedelta = val;
1748     }
1749     return RISCV_EXCP_NONE;
1750 }
1751 
1752 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1753                                        target_ulong *val)
1754 {
1755     if (!env->rdtime_fn) {
1756         return RISCV_EXCP_ILLEGAL_INST;
1757     }
1758 
1759     *val = env->htimedelta >> 32;
1760     return RISCV_EXCP_NONE;
1761 }
1762 
1763 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1764                                         target_ulong val)
1765 {
1766     if (!env->rdtime_fn) {
1767         return RISCV_EXCP_ILLEGAL_INST;
1768     }
1769 
1770     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1771     return RISCV_EXCP_NONE;
1772 }
1773 
1774 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
1775 {
1776     *val = env->hvictl;
1777     return RISCV_EXCP_NONE;
1778 }
1779 
1780 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
1781 {
1782     env->hvictl = val & HVICTL_VALID_MASK;
1783     return RISCV_EXCP_NONE;
1784 }
1785 
1786 static int read_hvipriox(CPURISCVState *env, int first_index,
1787                          uint8_t *iprio, target_ulong *val)
1788 {
1789     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
1790 
1791     /* First index has to be a multiple of number of irqs per register */
1792     if (first_index % num_irqs) {
1793         return (riscv_cpu_virt_enabled(env)) ?
1794                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1795     }
1796 
1797     /* Fill-up return value */
1798     *val = 0;
1799     for (i = 0; i < num_irqs; i++) {
1800         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
1801             continue;
1802         }
1803         if (rdzero) {
1804             continue;
1805         }
1806         *val |= ((target_ulong)iprio[irq]) << (i * 8);
1807     }
1808 
1809     return RISCV_EXCP_NONE;
1810 }
1811 
1812 static int write_hvipriox(CPURISCVState *env, int first_index,
1813                           uint8_t *iprio, target_ulong val)
1814 {
1815     int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32);
1816 
1817     /* First index has to be a multiple of number of irqs per register */
1818     if (first_index % num_irqs) {
1819         return (riscv_cpu_virt_enabled(env)) ?
1820                RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
1821     }
1822 
1823     /* Fill-up priority arrary */
1824     for (i = 0; i < num_irqs; i++) {
1825         if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
1826             continue;
1827         }
1828         if (rdzero) {
1829             iprio[irq] = 0;
1830         } else {
1831             iprio[irq] = (val >> (i * 8)) & 0xff;
1832         }
1833     }
1834 
1835     return RISCV_EXCP_NONE;
1836 }
1837 
1838 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val)
1839 {
1840     return read_hvipriox(env, 0, env->hviprio, val);
1841 }
1842 
1843 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val)
1844 {
1845     return write_hvipriox(env, 0, env->hviprio, val);
1846 }
1847 
1848 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val)
1849 {
1850     return read_hvipriox(env, 4, env->hviprio, val);
1851 }
1852 
1853 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val)
1854 {
1855     return write_hvipriox(env, 4, env->hviprio, val);
1856 }
1857 
1858 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val)
1859 {
1860     return read_hvipriox(env, 8, env->hviprio, val);
1861 }
1862 
1863 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val)
1864 {
1865     return write_hvipriox(env, 8, env->hviprio, val);
1866 }
1867 
1868 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val)
1869 {
1870     return read_hvipriox(env, 12, env->hviprio, val);
1871 }
1872 
1873 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val)
1874 {
1875     return write_hvipriox(env, 12, env->hviprio, val);
1876 }
1877 
1878 /* Virtual CSR Registers */
1879 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1880                                     target_ulong *val)
1881 {
1882     *val = env->vsstatus;
1883     return RISCV_EXCP_NONE;
1884 }
1885 
1886 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1887                                      target_ulong val)
1888 {
1889     uint64_t mask = (target_ulong)-1;
1890     if ((val & VSSTATUS64_UXL) == 0) {
1891         mask &= ~VSSTATUS64_UXL;
1892     }
1893     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1894     return RISCV_EXCP_NONE;
1895 }
1896 
1897 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1898 {
1899     *val = env->vstvec;
1900     return RISCV_EXCP_NONE;
1901 }
1902 
1903 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1904                                    target_ulong val)
1905 {
1906     env->vstvec = val;
1907     return RISCV_EXCP_NONE;
1908 }
1909 
1910 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1911                                      target_ulong *val)
1912 {
1913     *val = env->vsscratch;
1914     return RISCV_EXCP_NONE;
1915 }
1916 
1917 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1918                                       target_ulong val)
1919 {
1920     env->vsscratch = val;
1921     return RISCV_EXCP_NONE;
1922 }
1923 
1924 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1925                                  target_ulong *val)
1926 {
1927     *val = env->vsepc;
1928     return RISCV_EXCP_NONE;
1929 }
1930 
1931 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1932                                   target_ulong val)
1933 {
1934     env->vsepc = val;
1935     return RISCV_EXCP_NONE;
1936 }
1937 
1938 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1939                                    target_ulong *val)
1940 {
1941     *val = env->vscause;
1942     return RISCV_EXCP_NONE;
1943 }
1944 
1945 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1946                                     target_ulong val)
1947 {
1948     env->vscause = val;
1949     return RISCV_EXCP_NONE;
1950 }
1951 
1952 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1953                                   target_ulong *val)
1954 {
1955     *val = env->vstval;
1956     return RISCV_EXCP_NONE;
1957 }
1958 
1959 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1960                                    target_ulong val)
1961 {
1962     env->vstval = val;
1963     return RISCV_EXCP_NONE;
1964 }
1965 
1966 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1967                                  target_ulong *val)
1968 {
1969     *val = env->vsatp;
1970     return RISCV_EXCP_NONE;
1971 }
1972 
1973 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1974                                   target_ulong val)
1975 {
1976     env->vsatp = val;
1977     return RISCV_EXCP_NONE;
1978 }
1979 
1980 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1981                                   target_ulong *val)
1982 {
1983     *val = env->mtval2;
1984     return RISCV_EXCP_NONE;
1985 }
1986 
1987 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1988                                    target_ulong val)
1989 {
1990     env->mtval2 = val;
1991     return RISCV_EXCP_NONE;
1992 }
1993 
1994 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1995                                   target_ulong *val)
1996 {
1997     *val = env->mtinst;
1998     return RISCV_EXCP_NONE;
1999 }
2000 
2001 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
2002                                    target_ulong val)
2003 {
2004     env->mtinst = val;
2005     return RISCV_EXCP_NONE;
2006 }
2007 
2008 /* Physical Memory Protection */
2009 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
2010                                    target_ulong *val)
2011 {
2012     *val = mseccfg_csr_read(env);
2013     return RISCV_EXCP_NONE;
2014 }
2015 
2016 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
2017                          target_ulong val)
2018 {
2019     mseccfg_csr_write(env, val);
2020     return RISCV_EXCP_NONE;
2021 }
2022 
2023 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
2024 {
2025     /* TODO: RV128 restriction check */
2026     if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
2027         return false;
2028     }
2029     return true;
2030 }
2031 
2032 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
2033                                   target_ulong *val)
2034 {
2035     uint32_t reg_index = csrno - CSR_PMPCFG0;
2036 
2037     if (!check_pmp_reg_index(env, reg_index)) {
2038         return RISCV_EXCP_ILLEGAL_INST;
2039     }
2040     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
2041     return RISCV_EXCP_NONE;
2042 }
2043 
2044 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
2045                                    target_ulong val)
2046 {
2047     uint32_t reg_index = csrno - CSR_PMPCFG0;
2048 
2049     if (!check_pmp_reg_index(env, reg_index)) {
2050         return RISCV_EXCP_ILLEGAL_INST;
2051     }
2052     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
2053     return RISCV_EXCP_NONE;
2054 }
2055 
2056 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
2057                                    target_ulong *val)
2058 {
2059     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
2060     return RISCV_EXCP_NONE;
2061 }
2062 
2063 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
2064                                     target_ulong val)
2065 {
2066     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
2067     return RISCV_EXCP_NONE;
2068 }
2069 
2070 /*
2071  * Functions to access Pointer Masking feature registers
2072  * We have to check if current priv lvl could modify
2073  * csr in given mode
2074  */
2075 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
2076 {
2077     int csr_priv = get_field(csrno, 0x300);
2078     int pm_current;
2079 
2080     if (env->debugger) {
2081         return false;
2082     }
2083     /*
2084      * If priv lvls differ that means we're accessing csr from higher priv lvl,
2085      * so allow the access
2086      */
2087     if (env->priv != csr_priv) {
2088         return false;
2089     }
2090     switch (env->priv) {
2091     case PRV_M:
2092         pm_current = get_field(env->mmte, M_PM_CURRENT);
2093         break;
2094     case PRV_S:
2095         pm_current = get_field(env->mmte, S_PM_CURRENT);
2096         break;
2097     case PRV_U:
2098         pm_current = get_field(env->mmte, U_PM_CURRENT);
2099         break;
2100     default:
2101         g_assert_not_reached();
2102     }
2103     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
2104     return !pm_current;
2105 }
2106 
2107 static RISCVException read_mmte(CPURISCVState *env, int csrno,
2108                                 target_ulong *val)
2109 {
2110     *val = env->mmte & MMTE_MASK;
2111     return RISCV_EXCP_NONE;
2112 }
2113 
2114 static RISCVException write_mmte(CPURISCVState *env, int csrno,
2115                                  target_ulong val)
2116 {
2117     uint64_t mstatus;
2118     target_ulong wpri_val = val & MMTE_MASK;
2119 
2120     if (val != wpri_val) {
2121         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
2122                       "MMTE: WPRI violation written 0x", val,
2123                       "vs expected 0x", wpri_val);
2124     }
2125     /* for machine mode pm.current is hardwired to 1 */
2126     wpri_val |= MMTE_M_PM_CURRENT;
2127 
2128     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
2129     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
2130     env->mmte = wpri_val | PM_EXT_DIRTY;
2131     riscv_cpu_update_mask(env);
2132 
2133     /* Set XS and SD bits, since PM CSRs are dirty */
2134     mstatus = env->mstatus | MSTATUS_XS;
2135     write_mstatus(env, csrno, mstatus);
2136     return RISCV_EXCP_NONE;
2137 }
2138 
2139 static RISCVException read_smte(CPURISCVState *env, int csrno,
2140                                 target_ulong *val)
2141 {
2142     *val = env->mmte & SMTE_MASK;
2143     return RISCV_EXCP_NONE;
2144 }
2145 
2146 static RISCVException write_smte(CPURISCVState *env, int csrno,
2147                                  target_ulong val)
2148 {
2149     target_ulong wpri_val = val & SMTE_MASK;
2150 
2151     if (val != wpri_val) {
2152         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
2153                       "SMTE: WPRI violation written 0x", val,
2154                       "vs expected 0x", wpri_val);
2155     }
2156 
2157     /* if pm.current==0 we can't modify current PM CSRs */
2158     if (check_pm_current_disabled(env, csrno)) {
2159         return RISCV_EXCP_NONE;
2160     }
2161 
2162     wpri_val |= (env->mmte & ~SMTE_MASK);
2163     write_mmte(env, csrno, wpri_val);
2164     return RISCV_EXCP_NONE;
2165 }
2166 
2167 static RISCVException read_umte(CPURISCVState *env, int csrno,
2168                                 target_ulong *val)
2169 {
2170     *val = env->mmte & UMTE_MASK;
2171     return RISCV_EXCP_NONE;
2172 }
2173 
2174 static RISCVException write_umte(CPURISCVState *env, int csrno,
2175                                  target_ulong val)
2176 {
2177     target_ulong wpri_val = val & UMTE_MASK;
2178 
2179     if (val != wpri_val) {
2180         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
2181                       "UMTE: WPRI violation written 0x", val,
2182                       "vs expected 0x", wpri_val);
2183     }
2184 
2185     if (check_pm_current_disabled(env, csrno)) {
2186         return RISCV_EXCP_NONE;
2187     }
2188 
2189     wpri_val |= (env->mmte & ~UMTE_MASK);
2190     write_mmte(env, csrno, wpri_val);
2191     return RISCV_EXCP_NONE;
2192 }
2193 
2194 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
2195                                    target_ulong *val)
2196 {
2197     *val = env->mpmmask;
2198     return RISCV_EXCP_NONE;
2199 }
2200 
2201 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
2202                                     target_ulong val)
2203 {
2204     uint64_t mstatus;
2205 
2206     env->mpmmask = val;
2207     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
2208         env->cur_pmmask = val;
2209     }
2210     env->mmte |= PM_EXT_DIRTY;
2211 
2212     /* Set XS and SD bits, since PM CSRs are dirty */
2213     mstatus = env->mstatus | MSTATUS_XS;
2214     write_mstatus(env, csrno, mstatus);
2215     return RISCV_EXCP_NONE;
2216 }
2217 
2218 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
2219                                    target_ulong *val)
2220 {
2221     *val = env->spmmask;
2222     return RISCV_EXCP_NONE;
2223 }
2224 
2225 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
2226                                     target_ulong val)
2227 {
2228     uint64_t mstatus;
2229 
2230     /* if pm.current==0 we can't modify current PM CSRs */
2231     if (check_pm_current_disabled(env, csrno)) {
2232         return RISCV_EXCP_NONE;
2233     }
2234     env->spmmask = val;
2235     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
2236         env->cur_pmmask = val;
2237     }
2238     env->mmte |= PM_EXT_DIRTY;
2239 
2240     /* Set XS and SD bits, since PM CSRs are dirty */
2241     mstatus = env->mstatus | MSTATUS_XS;
2242     write_mstatus(env, csrno, mstatus);
2243     return RISCV_EXCP_NONE;
2244 }
2245 
2246 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
2247                                    target_ulong *val)
2248 {
2249     *val = env->upmmask;
2250     return RISCV_EXCP_NONE;
2251 }
2252 
2253 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
2254                                     target_ulong val)
2255 {
2256     uint64_t mstatus;
2257 
2258     /* if pm.current==0 we can't modify current PM CSRs */
2259     if (check_pm_current_disabled(env, csrno)) {
2260         return RISCV_EXCP_NONE;
2261     }
2262     env->upmmask = val;
2263     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
2264         env->cur_pmmask = val;
2265     }
2266     env->mmte |= PM_EXT_DIRTY;
2267 
2268     /* Set XS and SD bits, since PM CSRs are dirty */
2269     mstatus = env->mstatus | MSTATUS_XS;
2270     write_mstatus(env, csrno, mstatus);
2271     return RISCV_EXCP_NONE;
2272 }
2273 
2274 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
2275                                    target_ulong *val)
2276 {
2277     *val = env->mpmbase;
2278     return RISCV_EXCP_NONE;
2279 }
2280 
2281 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
2282                                     target_ulong val)
2283 {
2284     uint64_t mstatus;
2285 
2286     env->mpmbase = val;
2287     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
2288         env->cur_pmbase = val;
2289     }
2290     env->mmte |= PM_EXT_DIRTY;
2291 
2292     /* Set XS and SD bits, since PM CSRs are dirty */
2293     mstatus = env->mstatus | MSTATUS_XS;
2294     write_mstatus(env, csrno, mstatus);
2295     return RISCV_EXCP_NONE;
2296 }
2297 
2298 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
2299                                    target_ulong *val)
2300 {
2301     *val = env->spmbase;
2302     return RISCV_EXCP_NONE;
2303 }
2304 
2305 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
2306                                     target_ulong val)
2307 {
2308     uint64_t mstatus;
2309 
2310     /* if pm.current==0 we can't modify current PM CSRs */
2311     if (check_pm_current_disabled(env, csrno)) {
2312         return RISCV_EXCP_NONE;
2313     }
2314     env->spmbase = val;
2315     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
2316         env->cur_pmbase = val;
2317     }
2318     env->mmte |= PM_EXT_DIRTY;
2319 
2320     /* Set XS and SD bits, since PM CSRs are dirty */
2321     mstatus = env->mstatus | MSTATUS_XS;
2322     write_mstatus(env, csrno, mstatus);
2323     return RISCV_EXCP_NONE;
2324 }
2325 
2326 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
2327                                    target_ulong *val)
2328 {
2329     *val = env->upmbase;
2330     return RISCV_EXCP_NONE;
2331 }
2332 
2333 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
2334                                     target_ulong val)
2335 {
2336     uint64_t mstatus;
2337 
2338     /* if pm.current==0 we can't modify current PM CSRs */
2339     if (check_pm_current_disabled(env, csrno)) {
2340         return RISCV_EXCP_NONE;
2341     }
2342     env->upmbase = val;
2343     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
2344         env->cur_pmbase = val;
2345     }
2346     env->mmte |= PM_EXT_DIRTY;
2347 
2348     /* Set XS and SD bits, since PM CSRs are dirty */
2349     mstatus = env->mstatus | MSTATUS_XS;
2350     write_mstatus(env, csrno, mstatus);
2351     return RISCV_EXCP_NONE;
2352 }
2353 
2354 #endif
2355 
2356 /*
2357  * riscv_csrrw - read and/or update control and status register
2358  *
2359  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
2360  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
2361  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
2362  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
2363  */
2364 
2365 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
2366                                                int csrno,
2367                                                bool write_mask,
2368                                                RISCVCPU *cpu)
2369 {
2370     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
2371     int read_only = get_field(csrno, 0xC00) == 3;
2372 #if !defined(CONFIG_USER_ONLY)
2373     int effective_priv = env->priv;
2374 
2375     if (riscv_has_ext(env, RVH) &&
2376         env->priv == PRV_S &&
2377         !riscv_cpu_virt_enabled(env)) {
2378         /*
2379          * We are in S mode without virtualisation, therefore we are in HS Mode.
2380          * Add 1 to the effective privledge level to allow us to access the
2381          * Hypervisor CSRs.
2382          */
2383         effective_priv++;
2384     }
2385 
2386     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
2387         return RISCV_EXCP_ILLEGAL_INST;
2388     }
2389 #endif
2390     if (write_mask && read_only) {
2391         return RISCV_EXCP_ILLEGAL_INST;
2392     }
2393 
2394     /* ensure the CSR extension is enabled. */
2395     if (!cpu->cfg.ext_icsr) {
2396         return RISCV_EXCP_ILLEGAL_INST;
2397     }
2398 
2399     /* check predicate */
2400     if (!csr_ops[csrno].predicate) {
2401         return RISCV_EXCP_ILLEGAL_INST;
2402     }
2403 
2404     return csr_ops[csrno].predicate(env, csrno);
2405 }
2406 
2407 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
2408                                        target_ulong *ret_value,
2409                                        target_ulong new_value,
2410                                        target_ulong write_mask)
2411 {
2412     RISCVException ret;
2413     target_ulong old_value;
2414 
2415     /* execute combined read/write operation if it exists */
2416     if (csr_ops[csrno].op) {
2417         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
2418     }
2419 
2420     /* if no accessor exists then return failure */
2421     if (!csr_ops[csrno].read) {
2422         return RISCV_EXCP_ILLEGAL_INST;
2423     }
2424     /* read old value */
2425     ret = csr_ops[csrno].read(env, csrno, &old_value);
2426     if (ret != RISCV_EXCP_NONE) {
2427         return ret;
2428     }
2429 
2430     /* write value if writable and write mask set, otherwise drop writes */
2431     if (write_mask) {
2432         new_value = (old_value & ~write_mask) | (new_value & write_mask);
2433         if (csr_ops[csrno].write) {
2434             ret = csr_ops[csrno].write(env, csrno, new_value);
2435             if (ret != RISCV_EXCP_NONE) {
2436                 return ret;
2437             }
2438         }
2439     }
2440 
2441     /* return old value */
2442     if (ret_value) {
2443         *ret_value = old_value;
2444     }
2445 
2446     return RISCV_EXCP_NONE;
2447 }
2448 
2449 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
2450                            target_ulong *ret_value,
2451                            target_ulong new_value, target_ulong write_mask)
2452 {
2453     RISCVCPU *cpu = env_archcpu(env);
2454 
2455     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
2456     if (ret != RISCV_EXCP_NONE) {
2457         return ret;
2458     }
2459 
2460     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
2461 }
2462 
2463 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
2464                                         Int128 *ret_value,
2465                                         Int128 new_value,
2466                                         Int128 write_mask)
2467 {
2468     RISCVException ret;
2469     Int128 old_value;
2470 
2471     /* read old value */
2472     ret = csr_ops[csrno].read128(env, csrno, &old_value);
2473     if (ret != RISCV_EXCP_NONE) {
2474         return ret;
2475     }
2476 
2477     /* write value if writable and write mask set, otherwise drop writes */
2478     if (int128_nz(write_mask)) {
2479         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
2480                               int128_and(new_value, write_mask));
2481         if (csr_ops[csrno].write128) {
2482             ret = csr_ops[csrno].write128(env, csrno, new_value);
2483             if (ret != RISCV_EXCP_NONE) {
2484                 return ret;
2485             }
2486         } else if (csr_ops[csrno].write) {
2487             /* avoids having to write wrappers for all registers */
2488             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
2489             if (ret != RISCV_EXCP_NONE) {
2490                 return ret;
2491             }
2492         }
2493     }
2494 
2495     /* return old value */
2496     if (ret_value) {
2497         *ret_value = old_value;
2498     }
2499 
2500     return RISCV_EXCP_NONE;
2501 }
2502 
2503 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
2504                                 Int128 *ret_value,
2505                                 Int128 new_value, Int128 write_mask)
2506 {
2507     RISCVException ret;
2508     RISCVCPU *cpu = env_archcpu(env);
2509 
2510     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
2511     if (ret != RISCV_EXCP_NONE) {
2512         return ret;
2513     }
2514 
2515     if (csr_ops[csrno].read128) {
2516         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
2517     }
2518 
2519     /*
2520      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
2521      * at all defined.
2522      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
2523      * significant), for those, this fallback is correctly handling the accesses
2524      */
2525     target_ulong old_value;
2526     ret = riscv_csrrw_do64(env, csrno, &old_value,
2527                            int128_getlo(new_value),
2528                            int128_getlo(write_mask));
2529     if (ret == RISCV_EXCP_NONE && ret_value) {
2530         *ret_value = int128_make64(old_value);
2531     }
2532     return ret;
2533 }
2534 
2535 /*
2536  * Debugger support.  If not in user mode, set env->debugger before the
2537  * riscv_csrrw call and clear it after the call.
2538  */
2539 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
2540                                  target_ulong *ret_value,
2541                                  target_ulong new_value,
2542                                  target_ulong write_mask)
2543 {
2544     RISCVException ret;
2545 #if !defined(CONFIG_USER_ONLY)
2546     env->debugger = true;
2547 #endif
2548     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
2549 #if !defined(CONFIG_USER_ONLY)
2550     env->debugger = false;
2551 #endif
2552     return ret;
2553 }
2554 
2555 /* Control and Status Register function table */
2556 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
2557     /* User Floating-Point CSRs */
2558     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
2559     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
2560     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
2561     /* Vector CSRs */
2562     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
2563     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
2564     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
2565     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
2566     [CSR_VL]       = { "vl",       vs,     read_vl                    },
2567     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2568     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2569     /* User Timers and Counters */
2570     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2571     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2572     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2573     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2574 
2575     /*
2576      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2577      * rdtime callback is not provided by machine/platform emulation.
2578      */
2579     [CSR_TIME]  = { "time",  ctr,   read_time  },
2580     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2581 
2582 #if !defined(CONFIG_USER_ONLY)
2583     /* Machine Timers and Counters */
2584     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2585     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2586     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2587     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2588 
2589     /* Machine Information Registers */
2590     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2591     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2592     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2593     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2594 
2595     /* Machine Trap Setup */
2596     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2597                                                read_mstatus_i128                   },
2598     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2599                                                read_misa_i128                      },
2600     [CSR_MIDELEG]     = { "mideleg",    any,   NULL,    NULL,    rmw_mideleg       },
2601     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2602     [CSR_MIE]         = { "mie",        any,   NULL,    NULL,    rmw_mie           },
2603     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2604     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2605 
2606     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2607 
2608     /* Machine Trap Handling */
2609     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2610                                          read_mscratch_i128, write_mscratch_i128   },
2611     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2612     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2613     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2614     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2615 
2616     /* Virtual Interrupts for Supervisor Level (AIA) */
2617     [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
2618     [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
2619 
2620     /* Machine-Level High-Half CSRs (AIA) */
2621     [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
2622     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
2623     [CSR_MVIENH]   = { "mvienh",   aia_any32, read_zero,  write_ignore },
2624     [CSR_MVIPH]    = { "mviph",    aia_any32, read_zero,  write_ignore },
2625     [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
2626 
2627     /* Supervisor Trap Setup */
2628     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2629                                               read_sstatus_i128                 },
2630     [CSR_SIE]        = { "sie",        smode, NULL,   NULL,    rmw_sie          },
2631     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2632     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2633 
2634     /* Supervisor Trap Handling */
2635     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2636                                           read_sscratch_i128, write_sscratch_i128  },
2637     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2638     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2639     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2640     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2641 
2642     /* Supervisor Protection and Translation */
2643     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2644 
2645     /* Supervisor-Level High-Half CSRs (AIA) */
2646     [CSR_SIEH]       = { "sieh",   aia_smode32, NULL, NULL, rmw_sieh },
2647     [CSR_SIPH]       = { "siph",   aia_smode32, NULL, NULL, rmw_siph },
2648 
2649     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2650     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2651     [CSR_HIDELEG]     = { "hideleg",     hmode,   NULL,   NULL,     rmw_hideleg       },
2652     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2653     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2654     [CSR_HIE]         = { "hie",         hmode,   NULL,   NULL,     rmw_hie           },
2655     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2656     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
2657     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2658     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2659     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       NULL              },
2660     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2661     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2662     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2663 
2664     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2665     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2666     [CSR_VSIE]        = { "vsie",        hmode,   NULL,    NULL,    rmw_vsie          },
2667     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2668     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2669     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2670     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2671     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2672     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2673 
2674     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2675     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2676 
2677     /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
2678     [CSR_HVIEN]       = { "hvien",       aia_hmode, read_zero, write_ignore },
2679     [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl, write_hvictl },
2680     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
2681     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
2682 
2683     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
2684     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
2685     [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
2686     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
2687     [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h, write_hviprio1h },
2688     [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h, write_hviprio2h },
2689     [CSR_VSIEH]       = { "vsieh",       aia_hmode32, NULL, NULL, rmw_vsieh },
2690     [CSR_VSIPH]       = { "vsiph",       aia_hmode32, NULL, NULL, rmw_vsiph },
2691 
2692     /* Physical Memory Protection */
2693     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2694     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2695     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2696     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2697     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2698     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2699     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2700     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2701     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2702     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2703     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2704     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2705     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2706     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2707     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2708     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2709     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2710     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2711     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2712     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2713     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2714 
2715     /* User Pointer Masking */
2716     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2717     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2718     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2719     /* Machine Pointer Masking */
2720     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2721     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2722     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2723     /* Supervisor Pointer Masking */
2724     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2725     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2726     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2727 
2728     /* Performance Counters */
2729     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2730     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2731     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2732     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2733     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2734     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2735     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2736     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2737     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2738     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2739     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2740     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2741     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2742     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2743     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2744     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2745     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2746     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2747     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2748     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2749     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2750     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2751     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2752     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2753     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2754     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2755     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2756     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2757     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2758 
2759     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2760     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2761     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2762     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2763     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2764     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2765     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2766     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2767     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2768     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2769     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2770     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2771     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2772     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2773     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2774     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2775     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2776     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2777     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2778     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2779     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2780     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2781     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2782     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2783     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2784     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2785     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2786     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2787     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2788 
2789     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2790     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2791     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2792     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2793     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2794     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2795     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2796     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2797     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2798     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2799     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2800     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2801     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2802     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2803     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2804     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2805     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2806     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2807     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2808     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2809     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2810     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2811     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2812     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2813     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2814     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2815     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2816     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2817     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2818 
2819     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2820     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2821     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2822     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2823     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2824     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2825     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2826     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2827     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2828     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2829     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2830     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2831     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2832     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2833     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2834     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2835     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2836     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2837     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2838     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2839     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2840     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2841     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2842     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2843     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2844     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2845     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2846     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2847     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2848 
2849     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2850     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2851     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2852     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2853     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2854     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2855     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2856     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2857     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2858     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2859     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2860     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2861     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2862     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2863     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2864     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2865     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2866     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2867     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2868     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2869     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2870     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2871     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2872     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2873     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2874     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2875     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2876     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2877     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2878 #endif /* !CONFIG_USER_ONLY */
2879 };
2880