xref: /openbmc/qemu/target/riscv/csr.c (revision cd032fe7) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 
26 /* CSR function table public API */
27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28 {
29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30 }
31 
32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33 {
34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35 }
36 
37 /* Predicates */
38 static RISCVException fs(CPURISCVState *env, int csrno)
39 {
40 #if !defined(CONFIG_USER_ONLY)
41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
42         return RISCV_EXCP_ILLEGAL_INST;
43     }
44 #endif
45     return RISCV_EXCP_NONE;
46 }
47 
48 static RISCVException vs(CPURISCVState *env, int csrno)
49 {
50     CPUState *cs = env_cpu(env);
51     RISCVCPU *cpu = RISCV_CPU(cs);
52 
53     if (env->misa_ext & RVV ||
54         cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
55 #if !defined(CONFIG_USER_ONLY)
56         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
57             return RISCV_EXCP_ILLEGAL_INST;
58         }
59 #endif
60         return RISCV_EXCP_NONE;
61     }
62     return RISCV_EXCP_ILLEGAL_INST;
63 }
64 
65 static RISCVException ctr(CPURISCVState *env, int csrno)
66 {
67 #if !defined(CONFIG_USER_ONLY)
68     CPUState *cs = env_cpu(env);
69     RISCVCPU *cpu = RISCV_CPU(cs);
70 
71     if (!cpu->cfg.ext_counters) {
72         /* The Counters extensions is not enabled */
73         return RISCV_EXCP_ILLEGAL_INST;
74     }
75 
76     if (riscv_cpu_virt_enabled(env)) {
77         switch (csrno) {
78         case CSR_CYCLE:
79             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
80                 get_field(env->mcounteren, COUNTEREN_CY)) {
81                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
82             }
83             break;
84         case CSR_TIME:
85             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
86                 get_field(env->mcounteren, COUNTEREN_TM)) {
87                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
88             }
89             break;
90         case CSR_INSTRET:
91             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
92                 get_field(env->mcounteren, COUNTEREN_IR)) {
93                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
94             }
95             break;
96         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
97             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
98                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
99                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
100             }
101             break;
102         }
103         if (riscv_cpu_mxl(env) == MXL_RV32) {
104             switch (csrno) {
105             case CSR_CYCLEH:
106                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
107                     get_field(env->mcounteren, COUNTEREN_CY)) {
108                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
109                 }
110                 break;
111             case CSR_TIMEH:
112                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
113                     get_field(env->mcounteren, COUNTEREN_TM)) {
114                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
115                 }
116                 break;
117             case CSR_INSTRETH:
118                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
119                     get_field(env->mcounteren, COUNTEREN_IR)) {
120                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
121                 }
122                 break;
123             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
124                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
125                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
126                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
127                 }
128                 break;
129             }
130         }
131     }
132 #endif
133     return RISCV_EXCP_NONE;
134 }
135 
136 static RISCVException ctr32(CPURISCVState *env, int csrno)
137 {
138     if (riscv_cpu_mxl(env) != MXL_RV32) {
139         return RISCV_EXCP_ILLEGAL_INST;
140     }
141 
142     return ctr(env, csrno);
143 }
144 
145 #if !defined(CONFIG_USER_ONLY)
146 static RISCVException any(CPURISCVState *env, int csrno)
147 {
148     return RISCV_EXCP_NONE;
149 }
150 
151 static RISCVException any32(CPURISCVState *env, int csrno)
152 {
153     if (riscv_cpu_mxl(env) != MXL_RV32) {
154         return RISCV_EXCP_ILLEGAL_INST;
155     }
156 
157     return any(env, csrno);
158 
159 }
160 
161 static RISCVException smode(CPURISCVState *env, int csrno)
162 {
163     if (riscv_has_ext(env, RVS)) {
164         return RISCV_EXCP_NONE;
165     }
166 
167     return RISCV_EXCP_ILLEGAL_INST;
168 }
169 
170 static RISCVException hmode(CPURISCVState *env, int csrno)
171 {
172     if (riscv_has_ext(env, RVS) &&
173         riscv_has_ext(env, RVH)) {
174         /* Hypervisor extension is supported */
175         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
176             env->priv == PRV_M) {
177             return RISCV_EXCP_NONE;
178         } else {
179             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
180         }
181     }
182 
183     return RISCV_EXCP_ILLEGAL_INST;
184 }
185 
186 static RISCVException hmode32(CPURISCVState *env, int csrno)
187 {
188     if (riscv_cpu_mxl(env) != MXL_RV32) {
189         if (!riscv_cpu_virt_enabled(env)) {
190             return RISCV_EXCP_ILLEGAL_INST;
191         } else {
192             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
193         }
194     }
195 
196     return hmode(env, csrno);
197 
198 }
199 
200 /* Checks if PointerMasking registers could be accessed */
201 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
202 {
203     /* Check if j-ext is present */
204     if (riscv_has_ext(env, RVJ)) {
205         return RISCV_EXCP_NONE;
206     }
207     return RISCV_EXCP_ILLEGAL_INST;
208 }
209 
210 static RISCVException pmp(CPURISCVState *env, int csrno)
211 {
212     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
213         return RISCV_EXCP_NONE;
214     }
215 
216     return RISCV_EXCP_ILLEGAL_INST;
217 }
218 
219 static RISCVException epmp(CPURISCVState *env, int csrno)
220 {
221     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
222         return RISCV_EXCP_NONE;
223     }
224 
225     return RISCV_EXCP_ILLEGAL_INST;
226 }
227 #endif
228 
229 /* User Floating-Point CSRs */
230 static RISCVException read_fflags(CPURISCVState *env, int csrno,
231                                   target_ulong *val)
232 {
233     *val = riscv_cpu_get_fflags(env);
234     return RISCV_EXCP_NONE;
235 }
236 
237 static RISCVException write_fflags(CPURISCVState *env, int csrno,
238                                    target_ulong val)
239 {
240 #if !defined(CONFIG_USER_ONLY)
241     env->mstatus |= MSTATUS_FS;
242 #endif
243     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
244     return RISCV_EXCP_NONE;
245 }
246 
247 static RISCVException read_frm(CPURISCVState *env, int csrno,
248                                target_ulong *val)
249 {
250     *val = env->frm;
251     return RISCV_EXCP_NONE;
252 }
253 
254 static RISCVException write_frm(CPURISCVState *env, int csrno,
255                                 target_ulong val)
256 {
257 #if !defined(CONFIG_USER_ONLY)
258     env->mstatus |= MSTATUS_FS;
259 #endif
260     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
261     return RISCV_EXCP_NONE;
262 }
263 
264 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
265                                 target_ulong *val)
266 {
267     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
268         | (env->frm << FSR_RD_SHIFT);
269     return RISCV_EXCP_NONE;
270 }
271 
272 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
273                                  target_ulong val)
274 {
275 #if !defined(CONFIG_USER_ONLY)
276     env->mstatus |= MSTATUS_FS;
277 #endif
278     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
279     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
280     return RISCV_EXCP_NONE;
281 }
282 
283 static RISCVException read_vtype(CPURISCVState *env, int csrno,
284                                  target_ulong *val)
285 {
286     uint64_t vill;
287     switch (env->xl) {
288     case MXL_RV32:
289         vill = (uint32_t)env->vill << 31;
290         break;
291     case MXL_RV64:
292         vill = (uint64_t)env->vill << 63;
293         break;
294     default:
295         g_assert_not_reached();
296     }
297     *val = (target_ulong)vill | env->vtype;
298     return RISCV_EXCP_NONE;
299 }
300 
301 static RISCVException read_vl(CPURISCVState *env, int csrno,
302                               target_ulong *val)
303 {
304     *val = env->vl;
305     return RISCV_EXCP_NONE;
306 }
307 
308 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
309 {
310     *val = env_archcpu(env)->cfg.vlen >> 3;
311     return RISCV_EXCP_NONE;
312 }
313 
314 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
315                                 target_ulong *val)
316 {
317     *val = env->vxrm;
318     return RISCV_EXCP_NONE;
319 }
320 
321 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
322                                  target_ulong val)
323 {
324 #if !defined(CONFIG_USER_ONLY)
325     env->mstatus |= MSTATUS_VS;
326 #endif
327     env->vxrm = val;
328     return RISCV_EXCP_NONE;
329 }
330 
331 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
332                                  target_ulong *val)
333 {
334     *val = env->vxsat;
335     return RISCV_EXCP_NONE;
336 }
337 
338 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
339                                   target_ulong val)
340 {
341 #if !defined(CONFIG_USER_ONLY)
342     env->mstatus |= MSTATUS_VS;
343 #endif
344     env->vxsat = val;
345     return RISCV_EXCP_NONE;
346 }
347 
348 static RISCVException read_vstart(CPURISCVState *env, int csrno,
349                                   target_ulong *val)
350 {
351     *val = env->vstart;
352     return RISCV_EXCP_NONE;
353 }
354 
355 static RISCVException write_vstart(CPURISCVState *env, int csrno,
356                                    target_ulong val)
357 {
358 #if !defined(CONFIG_USER_ONLY)
359     env->mstatus |= MSTATUS_VS;
360 #endif
361     /*
362      * The vstart CSR is defined to have only enough writable bits
363      * to hold the largest element index, i.e. lg2(VLEN) bits.
364      */
365     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
366     return RISCV_EXCP_NONE;
367 }
368 
369 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
370 {
371     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
372     return RISCV_EXCP_NONE;
373 }
374 
375 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
376 {
377 #if !defined(CONFIG_USER_ONLY)
378     env->mstatus |= MSTATUS_VS;
379 #endif
380     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
381     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
382     return RISCV_EXCP_NONE;
383 }
384 
385 /* User Timers and Counters */
386 static RISCVException read_instret(CPURISCVState *env, int csrno,
387                                    target_ulong *val)
388 {
389 #if !defined(CONFIG_USER_ONLY)
390     if (icount_enabled()) {
391         *val = icount_get();
392     } else {
393         *val = cpu_get_host_ticks();
394     }
395 #else
396     *val = cpu_get_host_ticks();
397 #endif
398     return RISCV_EXCP_NONE;
399 }
400 
401 static RISCVException read_instreth(CPURISCVState *env, int csrno,
402                                     target_ulong *val)
403 {
404 #if !defined(CONFIG_USER_ONLY)
405     if (icount_enabled()) {
406         *val = icount_get() >> 32;
407     } else {
408         *val = cpu_get_host_ticks() >> 32;
409     }
410 #else
411     *val = cpu_get_host_ticks() >> 32;
412 #endif
413     return RISCV_EXCP_NONE;
414 }
415 
416 #if defined(CONFIG_USER_ONLY)
417 static RISCVException read_time(CPURISCVState *env, int csrno,
418                                 target_ulong *val)
419 {
420     *val = cpu_get_host_ticks();
421     return RISCV_EXCP_NONE;
422 }
423 
424 static RISCVException read_timeh(CPURISCVState *env, int csrno,
425                                  target_ulong *val)
426 {
427     *val = cpu_get_host_ticks() >> 32;
428     return RISCV_EXCP_NONE;
429 }
430 
431 #else /* CONFIG_USER_ONLY */
432 
433 static RISCVException read_time(CPURISCVState *env, int csrno,
434                                 target_ulong *val)
435 {
436     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
437 
438     if (!env->rdtime_fn) {
439         return RISCV_EXCP_ILLEGAL_INST;
440     }
441 
442     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
443     return RISCV_EXCP_NONE;
444 }
445 
446 static RISCVException read_timeh(CPURISCVState *env, int csrno,
447                                  target_ulong *val)
448 {
449     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
450 
451     if (!env->rdtime_fn) {
452         return RISCV_EXCP_ILLEGAL_INST;
453     }
454 
455     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
456     return RISCV_EXCP_NONE;
457 }
458 
459 /* Machine constants */
460 
461 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
462 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
463 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
464 #define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS)
465 
466 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
467                                            VS_MODE_INTERRUPTS;
468 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
469 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
470                                      HS_MODE_INTERRUPTS;
471 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
472                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
473                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
474                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
475                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
476                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
477                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
478                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
479                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
480                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
481                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
482                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
483                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
484                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
485                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
486                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
487                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
488                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
489                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
490 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
491     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
492       (1ULL << (RISCV_EXCP_VS_ECALL)) |
493       (1ULL << (RISCV_EXCP_M_ECALL)) |
494       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
495       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
496       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
497       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
498 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
499     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
500     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
501 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
502 static const target_ulong hip_writable_mask = MIP_VSSIP;
503 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
504 static const target_ulong vsip_writable_mask = MIP_VSSIP;
505 
506 static const char valid_vm_1_10_32[16] = {
507     [VM_1_10_MBARE] = 1,
508     [VM_1_10_SV32] = 1
509 };
510 
511 static const char valid_vm_1_10_64[16] = {
512     [VM_1_10_MBARE] = 1,
513     [VM_1_10_SV39] = 1,
514     [VM_1_10_SV48] = 1,
515     [VM_1_10_SV57] = 1
516 };
517 
518 /* Machine Information Registers */
519 static RISCVException read_zero(CPURISCVState *env, int csrno,
520                                 target_ulong *val)
521 {
522     *val = 0;
523     return RISCV_EXCP_NONE;
524 }
525 
526 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
527                                    target_ulong *val)
528 {
529     *val = env->mhartid;
530     return RISCV_EXCP_NONE;
531 }
532 
533 /* Machine Trap Setup */
534 
535 /* We do not store SD explicitly, only compute it on demand. */
536 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
537 {
538     if ((status & MSTATUS_FS) == MSTATUS_FS ||
539         (status & MSTATUS_VS) == MSTATUS_VS ||
540         (status & MSTATUS_XS) == MSTATUS_XS) {
541         switch (xl) {
542         case MXL_RV32:
543             return status | MSTATUS32_SD;
544         case MXL_RV64:
545             return status | MSTATUS64_SD;
546         case MXL_RV128:
547             return MSTATUSH128_SD;
548         default:
549             g_assert_not_reached();
550         }
551     }
552     return status;
553 }
554 
555 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
556                                    target_ulong *val)
557 {
558     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
559     return RISCV_EXCP_NONE;
560 }
561 
562 static int validate_vm(CPURISCVState *env, target_ulong vm)
563 {
564     if (riscv_cpu_mxl(env) == MXL_RV32) {
565         return valid_vm_1_10_32[vm & 0xf];
566     } else {
567         return valid_vm_1_10_64[vm & 0xf];
568     }
569 }
570 
571 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
572                                     target_ulong val)
573 {
574     uint64_t mstatus = env->mstatus;
575     uint64_t mask = 0;
576     RISCVMXL xl = riscv_cpu_mxl(env);
577 
578     /* flush tlb on mstatus fields that affect VM */
579     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
580             MSTATUS_MPRV | MSTATUS_SUM)) {
581         tlb_flush(env_cpu(env));
582     }
583     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
584         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
585         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
586         MSTATUS_TW | MSTATUS_VS;
587 
588     if (xl != MXL_RV32 || env->debugger) {
589         /*
590          * RV32: MPV and GVA are not in mstatus. The current plan is to
591          * add them to mstatush. For now, we just don't support it.
592          */
593         mask |= MSTATUS_MPV | MSTATUS_GVA;
594         if ((val & MSTATUS64_UXL) != 0) {
595             mask |= MSTATUS64_UXL;
596         }
597     }
598 
599     mstatus = (mstatus & ~mask) | (val & mask);
600 
601     if (xl > MXL_RV32) {
602         /* SXL field is for now read only */
603         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
604     }
605     env->mstatus = mstatus;
606     env->xl = cpu_recompute_xl(env);
607 
608     return RISCV_EXCP_NONE;
609 }
610 
611 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
612                                     target_ulong *val)
613 {
614     *val = env->mstatus >> 32;
615     return RISCV_EXCP_NONE;
616 }
617 
618 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
619                                      target_ulong val)
620 {
621     uint64_t valh = (uint64_t)val << 32;
622     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
623 
624     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
625         tlb_flush(env_cpu(env));
626     }
627 
628     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
629 
630     return RISCV_EXCP_NONE;
631 }
632 
633 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
634                                         Int128 *val)
635 {
636     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
637     return RISCV_EXCP_NONE;
638 }
639 
640 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
641                                      Int128 *val)
642 {
643     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
644     return RISCV_EXCP_NONE;
645 }
646 
647 static RISCVException read_misa(CPURISCVState *env, int csrno,
648                                 target_ulong *val)
649 {
650     target_ulong misa;
651 
652     switch (env->misa_mxl) {
653     case MXL_RV32:
654         misa = (target_ulong)MXL_RV32 << 30;
655         break;
656 #ifdef TARGET_RISCV64
657     case MXL_RV64:
658         misa = (target_ulong)MXL_RV64 << 62;
659         break;
660 #endif
661     default:
662         g_assert_not_reached();
663     }
664 
665     *val = misa | env->misa_ext;
666     return RISCV_EXCP_NONE;
667 }
668 
669 static RISCVException write_misa(CPURISCVState *env, int csrno,
670                                  target_ulong val)
671 {
672     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
673         /* drop write to misa */
674         return RISCV_EXCP_NONE;
675     }
676 
677     /* 'I' or 'E' must be present */
678     if (!(val & (RVI | RVE))) {
679         /* It is not, drop write to misa */
680         return RISCV_EXCP_NONE;
681     }
682 
683     /* 'E' excludes all other extensions */
684     if (val & RVE) {
685         /* when we support 'E' we can do "val = RVE;" however
686          * for now we just drop writes if 'E' is present.
687          */
688         return RISCV_EXCP_NONE;
689     }
690 
691     /*
692      * misa.MXL writes are not supported by QEMU.
693      * Drop writes to those bits.
694      */
695 
696     /* Mask extensions that are not supported by this hart */
697     val &= env->misa_ext_mask;
698 
699     /* Mask extensions that are not supported by QEMU */
700     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
701 
702     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
703     if ((val & RVD) && !(val & RVF)) {
704         val &= ~RVD;
705     }
706 
707     /* Suppress 'C' if next instruction is not aligned
708      * TODO: this should check next_pc
709      */
710     if ((val & RVC) && (GETPC() & ~3) != 0) {
711         val &= ~RVC;
712     }
713 
714     /* If nothing changed, do nothing. */
715     if (val == env->misa_ext) {
716         return RISCV_EXCP_NONE;
717     }
718 
719     /* flush translation cache */
720     tb_flush(env_cpu(env));
721     env->misa_ext = val;
722     env->xl = riscv_cpu_mxl(env);
723     return RISCV_EXCP_NONE;
724 }
725 
726 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
727                                    target_ulong *val)
728 {
729     *val = env->medeleg;
730     return RISCV_EXCP_NONE;
731 }
732 
733 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
734                                     target_ulong val)
735 {
736     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
737     return RISCV_EXCP_NONE;
738 }
739 
740 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
741                                    target_ulong *val)
742 {
743     *val = env->mideleg;
744     return RISCV_EXCP_NONE;
745 }
746 
747 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
748                                     target_ulong val)
749 {
750     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
751     if (riscv_has_ext(env, RVH)) {
752         env->mideleg |= HS_MODE_INTERRUPTS;
753     }
754     return RISCV_EXCP_NONE;
755 }
756 
757 static RISCVException read_mie(CPURISCVState *env, int csrno,
758                                target_ulong *val)
759 {
760     *val = env->mie;
761     return RISCV_EXCP_NONE;
762 }
763 
764 static RISCVException write_mie(CPURISCVState *env, int csrno,
765                                 target_ulong val)
766 {
767     env->mie = (env->mie & ~all_ints) | (val & all_ints);
768     if (!riscv_has_ext(env, RVH)) {
769         env->mie &= ~MIP_SGEIP;
770     }
771     return RISCV_EXCP_NONE;
772 }
773 
774 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
775                                  target_ulong *val)
776 {
777     *val = env->mtvec;
778     return RISCV_EXCP_NONE;
779 }
780 
781 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
782                                   target_ulong val)
783 {
784     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
785     if ((val & 3) < 2) {
786         env->mtvec = val;
787     } else {
788         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
789     }
790     return RISCV_EXCP_NONE;
791 }
792 
793 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
794                                       target_ulong *val)
795 {
796     *val = env->mcounteren;
797     return RISCV_EXCP_NONE;
798 }
799 
800 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
801                                        target_ulong val)
802 {
803     env->mcounteren = val;
804     return RISCV_EXCP_NONE;
805 }
806 
807 /* Machine Trap Handling */
808 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
809                                          Int128 *val)
810 {
811     *val = int128_make128(env->mscratch, env->mscratchh);
812     return RISCV_EXCP_NONE;
813 }
814 
815 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
816                                           Int128 val)
817 {
818     env->mscratch = int128_getlo(val);
819     env->mscratchh = int128_gethi(val);
820     return RISCV_EXCP_NONE;
821 }
822 
823 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
824                                     target_ulong *val)
825 {
826     *val = env->mscratch;
827     return RISCV_EXCP_NONE;
828 }
829 
830 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
831                                      target_ulong val)
832 {
833     env->mscratch = val;
834     return RISCV_EXCP_NONE;
835 }
836 
837 static RISCVException read_mepc(CPURISCVState *env, int csrno,
838                                      target_ulong *val)
839 {
840     *val = env->mepc;
841     return RISCV_EXCP_NONE;
842 }
843 
844 static RISCVException write_mepc(CPURISCVState *env, int csrno,
845                                      target_ulong val)
846 {
847     env->mepc = val;
848     return RISCV_EXCP_NONE;
849 }
850 
851 static RISCVException read_mcause(CPURISCVState *env, int csrno,
852                                      target_ulong *val)
853 {
854     *val = env->mcause;
855     return RISCV_EXCP_NONE;
856 }
857 
858 static RISCVException write_mcause(CPURISCVState *env, int csrno,
859                                      target_ulong val)
860 {
861     env->mcause = val;
862     return RISCV_EXCP_NONE;
863 }
864 
865 static RISCVException read_mtval(CPURISCVState *env, int csrno,
866                                  target_ulong *val)
867 {
868     *val = env->mtval;
869     return RISCV_EXCP_NONE;
870 }
871 
872 static RISCVException write_mtval(CPURISCVState *env, int csrno,
873                                   target_ulong val)
874 {
875     env->mtval = val;
876     return RISCV_EXCP_NONE;
877 }
878 
879 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
880                               target_ulong *ret_value,
881                               target_ulong new_value, target_ulong write_mask)
882 {
883     RISCVCPU *cpu = env_archcpu(env);
884     /* Allow software control of delegable interrupts not claimed by hardware */
885     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
886     uint32_t gin, old_mip;
887 
888     if (mask) {
889         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
890     } else {
891         old_mip = env->mip;
892     }
893 
894     if (csrno != CSR_HVIP) {
895         gin = get_field(env->hstatus, HSTATUS_VGEIN);
896         old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0;
897     }
898 
899     if (ret_value) {
900         *ret_value = old_mip;
901     }
902 
903     return RISCV_EXCP_NONE;
904 }
905 
906 /* Supervisor Trap Setup */
907 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
908                                         Int128 *val)
909 {
910     uint64_t mask = sstatus_v1_10_mask;
911     uint64_t sstatus = env->mstatus & mask;
912     if (env->xl != MXL_RV32 || env->debugger) {
913         mask |= SSTATUS64_UXL;
914     }
915 
916     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
917     return RISCV_EXCP_NONE;
918 }
919 
920 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
921                                    target_ulong *val)
922 {
923     target_ulong mask = (sstatus_v1_10_mask);
924     if (env->xl != MXL_RV32 || env->debugger) {
925         mask |= SSTATUS64_UXL;
926     }
927     /* TODO: Use SXL not MXL. */
928     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
929     return RISCV_EXCP_NONE;
930 }
931 
932 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
933                                     target_ulong val)
934 {
935     target_ulong mask = (sstatus_v1_10_mask);
936 
937     if (env->xl != MXL_RV32 || env->debugger) {
938         if ((val & SSTATUS64_UXL) != 0) {
939             mask |= SSTATUS64_UXL;
940         }
941     }
942     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
943     return write_mstatus(env, CSR_MSTATUS, newval);
944 }
945 
946 static RISCVException read_vsie(CPURISCVState *env, int csrno,
947                                 target_ulong *val)
948 {
949     /* Shift the VS bits to their S bit location in vsie */
950     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
951     return RISCV_EXCP_NONE;
952 }
953 
954 static RISCVException read_sie(CPURISCVState *env, int csrno,
955                                target_ulong *val)
956 {
957     if (riscv_cpu_virt_enabled(env)) {
958         read_vsie(env, CSR_VSIE, val);
959     } else {
960         *val = env->mie & env->mideleg;
961     }
962     return RISCV_EXCP_NONE;
963 }
964 
965 static RISCVException write_vsie(CPURISCVState *env, int csrno,
966                                  target_ulong val)
967 {
968     /* Shift the S bits to their VS bit location in mie */
969     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
970                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
971     return write_mie(env, CSR_MIE, newval);
972 }
973 
974 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
975 {
976     if (riscv_cpu_virt_enabled(env)) {
977         write_vsie(env, CSR_VSIE, val);
978     } else {
979         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
980                               (val & S_MODE_INTERRUPTS);
981         write_mie(env, CSR_MIE, newval);
982     }
983 
984     return RISCV_EXCP_NONE;
985 }
986 
987 static RISCVException read_stvec(CPURISCVState *env, int csrno,
988                                  target_ulong *val)
989 {
990     *val = env->stvec;
991     return RISCV_EXCP_NONE;
992 }
993 
994 static RISCVException write_stvec(CPURISCVState *env, int csrno,
995                                   target_ulong val)
996 {
997     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
998     if ((val & 3) < 2) {
999         env->stvec = val;
1000     } else {
1001         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
1002     }
1003     return RISCV_EXCP_NONE;
1004 }
1005 
1006 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
1007                                       target_ulong *val)
1008 {
1009     *val = env->scounteren;
1010     return RISCV_EXCP_NONE;
1011 }
1012 
1013 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
1014                                        target_ulong val)
1015 {
1016     env->scounteren = val;
1017     return RISCV_EXCP_NONE;
1018 }
1019 
1020 /* Supervisor Trap Handling */
1021 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
1022                                          Int128 *val)
1023 {
1024     *val = int128_make128(env->sscratch, env->sscratchh);
1025     return RISCV_EXCP_NONE;
1026 }
1027 
1028 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
1029                                           Int128 val)
1030 {
1031     env->sscratch = int128_getlo(val);
1032     env->sscratchh = int128_gethi(val);
1033     return RISCV_EXCP_NONE;
1034 }
1035 
1036 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
1037                                     target_ulong *val)
1038 {
1039     *val = env->sscratch;
1040     return RISCV_EXCP_NONE;
1041 }
1042 
1043 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1044                                      target_ulong val)
1045 {
1046     env->sscratch = val;
1047     return RISCV_EXCP_NONE;
1048 }
1049 
1050 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1051                                 target_ulong *val)
1052 {
1053     *val = env->sepc;
1054     return RISCV_EXCP_NONE;
1055 }
1056 
1057 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1058                                  target_ulong val)
1059 {
1060     env->sepc = val;
1061     return RISCV_EXCP_NONE;
1062 }
1063 
1064 static RISCVException read_scause(CPURISCVState *env, int csrno,
1065                                   target_ulong *val)
1066 {
1067     *val = env->scause;
1068     return RISCV_EXCP_NONE;
1069 }
1070 
1071 static RISCVException write_scause(CPURISCVState *env, int csrno,
1072                                    target_ulong val)
1073 {
1074     env->scause = val;
1075     return RISCV_EXCP_NONE;
1076 }
1077 
1078 static RISCVException read_stval(CPURISCVState *env, int csrno,
1079                                  target_ulong *val)
1080 {
1081     *val = env->stval;
1082     return RISCV_EXCP_NONE;
1083 }
1084 
1085 static RISCVException write_stval(CPURISCVState *env, int csrno,
1086                                   target_ulong val)
1087 {
1088     env->stval = val;
1089     return RISCV_EXCP_NONE;
1090 }
1091 
1092 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1093                                target_ulong *ret_value,
1094                                target_ulong new_value, target_ulong write_mask)
1095 {
1096     /* Shift the S bits to their VS bit location in mip */
1097     int ret = rmw_mip(env, csrno, ret_value, new_value << 1,
1098                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
1099 
1100     if (ret_value) {
1101         *ret_value &= VS_MODE_INTERRUPTS;
1102         /* Shift the VS bits to their S bit location in vsip */
1103         *ret_value >>= 1;
1104     }
1105     return ret;
1106 }
1107 
1108 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1109                               target_ulong *ret_value,
1110                               target_ulong new_value, target_ulong write_mask)
1111 {
1112     int ret;
1113 
1114     if (riscv_cpu_virt_enabled(env)) {
1115         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
1116     } else {
1117         ret = rmw_mip(env, csrno, ret_value, new_value,
1118                       write_mask & env->mideleg & sip_writable_mask);
1119     }
1120 
1121     if (ret_value) {
1122         *ret_value &= env->mideleg & S_MODE_INTERRUPTS;
1123     }
1124     return ret;
1125 }
1126 
1127 /* Supervisor Protection and Translation */
1128 static RISCVException read_satp(CPURISCVState *env, int csrno,
1129                                 target_ulong *val)
1130 {
1131     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1132         *val = 0;
1133         return RISCV_EXCP_NONE;
1134     }
1135 
1136     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1137         return RISCV_EXCP_ILLEGAL_INST;
1138     } else {
1139         *val = env->satp;
1140     }
1141 
1142     return RISCV_EXCP_NONE;
1143 }
1144 
1145 static RISCVException write_satp(CPURISCVState *env, int csrno,
1146                                  target_ulong val)
1147 {
1148     target_ulong vm, mask, asid;
1149 
1150     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1151         return RISCV_EXCP_NONE;
1152     }
1153 
1154     if (riscv_cpu_mxl(env) == MXL_RV32) {
1155         vm = validate_vm(env, get_field(val, SATP32_MODE));
1156         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1157         asid = (val ^ env->satp) & SATP32_ASID;
1158     } else {
1159         vm = validate_vm(env, get_field(val, SATP64_MODE));
1160         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1161         asid = (val ^ env->satp) & SATP64_ASID;
1162     }
1163 
1164     if (vm && mask) {
1165         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1166             return RISCV_EXCP_ILLEGAL_INST;
1167         } else {
1168             if (asid) {
1169                 tlb_flush(env_cpu(env));
1170             }
1171             env->satp = val;
1172         }
1173     }
1174     return RISCV_EXCP_NONE;
1175 }
1176 
1177 /* Hypervisor Extensions */
1178 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1179                                    target_ulong *val)
1180 {
1181     *val = env->hstatus;
1182     if (riscv_cpu_mxl(env) != MXL_RV32) {
1183         /* We only support 64-bit VSXL */
1184         *val = set_field(*val, HSTATUS_VSXL, 2);
1185     }
1186     /* We only support little endian */
1187     *val = set_field(*val, HSTATUS_VSBE, 0);
1188     return RISCV_EXCP_NONE;
1189 }
1190 
1191 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1192                                     target_ulong val)
1193 {
1194     env->hstatus = val;
1195     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1196         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1197     }
1198     if (get_field(val, HSTATUS_VSBE) != 0) {
1199         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1200     }
1201     return RISCV_EXCP_NONE;
1202 }
1203 
1204 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1205                                    target_ulong *val)
1206 {
1207     *val = env->hedeleg;
1208     return RISCV_EXCP_NONE;
1209 }
1210 
1211 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1212                                     target_ulong val)
1213 {
1214     env->hedeleg = val & vs_delegable_excps;
1215     return RISCV_EXCP_NONE;
1216 }
1217 
1218 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1219                                    target_ulong *val)
1220 {
1221     *val = env->hideleg;
1222     return RISCV_EXCP_NONE;
1223 }
1224 
1225 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1226                                     target_ulong val)
1227 {
1228     env->hideleg = val & vs_delegable_ints;
1229     return RISCV_EXCP_NONE;
1230 }
1231 
1232 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1233                                target_ulong *ret_value,
1234                                target_ulong new_value, target_ulong write_mask)
1235 {
1236     int ret = rmw_mip(env, csrno, ret_value, new_value,
1237                       write_mask & hvip_writable_mask);
1238 
1239     if (ret_value) {
1240         *ret_value &= VS_MODE_INTERRUPTS;
1241     }
1242     return ret;
1243 }
1244 
1245 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1246                               target_ulong *ret_value,
1247                               target_ulong new_value, target_ulong write_mask)
1248 {
1249     int ret = rmw_mip(env, csrno, ret_value, new_value,
1250                       write_mask & hip_writable_mask);
1251 
1252     if (ret_value) {
1253         *ret_value &= HS_MODE_INTERRUPTS;
1254     }
1255     return ret;
1256 }
1257 
1258 static RISCVException read_hie(CPURISCVState *env, int csrno,
1259                                target_ulong *val)
1260 {
1261     *val = env->mie & HS_MODE_INTERRUPTS;
1262     return RISCV_EXCP_NONE;
1263 }
1264 
1265 static RISCVException write_hie(CPURISCVState *env, int csrno,
1266                                 target_ulong val)
1267 {
1268     target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS);
1269     return write_mie(env, CSR_MIE, newval);
1270 }
1271 
1272 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1273                                       target_ulong *val)
1274 {
1275     *val = env->hcounteren;
1276     return RISCV_EXCP_NONE;
1277 }
1278 
1279 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1280                                        target_ulong val)
1281 {
1282     env->hcounteren = val;
1283     return RISCV_EXCP_NONE;
1284 }
1285 
1286 static RISCVException read_hgeie(CPURISCVState *env, int csrno,
1287                                  target_ulong *val)
1288 {
1289     if (val) {
1290         *val = env->hgeie;
1291     }
1292     return RISCV_EXCP_NONE;
1293 }
1294 
1295 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1296                                   target_ulong val)
1297 {
1298     /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
1299     val &= ((((target_ulong)1) << env->geilen) - 1) << 1;
1300     env->hgeie = val;
1301     /* Update mip.SGEIP bit */
1302     riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP,
1303                          BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1304     return RISCV_EXCP_NONE;
1305 }
1306 
1307 static RISCVException read_htval(CPURISCVState *env, int csrno,
1308                                  target_ulong *val)
1309 {
1310     *val = env->htval;
1311     return RISCV_EXCP_NONE;
1312 }
1313 
1314 static RISCVException write_htval(CPURISCVState *env, int csrno,
1315                                   target_ulong val)
1316 {
1317     env->htval = val;
1318     return RISCV_EXCP_NONE;
1319 }
1320 
1321 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1322                                   target_ulong *val)
1323 {
1324     *val = env->htinst;
1325     return RISCV_EXCP_NONE;
1326 }
1327 
1328 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1329                                    target_ulong val)
1330 {
1331     return RISCV_EXCP_NONE;
1332 }
1333 
1334 static RISCVException read_hgeip(CPURISCVState *env, int csrno,
1335                                  target_ulong *val)
1336 {
1337     if (val) {
1338         *val = env->hgeip;
1339     }
1340     return RISCV_EXCP_NONE;
1341 }
1342 
1343 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1344                                  target_ulong *val)
1345 {
1346     *val = env->hgatp;
1347     return RISCV_EXCP_NONE;
1348 }
1349 
1350 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1351                                   target_ulong val)
1352 {
1353     env->hgatp = val;
1354     return RISCV_EXCP_NONE;
1355 }
1356 
1357 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1358                                       target_ulong *val)
1359 {
1360     if (!env->rdtime_fn) {
1361         return RISCV_EXCP_ILLEGAL_INST;
1362     }
1363 
1364     *val = env->htimedelta;
1365     return RISCV_EXCP_NONE;
1366 }
1367 
1368 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1369                                        target_ulong val)
1370 {
1371     if (!env->rdtime_fn) {
1372         return RISCV_EXCP_ILLEGAL_INST;
1373     }
1374 
1375     if (riscv_cpu_mxl(env) == MXL_RV32) {
1376         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1377     } else {
1378         env->htimedelta = val;
1379     }
1380     return RISCV_EXCP_NONE;
1381 }
1382 
1383 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1384                                        target_ulong *val)
1385 {
1386     if (!env->rdtime_fn) {
1387         return RISCV_EXCP_ILLEGAL_INST;
1388     }
1389 
1390     *val = env->htimedelta >> 32;
1391     return RISCV_EXCP_NONE;
1392 }
1393 
1394 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1395                                         target_ulong val)
1396 {
1397     if (!env->rdtime_fn) {
1398         return RISCV_EXCP_ILLEGAL_INST;
1399     }
1400 
1401     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1402     return RISCV_EXCP_NONE;
1403 }
1404 
1405 /* Virtual CSR Registers */
1406 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1407                                     target_ulong *val)
1408 {
1409     *val = env->vsstatus;
1410     return RISCV_EXCP_NONE;
1411 }
1412 
1413 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1414                                      target_ulong val)
1415 {
1416     uint64_t mask = (target_ulong)-1;
1417     if ((val & VSSTATUS64_UXL) == 0) {
1418         mask &= ~VSSTATUS64_UXL;
1419     }
1420     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1421     return RISCV_EXCP_NONE;
1422 }
1423 
1424 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1425 {
1426     *val = env->vstvec;
1427     return RISCV_EXCP_NONE;
1428 }
1429 
1430 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1431                                    target_ulong val)
1432 {
1433     env->vstvec = val;
1434     return RISCV_EXCP_NONE;
1435 }
1436 
1437 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1438                                      target_ulong *val)
1439 {
1440     *val = env->vsscratch;
1441     return RISCV_EXCP_NONE;
1442 }
1443 
1444 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1445                                       target_ulong val)
1446 {
1447     env->vsscratch = val;
1448     return RISCV_EXCP_NONE;
1449 }
1450 
1451 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1452                                  target_ulong *val)
1453 {
1454     *val = env->vsepc;
1455     return RISCV_EXCP_NONE;
1456 }
1457 
1458 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1459                                   target_ulong val)
1460 {
1461     env->vsepc = val;
1462     return RISCV_EXCP_NONE;
1463 }
1464 
1465 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1466                                    target_ulong *val)
1467 {
1468     *val = env->vscause;
1469     return RISCV_EXCP_NONE;
1470 }
1471 
1472 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1473                                     target_ulong val)
1474 {
1475     env->vscause = val;
1476     return RISCV_EXCP_NONE;
1477 }
1478 
1479 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1480                                   target_ulong *val)
1481 {
1482     *val = env->vstval;
1483     return RISCV_EXCP_NONE;
1484 }
1485 
1486 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1487                                    target_ulong val)
1488 {
1489     env->vstval = val;
1490     return RISCV_EXCP_NONE;
1491 }
1492 
1493 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1494                                  target_ulong *val)
1495 {
1496     *val = env->vsatp;
1497     return RISCV_EXCP_NONE;
1498 }
1499 
1500 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1501                                   target_ulong val)
1502 {
1503     env->vsatp = val;
1504     return RISCV_EXCP_NONE;
1505 }
1506 
1507 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1508                                   target_ulong *val)
1509 {
1510     *val = env->mtval2;
1511     return RISCV_EXCP_NONE;
1512 }
1513 
1514 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1515                                    target_ulong val)
1516 {
1517     env->mtval2 = val;
1518     return RISCV_EXCP_NONE;
1519 }
1520 
1521 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1522                                   target_ulong *val)
1523 {
1524     *val = env->mtinst;
1525     return RISCV_EXCP_NONE;
1526 }
1527 
1528 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1529                                    target_ulong val)
1530 {
1531     env->mtinst = val;
1532     return RISCV_EXCP_NONE;
1533 }
1534 
1535 /* Physical Memory Protection */
1536 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1537                                    target_ulong *val)
1538 {
1539     *val = mseccfg_csr_read(env);
1540     return RISCV_EXCP_NONE;
1541 }
1542 
1543 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1544                          target_ulong val)
1545 {
1546     mseccfg_csr_write(env, val);
1547     return RISCV_EXCP_NONE;
1548 }
1549 
1550 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
1551 {
1552     /* TODO: RV128 restriction check */
1553     if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
1554         return false;
1555     }
1556     return true;
1557 }
1558 
1559 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1560                                   target_ulong *val)
1561 {
1562     uint32_t reg_index = csrno - CSR_PMPCFG0;
1563 
1564     if (!check_pmp_reg_index(env, reg_index)) {
1565         return RISCV_EXCP_ILLEGAL_INST;
1566     }
1567     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1568     return RISCV_EXCP_NONE;
1569 }
1570 
1571 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1572                                    target_ulong val)
1573 {
1574     uint32_t reg_index = csrno - CSR_PMPCFG0;
1575 
1576     if (!check_pmp_reg_index(env, reg_index)) {
1577         return RISCV_EXCP_ILLEGAL_INST;
1578     }
1579     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1580     return RISCV_EXCP_NONE;
1581 }
1582 
1583 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1584                                    target_ulong *val)
1585 {
1586     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1587     return RISCV_EXCP_NONE;
1588 }
1589 
1590 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1591                                     target_ulong val)
1592 {
1593     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1594     return RISCV_EXCP_NONE;
1595 }
1596 
1597 /*
1598  * Functions to access Pointer Masking feature registers
1599  * We have to check if current priv lvl could modify
1600  * csr in given mode
1601  */
1602 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1603 {
1604     int csr_priv = get_field(csrno, 0x300);
1605     int pm_current;
1606 
1607     if (env->debugger) {
1608         return false;
1609     }
1610     /*
1611      * If priv lvls differ that means we're accessing csr from higher priv lvl,
1612      * so allow the access
1613      */
1614     if (env->priv != csr_priv) {
1615         return false;
1616     }
1617     switch (env->priv) {
1618     case PRV_M:
1619         pm_current = get_field(env->mmte, M_PM_CURRENT);
1620         break;
1621     case PRV_S:
1622         pm_current = get_field(env->mmte, S_PM_CURRENT);
1623         break;
1624     case PRV_U:
1625         pm_current = get_field(env->mmte, U_PM_CURRENT);
1626         break;
1627     default:
1628         g_assert_not_reached();
1629     }
1630     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
1631     return !pm_current;
1632 }
1633 
1634 static RISCVException read_mmte(CPURISCVState *env, int csrno,
1635                                 target_ulong *val)
1636 {
1637     *val = env->mmte & MMTE_MASK;
1638     return RISCV_EXCP_NONE;
1639 }
1640 
1641 static RISCVException write_mmte(CPURISCVState *env, int csrno,
1642                                  target_ulong val)
1643 {
1644     uint64_t mstatus;
1645     target_ulong wpri_val = val & MMTE_MASK;
1646 
1647     if (val != wpri_val) {
1648         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1649                       "MMTE: WPRI violation written 0x", val,
1650                       "vs expected 0x", wpri_val);
1651     }
1652     /* for machine mode pm.current is hardwired to 1 */
1653     wpri_val |= MMTE_M_PM_CURRENT;
1654 
1655     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
1656     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1657     env->mmte = wpri_val | PM_EXT_DIRTY;
1658     riscv_cpu_update_mask(env);
1659 
1660     /* Set XS and SD bits, since PM CSRs are dirty */
1661     mstatus = env->mstatus | MSTATUS_XS;
1662     write_mstatus(env, csrno, mstatus);
1663     return RISCV_EXCP_NONE;
1664 }
1665 
1666 static RISCVException read_smte(CPURISCVState *env, int csrno,
1667                                 target_ulong *val)
1668 {
1669     *val = env->mmte & SMTE_MASK;
1670     return RISCV_EXCP_NONE;
1671 }
1672 
1673 static RISCVException write_smte(CPURISCVState *env, int csrno,
1674                                  target_ulong val)
1675 {
1676     target_ulong wpri_val = val & SMTE_MASK;
1677 
1678     if (val != wpri_val) {
1679         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1680                       "SMTE: WPRI violation written 0x", val,
1681                       "vs expected 0x", wpri_val);
1682     }
1683 
1684     /* if pm.current==0 we can't modify current PM CSRs */
1685     if (check_pm_current_disabled(env, csrno)) {
1686         return RISCV_EXCP_NONE;
1687     }
1688 
1689     wpri_val |= (env->mmte & ~SMTE_MASK);
1690     write_mmte(env, csrno, wpri_val);
1691     return RISCV_EXCP_NONE;
1692 }
1693 
1694 static RISCVException read_umte(CPURISCVState *env, int csrno,
1695                                 target_ulong *val)
1696 {
1697     *val = env->mmte & UMTE_MASK;
1698     return RISCV_EXCP_NONE;
1699 }
1700 
1701 static RISCVException write_umte(CPURISCVState *env, int csrno,
1702                                  target_ulong val)
1703 {
1704     target_ulong wpri_val = val & UMTE_MASK;
1705 
1706     if (val != wpri_val) {
1707         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1708                       "UMTE: WPRI violation written 0x", val,
1709                       "vs expected 0x", wpri_val);
1710     }
1711 
1712     if (check_pm_current_disabled(env, csrno)) {
1713         return RISCV_EXCP_NONE;
1714     }
1715 
1716     wpri_val |= (env->mmte & ~UMTE_MASK);
1717     write_mmte(env, csrno, wpri_val);
1718     return RISCV_EXCP_NONE;
1719 }
1720 
1721 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1722                                    target_ulong *val)
1723 {
1724     *val = env->mpmmask;
1725     return RISCV_EXCP_NONE;
1726 }
1727 
1728 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1729                                     target_ulong val)
1730 {
1731     uint64_t mstatus;
1732 
1733     env->mpmmask = val;
1734     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1735         env->cur_pmmask = val;
1736     }
1737     env->mmte |= PM_EXT_DIRTY;
1738 
1739     /* Set XS and SD bits, since PM CSRs are dirty */
1740     mstatus = env->mstatus | MSTATUS_XS;
1741     write_mstatus(env, csrno, mstatus);
1742     return RISCV_EXCP_NONE;
1743 }
1744 
1745 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1746                                    target_ulong *val)
1747 {
1748     *val = env->spmmask;
1749     return RISCV_EXCP_NONE;
1750 }
1751 
1752 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1753                                     target_ulong val)
1754 {
1755     uint64_t mstatus;
1756 
1757     /* if pm.current==0 we can't modify current PM CSRs */
1758     if (check_pm_current_disabled(env, csrno)) {
1759         return RISCV_EXCP_NONE;
1760     }
1761     env->spmmask = val;
1762     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1763         env->cur_pmmask = val;
1764     }
1765     env->mmte |= PM_EXT_DIRTY;
1766 
1767     /* Set XS and SD bits, since PM CSRs are dirty */
1768     mstatus = env->mstatus | MSTATUS_XS;
1769     write_mstatus(env, csrno, mstatus);
1770     return RISCV_EXCP_NONE;
1771 }
1772 
1773 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1774                                    target_ulong *val)
1775 {
1776     *val = env->upmmask;
1777     return RISCV_EXCP_NONE;
1778 }
1779 
1780 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1781                                     target_ulong val)
1782 {
1783     uint64_t mstatus;
1784 
1785     /* if pm.current==0 we can't modify current PM CSRs */
1786     if (check_pm_current_disabled(env, csrno)) {
1787         return RISCV_EXCP_NONE;
1788     }
1789     env->upmmask = val;
1790     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1791         env->cur_pmmask = val;
1792     }
1793     env->mmte |= PM_EXT_DIRTY;
1794 
1795     /* Set XS and SD bits, since PM CSRs are dirty */
1796     mstatus = env->mstatus | MSTATUS_XS;
1797     write_mstatus(env, csrno, mstatus);
1798     return RISCV_EXCP_NONE;
1799 }
1800 
1801 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1802                                    target_ulong *val)
1803 {
1804     *val = env->mpmbase;
1805     return RISCV_EXCP_NONE;
1806 }
1807 
1808 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1809                                     target_ulong val)
1810 {
1811     uint64_t mstatus;
1812 
1813     env->mpmbase = val;
1814     if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) {
1815         env->cur_pmbase = val;
1816     }
1817     env->mmte |= PM_EXT_DIRTY;
1818 
1819     /* Set XS and SD bits, since PM CSRs are dirty */
1820     mstatus = env->mstatus | MSTATUS_XS;
1821     write_mstatus(env, csrno, mstatus);
1822     return RISCV_EXCP_NONE;
1823 }
1824 
1825 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1826                                    target_ulong *val)
1827 {
1828     *val = env->spmbase;
1829     return RISCV_EXCP_NONE;
1830 }
1831 
1832 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1833                                     target_ulong val)
1834 {
1835     uint64_t mstatus;
1836 
1837     /* if pm.current==0 we can't modify current PM CSRs */
1838     if (check_pm_current_disabled(env, csrno)) {
1839         return RISCV_EXCP_NONE;
1840     }
1841     env->spmbase = val;
1842     if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) {
1843         env->cur_pmbase = val;
1844     }
1845     env->mmte |= PM_EXT_DIRTY;
1846 
1847     /* Set XS and SD bits, since PM CSRs are dirty */
1848     mstatus = env->mstatus | MSTATUS_XS;
1849     write_mstatus(env, csrno, mstatus);
1850     return RISCV_EXCP_NONE;
1851 }
1852 
1853 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1854                                    target_ulong *val)
1855 {
1856     *val = env->upmbase;
1857     return RISCV_EXCP_NONE;
1858 }
1859 
1860 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1861                                     target_ulong val)
1862 {
1863     uint64_t mstatus;
1864 
1865     /* if pm.current==0 we can't modify current PM CSRs */
1866     if (check_pm_current_disabled(env, csrno)) {
1867         return RISCV_EXCP_NONE;
1868     }
1869     env->upmbase = val;
1870     if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) {
1871         env->cur_pmbase = val;
1872     }
1873     env->mmte |= PM_EXT_DIRTY;
1874 
1875     /* Set XS and SD bits, since PM CSRs are dirty */
1876     mstatus = env->mstatus | MSTATUS_XS;
1877     write_mstatus(env, csrno, mstatus);
1878     return RISCV_EXCP_NONE;
1879 }
1880 
1881 #endif
1882 
1883 /*
1884  * riscv_csrrw - read and/or update control and status register
1885  *
1886  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1887  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1888  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1889  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1890  */
1891 
1892 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
1893                                                int csrno,
1894                                                bool write_mask,
1895                                                RISCVCPU *cpu)
1896 {
1897     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
1898     int read_only = get_field(csrno, 0xC00) == 3;
1899 #if !defined(CONFIG_USER_ONLY)
1900     int effective_priv = env->priv;
1901 
1902     if (riscv_has_ext(env, RVH) &&
1903         env->priv == PRV_S &&
1904         !riscv_cpu_virt_enabled(env)) {
1905         /*
1906          * We are in S mode without virtualisation, therefore we are in HS Mode.
1907          * Add 1 to the effective privledge level to allow us to access the
1908          * Hypervisor CSRs.
1909          */
1910         effective_priv++;
1911     }
1912 
1913     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1914         return RISCV_EXCP_ILLEGAL_INST;
1915     }
1916 #endif
1917     if (write_mask && read_only) {
1918         return RISCV_EXCP_ILLEGAL_INST;
1919     }
1920 
1921     /* ensure the CSR extension is enabled. */
1922     if (!cpu->cfg.ext_icsr) {
1923         return RISCV_EXCP_ILLEGAL_INST;
1924     }
1925 
1926     /* check predicate */
1927     if (!csr_ops[csrno].predicate) {
1928         return RISCV_EXCP_ILLEGAL_INST;
1929     }
1930 
1931     return csr_ops[csrno].predicate(env, csrno);
1932 }
1933 
1934 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
1935                                        target_ulong *ret_value,
1936                                        target_ulong new_value,
1937                                        target_ulong write_mask)
1938 {
1939     RISCVException ret;
1940     target_ulong old_value;
1941 
1942     /* execute combined read/write operation if it exists */
1943     if (csr_ops[csrno].op) {
1944         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1945     }
1946 
1947     /* if no accessor exists then return failure */
1948     if (!csr_ops[csrno].read) {
1949         return RISCV_EXCP_ILLEGAL_INST;
1950     }
1951     /* read old value */
1952     ret = csr_ops[csrno].read(env, csrno, &old_value);
1953     if (ret != RISCV_EXCP_NONE) {
1954         return ret;
1955     }
1956 
1957     /* write value if writable and write mask set, otherwise drop writes */
1958     if (write_mask) {
1959         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1960         if (csr_ops[csrno].write) {
1961             ret = csr_ops[csrno].write(env, csrno, new_value);
1962             if (ret != RISCV_EXCP_NONE) {
1963                 return ret;
1964             }
1965         }
1966     }
1967 
1968     /* return old value */
1969     if (ret_value) {
1970         *ret_value = old_value;
1971     }
1972 
1973     return RISCV_EXCP_NONE;
1974 }
1975 
1976 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1977                            target_ulong *ret_value,
1978                            target_ulong new_value, target_ulong write_mask)
1979 {
1980     RISCVCPU *cpu = env_archcpu(env);
1981 
1982     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
1983     if (ret != RISCV_EXCP_NONE) {
1984         return ret;
1985     }
1986 
1987     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
1988 }
1989 
1990 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
1991                                         Int128 *ret_value,
1992                                         Int128 new_value,
1993                                         Int128 write_mask)
1994 {
1995     RISCVException ret;
1996     Int128 old_value;
1997 
1998     /* read old value */
1999     ret = csr_ops[csrno].read128(env, csrno, &old_value);
2000     if (ret != RISCV_EXCP_NONE) {
2001         return ret;
2002     }
2003 
2004     /* write value if writable and write mask set, otherwise drop writes */
2005     if (int128_nz(write_mask)) {
2006         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
2007                               int128_and(new_value, write_mask));
2008         if (csr_ops[csrno].write128) {
2009             ret = csr_ops[csrno].write128(env, csrno, new_value);
2010             if (ret != RISCV_EXCP_NONE) {
2011                 return ret;
2012             }
2013         } else if (csr_ops[csrno].write) {
2014             /* avoids having to write wrappers for all registers */
2015             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
2016             if (ret != RISCV_EXCP_NONE) {
2017                 return ret;
2018             }
2019         }
2020     }
2021 
2022     /* return old value */
2023     if (ret_value) {
2024         *ret_value = old_value;
2025     }
2026 
2027     return RISCV_EXCP_NONE;
2028 }
2029 
2030 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
2031                                 Int128 *ret_value,
2032                                 Int128 new_value, Int128 write_mask)
2033 {
2034     RISCVException ret;
2035     RISCVCPU *cpu = env_archcpu(env);
2036 
2037     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
2038     if (ret != RISCV_EXCP_NONE) {
2039         return ret;
2040     }
2041 
2042     if (csr_ops[csrno].read128) {
2043         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
2044     }
2045 
2046     /*
2047      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
2048      * at all defined.
2049      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
2050      * significant), for those, this fallback is correctly handling the accesses
2051      */
2052     target_ulong old_value;
2053     ret = riscv_csrrw_do64(env, csrno, &old_value,
2054                            int128_getlo(new_value),
2055                            int128_getlo(write_mask));
2056     if (ret == RISCV_EXCP_NONE && ret_value) {
2057         *ret_value = int128_make64(old_value);
2058     }
2059     return ret;
2060 }
2061 
2062 /*
2063  * Debugger support.  If not in user mode, set env->debugger before the
2064  * riscv_csrrw call and clear it after the call.
2065  */
2066 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
2067                                  target_ulong *ret_value,
2068                                  target_ulong new_value,
2069                                  target_ulong write_mask)
2070 {
2071     RISCVException ret;
2072 #if !defined(CONFIG_USER_ONLY)
2073     env->debugger = true;
2074 #endif
2075     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
2076 #if !defined(CONFIG_USER_ONLY)
2077     env->debugger = false;
2078 #endif
2079     return ret;
2080 }
2081 
2082 /* Control and Status Register function table */
2083 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
2084     /* User Floating-Point CSRs */
2085     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
2086     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
2087     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
2088     /* Vector CSRs */
2089     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
2090     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
2091     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
2092     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
2093     [CSR_VL]       = { "vl",       vs,     read_vl                    },
2094     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2095     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2096     /* User Timers and Counters */
2097     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2098     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2099     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2100     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2101 
2102     /*
2103      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2104      * rdtime callback is not provided by machine/platform emulation.
2105      */
2106     [CSR_TIME]  = { "time",  ctr,   read_time  },
2107     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2108 
2109 #if !defined(CONFIG_USER_ONLY)
2110     /* Machine Timers and Counters */
2111     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2112     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2113     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2114     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2115 
2116     /* Machine Information Registers */
2117     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2118     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2119     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2120     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2121 
2122     /* Machine Trap Setup */
2123     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2124                                                read_mstatus_i128                   },
2125     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2126                                                read_misa_i128                      },
2127     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
2128     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2129     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
2130     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2131     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2132 
2133     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2134 
2135     /* Machine Trap Handling */
2136     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2137                                          read_mscratch_i128, write_mscratch_i128   },
2138     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2139     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2140     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2141     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2142 
2143     /* Supervisor Trap Setup */
2144     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2145                                               read_sstatus_i128                 },
2146     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
2147     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2148     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2149 
2150     /* Supervisor Trap Handling */
2151     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2152                                           read_sscratch_i128, write_sscratch_i128  },
2153     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2154     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2155     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2156     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2157 
2158     /* Supervisor Protection and Translation */
2159     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2160 
2161     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2162     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2163     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
2164     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2165     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2166     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
2167     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2168     [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
2169     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2170     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2171     [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       NULL              },
2172     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2173     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2174     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2175 
2176     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2177     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2178     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
2179     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2180     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2181     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2182     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2183     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2184     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2185 
2186     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2187     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2188 
2189     /* Physical Memory Protection */
2190     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2191     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2192     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2193     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2194     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2195     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2196     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2197     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2198     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2199     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2200     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2201     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2202     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2203     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2204     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2205     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2206     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2207     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2208     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2209     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2210     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2211 
2212     /* User Pointer Masking */
2213     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2214     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2215     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2216     /* Machine Pointer Masking */
2217     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2218     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2219     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2220     /* Supervisor Pointer Masking */
2221     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2222     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2223     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2224 
2225     /* Performance Counters */
2226     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2227     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2228     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2229     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2230     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2231     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2232     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2233     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2234     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2235     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2236     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2237     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2238     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2239     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2240     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2241     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2242     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2243     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2244     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2245     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2246     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2247     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2248     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2249     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2250     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2251     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2252     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2253     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2254     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2255 
2256     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2257     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2258     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2259     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2260     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2261     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2262     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2263     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2264     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2265     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2266     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2267     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2268     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2269     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2270     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2271     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2272     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2273     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2274     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2275     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2276     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2277     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2278     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2279     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2280     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2281     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2282     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2283     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2284     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2285 
2286     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2287     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2288     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2289     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2290     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2291     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2292     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2293     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2294     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2295     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2296     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2297     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2298     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2299     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2300     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2301     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2302     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2303     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2304     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2305     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2306     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2307     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2308     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2309     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2310     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2311     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2312     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2313     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2314     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2315 
2316     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2317     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2318     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2319     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2320     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2321     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2322     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2323     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2324     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2325     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2326     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2327     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2328     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2329     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2330     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2331     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2332     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2333     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2334     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2335     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2336     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2337     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2338     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2339     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2340     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2341     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2342     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2343     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2344     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2345 
2346     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2347     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2348     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2349     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2350     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2351     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2352     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2353     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2354     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2355     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2356     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2357     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2358     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2359     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2360     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2361     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2362     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2363     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2364     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2365     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2366     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2367     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2368     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2369     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2370     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2371     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2372     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2373     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2374     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2375 #endif /* !CONFIG_USER_ONLY */
2376 };
2377