1 /* 2 * RISC-V Control and Status Registers. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/timer.h" 23 #include "cpu.h" 24 #include "qemu/main-loop.h" 25 #include "exec/exec-all.h" 26 #include "sysemu/cpu-timers.h" 27 28 /* CSR function table public API */ 29 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) 30 { 31 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; 32 } 33 34 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) 35 { 36 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; 37 } 38 39 /* Predicates */ 40 static RISCVException fs(CPURISCVState *env, int csrno) 41 { 42 #if !defined(CONFIG_USER_ONLY) 43 if (!env->debugger && !riscv_cpu_fp_enabled(env) && 44 !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { 45 return RISCV_EXCP_ILLEGAL_INST; 46 } 47 #endif 48 return RISCV_EXCP_NONE; 49 } 50 51 static RISCVException vs(CPURISCVState *env, int csrno) 52 { 53 CPUState *cs = env_cpu(env); 54 RISCVCPU *cpu = RISCV_CPU(cs); 55 56 if (env->misa_ext & RVV || 57 cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { 58 #if !defined(CONFIG_USER_ONLY) 59 if (!env->debugger && !riscv_cpu_vector_enabled(env)) { 60 return RISCV_EXCP_ILLEGAL_INST; 61 } 62 #endif 63 return RISCV_EXCP_NONE; 64 } 65 return RISCV_EXCP_ILLEGAL_INST; 66 } 67 68 static RISCVException ctr(CPURISCVState *env, int csrno) 69 { 70 #if !defined(CONFIG_USER_ONLY) 71 CPUState *cs = env_cpu(env); 72 RISCVCPU *cpu = RISCV_CPU(cs); 73 74 if (!cpu->cfg.ext_counters) { 75 /* The Counters extensions is not enabled */ 76 return RISCV_EXCP_ILLEGAL_INST; 77 } 78 79 if (riscv_cpu_virt_enabled(env)) { 80 switch (csrno) { 81 case CSR_CYCLE: 82 if (!get_field(env->hcounteren, COUNTEREN_CY) && 83 get_field(env->mcounteren, COUNTEREN_CY)) { 84 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 85 } 86 break; 87 case CSR_TIME: 88 if (!get_field(env->hcounteren, COUNTEREN_TM) && 89 get_field(env->mcounteren, COUNTEREN_TM)) { 90 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 91 } 92 break; 93 case CSR_INSTRET: 94 if (!get_field(env->hcounteren, COUNTEREN_IR) && 95 get_field(env->mcounteren, COUNTEREN_IR)) { 96 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 97 } 98 break; 99 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: 100 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) && 101 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) { 102 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 103 } 104 break; 105 } 106 if (riscv_cpu_mxl(env) == MXL_RV32) { 107 switch (csrno) { 108 case CSR_CYCLEH: 109 if (!get_field(env->hcounteren, COUNTEREN_CY) && 110 get_field(env->mcounteren, COUNTEREN_CY)) { 111 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 112 } 113 break; 114 case CSR_TIMEH: 115 if (!get_field(env->hcounteren, COUNTEREN_TM) && 116 get_field(env->mcounteren, COUNTEREN_TM)) { 117 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 118 } 119 break; 120 case CSR_INSTRETH: 121 if (!get_field(env->hcounteren, COUNTEREN_IR) && 122 get_field(env->mcounteren, COUNTEREN_IR)) { 123 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 124 } 125 break; 126 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: 127 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) && 128 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) { 129 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 130 } 131 break; 132 } 133 } 134 } 135 #endif 136 return RISCV_EXCP_NONE; 137 } 138 139 static RISCVException ctr32(CPURISCVState *env, int csrno) 140 { 141 if (riscv_cpu_mxl(env) != MXL_RV32) { 142 return RISCV_EXCP_ILLEGAL_INST; 143 } 144 145 return ctr(env, csrno); 146 } 147 148 #if !defined(CONFIG_USER_ONLY) 149 static RISCVException any(CPURISCVState *env, int csrno) 150 { 151 return RISCV_EXCP_NONE; 152 } 153 154 static RISCVException any32(CPURISCVState *env, int csrno) 155 { 156 if (riscv_cpu_mxl(env) != MXL_RV32) { 157 return RISCV_EXCP_ILLEGAL_INST; 158 } 159 160 return any(env, csrno); 161 162 } 163 164 static int aia_any(CPURISCVState *env, int csrno) 165 { 166 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 167 return RISCV_EXCP_ILLEGAL_INST; 168 } 169 170 return any(env, csrno); 171 } 172 173 static int aia_any32(CPURISCVState *env, int csrno) 174 { 175 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 176 return RISCV_EXCP_ILLEGAL_INST; 177 } 178 179 return any32(env, csrno); 180 } 181 182 static RISCVException smode(CPURISCVState *env, int csrno) 183 { 184 if (riscv_has_ext(env, RVS)) { 185 return RISCV_EXCP_NONE; 186 } 187 188 return RISCV_EXCP_ILLEGAL_INST; 189 } 190 191 static int smode32(CPURISCVState *env, int csrno) 192 { 193 if (riscv_cpu_mxl(env) != MXL_RV32) { 194 return RISCV_EXCP_ILLEGAL_INST; 195 } 196 197 return smode(env, csrno); 198 } 199 200 static int aia_smode(CPURISCVState *env, int csrno) 201 { 202 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 203 return RISCV_EXCP_ILLEGAL_INST; 204 } 205 206 return smode(env, csrno); 207 } 208 209 static int aia_smode32(CPURISCVState *env, int csrno) 210 { 211 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 212 return RISCV_EXCP_ILLEGAL_INST; 213 } 214 215 return smode32(env, csrno); 216 } 217 218 static RISCVException hmode(CPURISCVState *env, int csrno) 219 { 220 if (riscv_has_ext(env, RVS) && 221 riscv_has_ext(env, RVH)) { 222 /* Hypervisor extension is supported */ 223 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || 224 env->priv == PRV_M) { 225 return RISCV_EXCP_NONE; 226 } else { 227 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 228 } 229 } 230 231 return RISCV_EXCP_ILLEGAL_INST; 232 } 233 234 static RISCVException hmode32(CPURISCVState *env, int csrno) 235 { 236 if (riscv_cpu_mxl(env) != MXL_RV32) { 237 if (!riscv_cpu_virt_enabled(env)) { 238 return RISCV_EXCP_ILLEGAL_INST; 239 } else { 240 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 241 } 242 } 243 244 return hmode(env, csrno); 245 246 } 247 248 /* Checks if PointerMasking registers could be accessed */ 249 static RISCVException pointer_masking(CPURISCVState *env, int csrno) 250 { 251 /* Check if j-ext is present */ 252 if (riscv_has_ext(env, RVJ)) { 253 return RISCV_EXCP_NONE; 254 } 255 return RISCV_EXCP_ILLEGAL_INST; 256 } 257 258 static int aia_hmode(CPURISCVState *env, int csrno) 259 { 260 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 261 return RISCV_EXCP_ILLEGAL_INST; 262 } 263 264 return hmode(env, csrno); 265 } 266 267 static int aia_hmode32(CPURISCVState *env, int csrno) 268 { 269 if (!riscv_feature(env, RISCV_FEATURE_AIA)) { 270 return RISCV_EXCP_ILLEGAL_INST; 271 } 272 273 return hmode32(env, csrno); 274 } 275 276 static RISCVException pmp(CPURISCVState *env, int csrno) 277 { 278 if (riscv_feature(env, RISCV_FEATURE_PMP)) { 279 return RISCV_EXCP_NONE; 280 } 281 282 return RISCV_EXCP_ILLEGAL_INST; 283 } 284 285 static RISCVException epmp(CPURISCVState *env, int csrno) 286 { 287 if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { 288 return RISCV_EXCP_NONE; 289 } 290 291 return RISCV_EXCP_ILLEGAL_INST; 292 } 293 294 static RISCVException debug(CPURISCVState *env, int csrno) 295 { 296 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 297 return RISCV_EXCP_NONE; 298 } 299 300 return RISCV_EXCP_ILLEGAL_INST; 301 } 302 #endif 303 304 /* User Floating-Point CSRs */ 305 static RISCVException read_fflags(CPURISCVState *env, int csrno, 306 target_ulong *val) 307 { 308 *val = riscv_cpu_get_fflags(env); 309 return RISCV_EXCP_NONE; 310 } 311 312 static RISCVException write_fflags(CPURISCVState *env, int csrno, 313 target_ulong val) 314 { 315 #if !defined(CONFIG_USER_ONLY) 316 if (riscv_has_ext(env, RVF)) { 317 env->mstatus |= MSTATUS_FS; 318 } 319 #endif 320 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); 321 return RISCV_EXCP_NONE; 322 } 323 324 static RISCVException read_frm(CPURISCVState *env, int csrno, 325 target_ulong *val) 326 { 327 *val = env->frm; 328 return RISCV_EXCP_NONE; 329 } 330 331 static RISCVException write_frm(CPURISCVState *env, int csrno, 332 target_ulong val) 333 { 334 #if !defined(CONFIG_USER_ONLY) 335 if (riscv_has_ext(env, RVF)) { 336 env->mstatus |= MSTATUS_FS; 337 } 338 #endif 339 env->frm = val & (FSR_RD >> FSR_RD_SHIFT); 340 return RISCV_EXCP_NONE; 341 } 342 343 static RISCVException read_fcsr(CPURISCVState *env, int csrno, 344 target_ulong *val) 345 { 346 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) 347 | (env->frm << FSR_RD_SHIFT); 348 return RISCV_EXCP_NONE; 349 } 350 351 static RISCVException write_fcsr(CPURISCVState *env, int csrno, 352 target_ulong val) 353 { 354 #if !defined(CONFIG_USER_ONLY) 355 if (riscv_has_ext(env, RVF)) { 356 env->mstatus |= MSTATUS_FS; 357 } 358 #endif 359 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; 360 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); 361 return RISCV_EXCP_NONE; 362 } 363 364 static RISCVException read_vtype(CPURISCVState *env, int csrno, 365 target_ulong *val) 366 { 367 uint64_t vill; 368 switch (env->xl) { 369 case MXL_RV32: 370 vill = (uint32_t)env->vill << 31; 371 break; 372 case MXL_RV64: 373 vill = (uint64_t)env->vill << 63; 374 break; 375 default: 376 g_assert_not_reached(); 377 } 378 *val = (target_ulong)vill | env->vtype; 379 return RISCV_EXCP_NONE; 380 } 381 382 static RISCVException read_vl(CPURISCVState *env, int csrno, 383 target_ulong *val) 384 { 385 *val = env->vl; 386 return RISCV_EXCP_NONE; 387 } 388 389 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) 390 { 391 *val = env_archcpu(env)->cfg.vlen >> 3; 392 return RISCV_EXCP_NONE; 393 } 394 395 static RISCVException read_vxrm(CPURISCVState *env, int csrno, 396 target_ulong *val) 397 { 398 *val = env->vxrm; 399 return RISCV_EXCP_NONE; 400 } 401 402 static RISCVException write_vxrm(CPURISCVState *env, int csrno, 403 target_ulong val) 404 { 405 #if !defined(CONFIG_USER_ONLY) 406 env->mstatus |= MSTATUS_VS; 407 #endif 408 env->vxrm = val; 409 return RISCV_EXCP_NONE; 410 } 411 412 static RISCVException read_vxsat(CPURISCVState *env, int csrno, 413 target_ulong *val) 414 { 415 *val = env->vxsat; 416 return RISCV_EXCP_NONE; 417 } 418 419 static RISCVException write_vxsat(CPURISCVState *env, int csrno, 420 target_ulong val) 421 { 422 #if !defined(CONFIG_USER_ONLY) 423 env->mstatus |= MSTATUS_VS; 424 #endif 425 env->vxsat = val; 426 return RISCV_EXCP_NONE; 427 } 428 429 static RISCVException read_vstart(CPURISCVState *env, int csrno, 430 target_ulong *val) 431 { 432 *val = env->vstart; 433 return RISCV_EXCP_NONE; 434 } 435 436 static RISCVException write_vstart(CPURISCVState *env, int csrno, 437 target_ulong val) 438 { 439 #if !defined(CONFIG_USER_ONLY) 440 env->mstatus |= MSTATUS_VS; 441 #endif 442 /* 443 * The vstart CSR is defined to have only enough writable bits 444 * to hold the largest element index, i.e. lg2(VLEN) bits. 445 */ 446 env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); 447 return RISCV_EXCP_NONE; 448 } 449 450 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) 451 { 452 *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); 453 return RISCV_EXCP_NONE; 454 } 455 456 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) 457 { 458 #if !defined(CONFIG_USER_ONLY) 459 env->mstatus |= MSTATUS_VS; 460 #endif 461 env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; 462 env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; 463 return RISCV_EXCP_NONE; 464 } 465 466 /* User Timers and Counters */ 467 static RISCVException read_instret(CPURISCVState *env, int csrno, 468 target_ulong *val) 469 { 470 #if !defined(CONFIG_USER_ONLY) 471 if (icount_enabled()) { 472 *val = icount_get(); 473 } else { 474 *val = cpu_get_host_ticks(); 475 } 476 #else 477 *val = cpu_get_host_ticks(); 478 #endif 479 return RISCV_EXCP_NONE; 480 } 481 482 static RISCVException read_instreth(CPURISCVState *env, int csrno, 483 target_ulong *val) 484 { 485 #if !defined(CONFIG_USER_ONLY) 486 if (icount_enabled()) { 487 *val = icount_get() >> 32; 488 } else { 489 *val = cpu_get_host_ticks() >> 32; 490 } 491 #else 492 *val = cpu_get_host_ticks() >> 32; 493 #endif 494 return RISCV_EXCP_NONE; 495 } 496 497 #if defined(CONFIG_USER_ONLY) 498 static RISCVException read_time(CPURISCVState *env, int csrno, 499 target_ulong *val) 500 { 501 *val = cpu_get_host_ticks(); 502 return RISCV_EXCP_NONE; 503 } 504 505 static RISCVException read_timeh(CPURISCVState *env, int csrno, 506 target_ulong *val) 507 { 508 *val = cpu_get_host_ticks() >> 32; 509 return RISCV_EXCP_NONE; 510 } 511 512 #else /* CONFIG_USER_ONLY */ 513 514 static RISCVException read_time(CPURISCVState *env, int csrno, 515 target_ulong *val) 516 { 517 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 518 519 if (!env->rdtime_fn) { 520 return RISCV_EXCP_ILLEGAL_INST; 521 } 522 523 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta; 524 return RISCV_EXCP_NONE; 525 } 526 527 static RISCVException read_timeh(CPURISCVState *env, int csrno, 528 target_ulong *val) 529 { 530 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; 531 532 if (!env->rdtime_fn) { 533 return RISCV_EXCP_ILLEGAL_INST; 534 } 535 536 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; 537 return RISCV_EXCP_NONE; 538 } 539 540 /* Machine constants */ 541 542 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) 543 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) 544 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) 545 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) 546 547 #define VSTOPI_NUM_SRCS 5 548 549 static const uint64_t delegable_ints = S_MODE_INTERRUPTS | 550 VS_MODE_INTERRUPTS; 551 static const uint64_t vs_delegable_ints = VS_MODE_INTERRUPTS; 552 static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | 553 HS_MODE_INTERRUPTS; 554 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ 555 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ 556 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ 557 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ 558 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ 559 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ 560 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ 561 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ 562 (1ULL << (RISCV_EXCP_U_ECALL)) | \ 563 (1ULL << (RISCV_EXCP_S_ECALL)) | \ 564 (1ULL << (RISCV_EXCP_VS_ECALL)) | \ 565 (1ULL << (RISCV_EXCP_M_ECALL)) | \ 566 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ 567 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ 568 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ 569 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ 570 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ 571 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ 572 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) 573 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & 574 ~((1ULL << (RISCV_EXCP_S_ECALL)) | 575 (1ULL << (RISCV_EXCP_VS_ECALL)) | 576 (1ULL << (RISCV_EXCP_M_ECALL)) | 577 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | 578 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | 579 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | 580 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); 581 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | 582 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | 583 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; 584 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; 585 static const target_ulong hip_writable_mask = MIP_VSSIP; 586 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; 587 static const target_ulong vsip_writable_mask = MIP_VSSIP; 588 589 static const char valid_vm_1_10_32[16] = { 590 [VM_1_10_MBARE] = 1, 591 [VM_1_10_SV32] = 1 592 }; 593 594 static const char valid_vm_1_10_64[16] = { 595 [VM_1_10_MBARE] = 1, 596 [VM_1_10_SV39] = 1, 597 [VM_1_10_SV48] = 1, 598 [VM_1_10_SV57] = 1 599 }; 600 601 /* Machine Information Registers */ 602 static RISCVException read_zero(CPURISCVState *env, int csrno, 603 target_ulong *val) 604 { 605 *val = 0; 606 return RISCV_EXCP_NONE; 607 } 608 609 static RISCVException write_ignore(CPURISCVState *env, int csrno, 610 target_ulong val) 611 { 612 return RISCV_EXCP_NONE; 613 } 614 615 static RISCVException read_mhartid(CPURISCVState *env, int csrno, 616 target_ulong *val) 617 { 618 *val = env->mhartid; 619 return RISCV_EXCP_NONE; 620 } 621 622 /* Machine Trap Setup */ 623 624 /* We do not store SD explicitly, only compute it on demand. */ 625 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) 626 { 627 if ((status & MSTATUS_FS) == MSTATUS_FS || 628 (status & MSTATUS_VS) == MSTATUS_VS || 629 (status & MSTATUS_XS) == MSTATUS_XS) { 630 switch (xl) { 631 case MXL_RV32: 632 return status | MSTATUS32_SD; 633 case MXL_RV64: 634 return status | MSTATUS64_SD; 635 case MXL_RV128: 636 return MSTATUSH128_SD; 637 default: 638 g_assert_not_reached(); 639 } 640 } 641 return status; 642 } 643 644 static RISCVException read_mstatus(CPURISCVState *env, int csrno, 645 target_ulong *val) 646 { 647 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus); 648 return RISCV_EXCP_NONE; 649 } 650 651 static int validate_vm(CPURISCVState *env, target_ulong vm) 652 { 653 if (riscv_cpu_mxl(env) == MXL_RV32) { 654 return valid_vm_1_10_32[vm & 0xf]; 655 } else { 656 return valid_vm_1_10_64[vm & 0xf]; 657 } 658 } 659 660 static RISCVException write_mstatus(CPURISCVState *env, int csrno, 661 target_ulong val) 662 { 663 uint64_t mstatus = env->mstatus; 664 uint64_t mask = 0; 665 RISCVMXL xl = riscv_cpu_mxl(env); 666 667 /* flush tlb on mstatus fields that affect VM */ 668 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | 669 MSTATUS_MPRV | MSTATUS_SUM)) { 670 tlb_flush(env_cpu(env)); 671 } 672 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | 673 MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | 674 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | 675 MSTATUS_TW | MSTATUS_VS; 676 677 if (riscv_has_ext(env, RVF)) { 678 mask |= MSTATUS_FS; 679 } 680 681 if (xl != MXL_RV32 || env->debugger) { 682 /* 683 * RV32: MPV and GVA are not in mstatus. The current plan is to 684 * add them to mstatush. For now, we just don't support it. 685 */ 686 mask |= MSTATUS_MPV | MSTATUS_GVA; 687 if ((val & MSTATUS64_UXL) != 0) { 688 mask |= MSTATUS64_UXL; 689 } 690 } 691 692 mstatus = (mstatus & ~mask) | (val & mask); 693 694 if (xl > MXL_RV32) { 695 /* SXL field is for now read only */ 696 mstatus = set_field(mstatus, MSTATUS64_SXL, xl); 697 } 698 env->mstatus = mstatus; 699 env->xl = cpu_recompute_xl(env); 700 701 return RISCV_EXCP_NONE; 702 } 703 704 static RISCVException read_mstatush(CPURISCVState *env, int csrno, 705 target_ulong *val) 706 { 707 *val = env->mstatus >> 32; 708 return RISCV_EXCP_NONE; 709 } 710 711 static RISCVException write_mstatush(CPURISCVState *env, int csrno, 712 target_ulong val) 713 { 714 uint64_t valh = (uint64_t)val << 32; 715 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; 716 717 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { 718 tlb_flush(env_cpu(env)); 719 } 720 721 env->mstatus = (env->mstatus & ~mask) | (valh & mask); 722 723 return RISCV_EXCP_NONE; 724 } 725 726 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, 727 Int128 *val) 728 { 729 *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus)); 730 return RISCV_EXCP_NONE; 731 } 732 733 static RISCVException read_misa_i128(CPURISCVState *env, int csrno, 734 Int128 *val) 735 { 736 *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62); 737 return RISCV_EXCP_NONE; 738 } 739 740 static RISCVException read_misa(CPURISCVState *env, int csrno, 741 target_ulong *val) 742 { 743 target_ulong misa; 744 745 switch (env->misa_mxl) { 746 case MXL_RV32: 747 misa = (target_ulong)MXL_RV32 << 30; 748 break; 749 #ifdef TARGET_RISCV64 750 case MXL_RV64: 751 misa = (target_ulong)MXL_RV64 << 62; 752 break; 753 #endif 754 default: 755 g_assert_not_reached(); 756 } 757 758 *val = misa | env->misa_ext; 759 return RISCV_EXCP_NONE; 760 } 761 762 static RISCVException write_misa(CPURISCVState *env, int csrno, 763 target_ulong val) 764 { 765 if (!riscv_feature(env, RISCV_FEATURE_MISA)) { 766 /* drop write to misa */ 767 return RISCV_EXCP_NONE; 768 } 769 770 /* 'I' or 'E' must be present */ 771 if (!(val & (RVI | RVE))) { 772 /* It is not, drop write to misa */ 773 return RISCV_EXCP_NONE; 774 } 775 776 /* 'E' excludes all other extensions */ 777 if (val & RVE) { 778 /* when we support 'E' we can do "val = RVE;" however 779 * for now we just drop writes if 'E' is present. 780 */ 781 return RISCV_EXCP_NONE; 782 } 783 784 /* 785 * misa.MXL writes are not supported by QEMU. 786 * Drop writes to those bits. 787 */ 788 789 /* Mask extensions that are not supported by this hart */ 790 val &= env->misa_ext_mask; 791 792 /* Mask extensions that are not supported by QEMU */ 793 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); 794 795 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ 796 if ((val & RVD) && !(val & RVF)) { 797 val &= ~RVD; 798 } 799 800 /* Suppress 'C' if next instruction is not aligned 801 * TODO: this should check next_pc 802 */ 803 if ((val & RVC) && (GETPC() & ~3) != 0) { 804 val &= ~RVC; 805 } 806 807 /* If nothing changed, do nothing. */ 808 if (val == env->misa_ext) { 809 return RISCV_EXCP_NONE; 810 } 811 812 if (!(val & RVF)) { 813 env->mstatus &= ~MSTATUS_FS; 814 } 815 816 /* flush translation cache */ 817 tb_flush(env_cpu(env)); 818 env->misa_ext = val; 819 env->xl = riscv_cpu_mxl(env); 820 return RISCV_EXCP_NONE; 821 } 822 823 static RISCVException read_medeleg(CPURISCVState *env, int csrno, 824 target_ulong *val) 825 { 826 *val = env->medeleg; 827 return RISCV_EXCP_NONE; 828 } 829 830 static RISCVException write_medeleg(CPURISCVState *env, int csrno, 831 target_ulong val) 832 { 833 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); 834 return RISCV_EXCP_NONE; 835 } 836 837 static RISCVException rmw_mideleg64(CPURISCVState *env, int csrno, 838 uint64_t *ret_val, 839 uint64_t new_val, uint64_t wr_mask) 840 { 841 uint64_t mask = wr_mask & delegable_ints; 842 843 if (ret_val) { 844 *ret_val = env->mideleg; 845 } 846 847 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); 848 849 if (riscv_has_ext(env, RVH)) { 850 env->mideleg |= HS_MODE_INTERRUPTS; 851 } 852 853 return RISCV_EXCP_NONE; 854 } 855 856 static RISCVException rmw_mideleg(CPURISCVState *env, int csrno, 857 target_ulong *ret_val, 858 target_ulong new_val, target_ulong wr_mask) 859 { 860 uint64_t rval; 861 RISCVException ret; 862 863 ret = rmw_mideleg64(env, csrno, &rval, new_val, wr_mask); 864 if (ret_val) { 865 *ret_val = rval; 866 } 867 868 return ret; 869 } 870 871 static RISCVException rmw_midelegh(CPURISCVState *env, int csrno, 872 target_ulong *ret_val, 873 target_ulong new_val, 874 target_ulong wr_mask) 875 { 876 uint64_t rval; 877 RISCVException ret; 878 879 ret = rmw_mideleg64(env, csrno, &rval, 880 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 881 if (ret_val) { 882 *ret_val = rval >> 32; 883 } 884 885 return ret; 886 } 887 888 static RISCVException rmw_mie64(CPURISCVState *env, int csrno, 889 uint64_t *ret_val, 890 uint64_t new_val, uint64_t wr_mask) 891 { 892 uint64_t mask = wr_mask & all_ints; 893 894 if (ret_val) { 895 *ret_val = env->mie; 896 } 897 898 env->mie = (env->mie & ~mask) | (new_val & mask); 899 900 if (!riscv_has_ext(env, RVH)) { 901 env->mie &= ~((uint64_t)MIP_SGEIP); 902 } 903 904 return RISCV_EXCP_NONE; 905 } 906 907 static RISCVException rmw_mie(CPURISCVState *env, int csrno, 908 target_ulong *ret_val, 909 target_ulong new_val, target_ulong wr_mask) 910 { 911 uint64_t rval; 912 RISCVException ret; 913 914 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask); 915 if (ret_val) { 916 *ret_val = rval; 917 } 918 919 return ret; 920 } 921 922 static RISCVException rmw_mieh(CPURISCVState *env, int csrno, 923 target_ulong *ret_val, 924 target_ulong new_val, target_ulong wr_mask) 925 { 926 uint64_t rval; 927 RISCVException ret; 928 929 ret = rmw_mie64(env, csrno, &rval, 930 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 931 if (ret_val) { 932 *ret_val = rval >> 32; 933 } 934 935 return ret; 936 } 937 938 static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) 939 { 940 int irq; 941 uint8_t iprio; 942 943 irq = riscv_cpu_mirq_pending(env); 944 if (irq <= 0 || irq > 63) { 945 *val = 0; 946 } else { 947 iprio = env->miprio[irq]; 948 if (!iprio) { 949 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { 950 iprio = IPRIO_MMAXIPRIO; 951 } 952 } 953 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 954 *val |= iprio; 955 } 956 957 return RISCV_EXCP_NONE; 958 } 959 960 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) 961 { 962 if (!riscv_cpu_virt_enabled(env)) { 963 return csrno; 964 } 965 966 switch (csrno) { 967 case CSR_SISELECT: 968 return CSR_VSISELECT; 969 case CSR_SIREG: 970 return CSR_VSIREG; 971 case CSR_SSETEIPNUM: 972 return CSR_VSSETEIPNUM; 973 case CSR_SCLREIPNUM: 974 return CSR_VSCLREIPNUM; 975 case CSR_SSETEIENUM: 976 return CSR_VSSETEIENUM; 977 case CSR_SCLREIENUM: 978 return CSR_VSCLREIENUM; 979 case CSR_STOPEI: 980 return CSR_VSTOPEI; 981 default: 982 return csrno; 983 }; 984 } 985 986 static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, 987 target_ulong new_val, target_ulong wr_mask) 988 { 989 target_ulong *iselect; 990 991 /* Translate CSR number for VS-mode */ 992 csrno = aia_xlate_vs_csrno(env, csrno); 993 994 /* Find the iselect CSR based on CSR number */ 995 switch (csrno) { 996 case CSR_MISELECT: 997 iselect = &env->miselect; 998 break; 999 case CSR_SISELECT: 1000 iselect = &env->siselect; 1001 break; 1002 case CSR_VSISELECT: 1003 iselect = &env->vsiselect; 1004 break; 1005 default: 1006 return RISCV_EXCP_ILLEGAL_INST; 1007 }; 1008 1009 if (val) { 1010 *val = *iselect; 1011 } 1012 1013 wr_mask &= ISELECT_MASK; 1014 if (wr_mask) { 1015 *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); 1016 } 1017 1018 return RISCV_EXCP_NONE; 1019 } 1020 1021 static int rmw_iprio(target_ulong xlen, 1022 target_ulong iselect, uint8_t *iprio, 1023 target_ulong *val, target_ulong new_val, 1024 target_ulong wr_mask, int ext_irq_no) 1025 { 1026 int i, firq, nirqs; 1027 target_ulong old_val; 1028 1029 if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) { 1030 return -EINVAL; 1031 } 1032 if (xlen != 32 && iselect & 0x1) { 1033 return -EINVAL; 1034 } 1035 1036 nirqs = 4 * (xlen / 32); 1037 firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs); 1038 1039 old_val = 0; 1040 for (i = 0; i < nirqs; i++) { 1041 old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i); 1042 } 1043 1044 if (val) { 1045 *val = old_val; 1046 } 1047 1048 if (wr_mask) { 1049 new_val = (old_val & ~wr_mask) | (new_val & wr_mask); 1050 for (i = 0; i < nirqs; i++) { 1051 /* 1052 * M-level and S-level external IRQ priority always read-only 1053 * zero. This means default priority order is always preferred 1054 * for M-level and S-level external IRQs. 1055 */ 1056 if ((firq + i) == ext_irq_no) { 1057 continue; 1058 } 1059 iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff; 1060 } 1061 } 1062 1063 return 0; 1064 } 1065 1066 static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, 1067 target_ulong new_val, target_ulong wr_mask) 1068 { 1069 bool virt; 1070 uint8_t *iprio; 1071 int ret = -EINVAL; 1072 target_ulong priv, isel, vgein; 1073 1074 /* Translate CSR number for VS-mode */ 1075 csrno = aia_xlate_vs_csrno(env, csrno); 1076 1077 /* Decode register details from CSR number */ 1078 virt = false; 1079 switch (csrno) { 1080 case CSR_MIREG: 1081 iprio = env->miprio; 1082 isel = env->miselect; 1083 priv = PRV_M; 1084 break; 1085 case CSR_SIREG: 1086 iprio = env->siprio; 1087 isel = env->siselect; 1088 priv = PRV_S; 1089 break; 1090 case CSR_VSIREG: 1091 iprio = env->hviprio; 1092 isel = env->vsiselect; 1093 priv = PRV_S; 1094 virt = true; 1095 break; 1096 default: 1097 goto done; 1098 }; 1099 1100 /* Find the selected guest interrupt file */ 1101 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1102 1103 if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) { 1104 /* Local interrupt priority registers not available for VS-mode */ 1105 if (!virt) { 1106 ret = rmw_iprio(riscv_cpu_mxl_bits(env), 1107 isel, iprio, val, new_val, wr_mask, 1108 (priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); 1109 } 1110 } else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) { 1111 /* IMSIC registers only available when machine implements it. */ 1112 if (env->aia_ireg_rmw_fn[priv]) { 1113 /* Selected guest interrupt file should not be zero */ 1114 if (virt && (!vgein || env->geilen < vgein)) { 1115 goto done; 1116 } 1117 /* Call machine specific IMSIC register emulation */ 1118 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1119 AIA_MAKE_IREG(isel, priv, virt, vgein, 1120 riscv_cpu_mxl_bits(env)), 1121 val, new_val, wr_mask); 1122 } 1123 } 1124 1125 done: 1126 if (ret) { 1127 return (riscv_cpu_virt_enabled(env) && virt) ? 1128 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1129 } 1130 return RISCV_EXCP_NONE; 1131 } 1132 1133 static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val, 1134 target_ulong new_val, target_ulong wr_mask) 1135 { 1136 int ret = -EINVAL; 1137 bool set, pend, virt; 1138 target_ulong priv, isel, vgein, xlen, nval, wmask; 1139 1140 /* Translate CSR number for VS-mode */ 1141 csrno = aia_xlate_vs_csrno(env, csrno); 1142 1143 /* Decode register details from CSR number */ 1144 virt = set = pend = false; 1145 switch (csrno) { 1146 case CSR_MSETEIPNUM: 1147 priv = PRV_M; 1148 set = true; 1149 pend = true; 1150 break; 1151 case CSR_MCLREIPNUM: 1152 priv = PRV_M; 1153 pend = true; 1154 break; 1155 case CSR_MSETEIENUM: 1156 priv = PRV_M; 1157 set = true; 1158 break; 1159 case CSR_MCLREIENUM: 1160 priv = PRV_M; 1161 break; 1162 case CSR_SSETEIPNUM: 1163 priv = PRV_S; 1164 set = true; 1165 pend = true; 1166 break; 1167 case CSR_SCLREIPNUM: 1168 priv = PRV_S; 1169 pend = true; 1170 break; 1171 case CSR_SSETEIENUM: 1172 priv = PRV_S; 1173 set = true; 1174 break; 1175 case CSR_SCLREIENUM: 1176 priv = PRV_S; 1177 break; 1178 case CSR_VSSETEIPNUM: 1179 priv = PRV_S; 1180 virt = true; 1181 set = true; 1182 pend = true; 1183 break; 1184 case CSR_VSCLREIPNUM: 1185 priv = PRV_S; 1186 virt = true; 1187 pend = true; 1188 break; 1189 case CSR_VSSETEIENUM: 1190 priv = PRV_S; 1191 virt = true; 1192 set = true; 1193 break; 1194 case CSR_VSCLREIENUM: 1195 priv = PRV_S; 1196 virt = true; 1197 break; 1198 default: 1199 goto done; 1200 }; 1201 1202 /* IMSIC CSRs only available when machine implements IMSIC. */ 1203 if (!env->aia_ireg_rmw_fn[priv]) { 1204 goto done; 1205 } 1206 1207 /* Find the selected guest interrupt file */ 1208 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1209 1210 /* Selected guest interrupt file should be valid */ 1211 if (virt && (!vgein || env->geilen < vgein)) { 1212 goto done; 1213 } 1214 1215 /* Set/Clear CSRs always read zero */ 1216 if (val) { 1217 *val = 0; 1218 } 1219 1220 if (wr_mask) { 1221 /* Get interrupt number */ 1222 new_val &= wr_mask; 1223 1224 /* Find target interrupt pending/enable register */ 1225 xlen = riscv_cpu_mxl_bits(env); 1226 isel = (new_val / xlen); 1227 isel *= (xlen / IMSIC_EIPx_BITS); 1228 isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0; 1229 1230 /* Find the interrupt bit to be set/clear */ 1231 wmask = ((target_ulong)1) << (new_val % xlen); 1232 nval = (set) ? wmask : 0; 1233 1234 /* Call machine specific IMSIC register emulation */ 1235 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1236 AIA_MAKE_IREG(isel, priv, virt, 1237 vgein, xlen), 1238 NULL, nval, wmask); 1239 } else { 1240 ret = 0; 1241 } 1242 1243 done: 1244 if (ret) { 1245 return (riscv_cpu_virt_enabled(env) && virt) ? 1246 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1247 } 1248 return RISCV_EXCP_NONE; 1249 } 1250 1251 static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val, 1252 target_ulong new_val, target_ulong wr_mask) 1253 { 1254 bool virt; 1255 int ret = -EINVAL; 1256 target_ulong priv, vgein; 1257 1258 /* Translate CSR number for VS-mode */ 1259 csrno = aia_xlate_vs_csrno(env, csrno); 1260 1261 /* Decode register details from CSR number */ 1262 virt = false; 1263 switch (csrno) { 1264 case CSR_MTOPEI: 1265 priv = PRV_M; 1266 break; 1267 case CSR_STOPEI: 1268 priv = PRV_S; 1269 break; 1270 case CSR_VSTOPEI: 1271 priv = PRV_S; 1272 virt = true; 1273 break; 1274 default: 1275 goto done; 1276 }; 1277 1278 /* IMSIC CSRs only available when machine implements IMSIC. */ 1279 if (!env->aia_ireg_rmw_fn[priv]) { 1280 goto done; 1281 } 1282 1283 /* Find the selected guest interrupt file */ 1284 vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; 1285 1286 /* Selected guest interrupt file should be valid */ 1287 if (virt && (!vgein || env->geilen < vgein)) { 1288 goto done; 1289 } 1290 1291 /* Call machine specific IMSIC register emulation for TOPEI */ 1292 ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv], 1293 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein, 1294 riscv_cpu_mxl_bits(env)), 1295 val, new_val, wr_mask); 1296 1297 done: 1298 if (ret) { 1299 return (riscv_cpu_virt_enabled(env) && virt) ? 1300 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 1301 } 1302 return RISCV_EXCP_NONE; 1303 } 1304 1305 static RISCVException read_mtvec(CPURISCVState *env, int csrno, 1306 target_ulong *val) 1307 { 1308 *val = env->mtvec; 1309 return RISCV_EXCP_NONE; 1310 } 1311 1312 static RISCVException write_mtvec(CPURISCVState *env, int csrno, 1313 target_ulong val) 1314 { 1315 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1316 if ((val & 3) < 2) { 1317 env->mtvec = val; 1318 } else { 1319 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n"); 1320 } 1321 return RISCV_EXCP_NONE; 1322 } 1323 1324 static RISCVException read_mcounteren(CPURISCVState *env, int csrno, 1325 target_ulong *val) 1326 { 1327 *val = env->mcounteren; 1328 return RISCV_EXCP_NONE; 1329 } 1330 1331 static RISCVException write_mcounteren(CPURISCVState *env, int csrno, 1332 target_ulong val) 1333 { 1334 env->mcounteren = val; 1335 return RISCV_EXCP_NONE; 1336 } 1337 1338 /* Machine Trap Handling */ 1339 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno, 1340 Int128 *val) 1341 { 1342 *val = int128_make128(env->mscratch, env->mscratchh); 1343 return RISCV_EXCP_NONE; 1344 } 1345 1346 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno, 1347 Int128 val) 1348 { 1349 env->mscratch = int128_getlo(val); 1350 env->mscratchh = int128_gethi(val); 1351 return RISCV_EXCP_NONE; 1352 } 1353 1354 static RISCVException read_mscratch(CPURISCVState *env, int csrno, 1355 target_ulong *val) 1356 { 1357 *val = env->mscratch; 1358 return RISCV_EXCP_NONE; 1359 } 1360 1361 static RISCVException write_mscratch(CPURISCVState *env, int csrno, 1362 target_ulong val) 1363 { 1364 env->mscratch = val; 1365 return RISCV_EXCP_NONE; 1366 } 1367 1368 static RISCVException read_mepc(CPURISCVState *env, int csrno, 1369 target_ulong *val) 1370 { 1371 *val = env->mepc; 1372 return RISCV_EXCP_NONE; 1373 } 1374 1375 static RISCVException write_mepc(CPURISCVState *env, int csrno, 1376 target_ulong val) 1377 { 1378 env->mepc = val; 1379 return RISCV_EXCP_NONE; 1380 } 1381 1382 static RISCVException read_mcause(CPURISCVState *env, int csrno, 1383 target_ulong *val) 1384 { 1385 *val = env->mcause; 1386 return RISCV_EXCP_NONE; 1387 } 1388 1389 static RISCVException write_mcause(CPURISCVState *env, int csrno, 1390 target_ulong val) 1391 { 1392 env->mcause = val; 1393 return RISCV_EXCP_NONE; 1394 } 1395 1396 static RISCVException read_mtval(CPURISCVState *env, int csrno, 1397 target_ulong *val) 1398 { 1399 *val = env->mtval; 1400 return RISCV_EXCP_NONE; 1401 } 1402 1403 static RISCVException write_mtval(CPURISCVState *env, int csrno, 1404 target_ulong val) 1405 { 1406 env->mtval = val; 1407 return RISCV_EXCP_NONE; 1408 } 1409 1410 /* Execution environment configuration setup */ 1411 static RISCVException read_menvcfg(CPURISCVState *env, int csrno, 1412 target_ulong *val) 1413 { 1414 *val = env->menvcfg; 1415 return RISCV_EXCP_NONE; 1416 } 1417 1418 static RISCVException write_menvcfg(CPURISCVState *env, int csrno, 1419 target_ulong val) 1420 { 1421 uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; 1422 1423 if (riscv_cpu_mxl(env) == MXL_RV64) { 1424 mask |= MENVCFG_PBMTE | MENVCFG_STCE; 1425 } 1426 env->menvcfg = (env->menvcfg & ~mask) | (val & mask); 1427 1428 return RISCV_EXCP_NONE; 1429 } 1430 1431 static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, 1432 target_ulong *val) 1433 { 1434 *val = env->menvcfg >> 32; 1435 return RISCV_EXCP_NONE; 1436 } 1437 1438 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, 1439 target_ulong val) 1440 { 1441 uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; 1442 uint64_t valh = (uint64_t)val << 32; 1443 1444 env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); 1445 1446 return RISCV_EXCP_NONE; 1447 } 1448 1449 static RISCVException read_senvcfg(CPURISCVState *env, int csrno, 1450 target_ulong *val) 1451 { 1452 *val = env->senvcfg; 1453 return RISCV_EXCP_NONE; 1454 } 1455 1456 static RISCVException write_senvcfg(CPURISCVState *env, int csrno, 1457 target_ulong val) 1458 { 1459 uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; 1460 1461 env->senvcfg = (env->senvcfg & ~mask) | (val & mask); 1462 1463 return RISCV_EXCP_NONE; 1464 } 1465 1466 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, 1467 target_ulong *val) 1468 { 1469 *val = env->henvcfg; 1470 return RISCV_EXCP_NONE; 1471 } 1472 1473 static RISCVException write_henvcfg(CPURISCVState *env, int csrno, 1474 target_ulong val) 1475 { 1476 uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; 1477 1478 if (riscv_cpu_mxl(env) == MXL_RV64) { 1479 mask |= HENVCFG_PBMTE | HENVCFG_STCE; 1480 } 1481 1482 env->henvcfg = (env->henvcfg & ~mask) | (val & mask); 1483 1484 return RISCV_EXCP_NONE; 1485 } 1486 1487 static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, 1488 target_ulong *val) 1489 { 1490 *val = env->henvcfg >> 32; 1491 return RISCV_EXCP_NONE; 1492 } 1493 1494 static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, 1495 target_ulong val) 1496 { 1497 uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; 1498 uint64_t valh = (uint64_t)val << 32; 1499 1500 env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); 1501 1502 return RISCV_EXCP_NONE; 1503 } 1504 1505 static RISCVException rmw_mip64(CPURISCVState *env, int csrno, 1506 uint64_t *ret_val, 1507 uint64_t new_val, uint64_t wr_mask) 1508 { 1509 RISCVCPU *cpu = env_archcpu(env); 1510 uint64_t old_mip, mask = wr_mask & delegable_ints; 1511 uint32_t gin; 1512 1513 if (mask & MIP_SEIP) { 1514 env->software_seip = new_val & MIP_SEIP; 1515 new_val |= env->external_seip * MIP_SEIP; 1516 } 1517 1518 if (mask) { 1519 old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask)); 1520 } else { 1521 old_mip = env->mip; 1522 } 1523 1524 if (csrno != CSR_HVIP) { 1525 gin = get_field(env->hstatus, HSTATUS_VGEIN); 1526 old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; 1527 } 1528 1529 if (ret_val) { 1530 *ret_val = old_mip; 1531 } 1532 1533 return RISCV_EXCP_NONE; 1534 } 1535 1536 static RISCVException rmw_mip(CPURISCVState *env, int csrno, 1537 target_ulong *ret_val, 1538 target_ulong new_val, target_ulong wr_mask) 1539 { 1540 uint64_t rval; 1541 RISCVException ret; 1542 1543 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask); 1544 if (ret_val) { 1545 *ret_val = rval; 1546 } 1547 1548 return ret; 1549 } 1550 1551 static RISCVException rmw_miph(CPURISCVState *env, int csrno, 1552 target_ulong *ret_val, 1553 target_ulong new_val, target_ulong wr_mask) 1554 { 1555 uint64_t rval; 1556 RISCVException ret; 1557 1558 ret = rmw_mip64(env, csrno, &rval, 1559 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1560 if (ret_val) { 1561 *ret_val = rval >> 32; 1562 } 1563 1564 return ret; 1565 } 1566 1567 /* Supervisor Trap Setup */ 1568 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, 1569 Int128 *val) 1570 { 1571 uint64_t mask = sstatus_v1_10_mask; 1572 uint64_t sstatus = env->mstatus & mask; 1573 if (env->xl != MXL_RV32 || env->debugger) { 1574 mask |= SSTATUS64_UXL; 1575 } 1576 1577 *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); 1578 return RISCV_EXCP_NONE; 1579 } 1580 1581 static RISCVException read_sstatus(CPURISCVState *env, int csrno, 1582 target_ulong *val) 1583 { 1584 target_ulong mask = (sstatus_v1_10_mask); 1585 if (env->xl != MXL_RV32 || env->debugger) { 1586 mask |= SSTATUS64_UXL; 1587 } 1588 /* TODO: Use SXL not MXL. */ 1589 *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); 1590 return RISCV_EXCP_NONE; 1591 } 1592 1593 static RISCVException write_sstatus(CPURISCVState *env, int csrno, 1594 target_ulong val) 1595 { 1596 target_ulong mask = (sstatus_v1_10_mask); 1597 1598 if (env->xl != MXL_RV32 || env->debugger) { 1599 if ((val & SSTATUS64_UXL) != 0) { 1600 mask |= SSTATUS64_UXL; 1601 } 1602 } 1603 target_ulong newval = (env->mstatus & ~mask) | (val & mask); 1604 return write_mstatus(env, CSR_MSTATUS, newval); 1605 } 1606 1607 static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, 1608 uint64_t *ret_val, 1609 uint64_t new_val, uint64_t wr_mask) 1610 { 1611 RISCVException ret; 1612 uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; 1613 1614 /* Bring VS-level bits to correct position */ 1615 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1616 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1617 new_val |= vsbits << 1; 1618 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1619 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1620 wr_mask |= vsbits << 1; 1621 1622 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); 1623 if (ret_val) { 1624 rval &= mask; 1625 vsbits = rval & VS_MODE_INTERRUPTS; 1626 rval &= ~VS_MODE_INTERRUPTS; 1627 *ret_val = rval | (vsbits >> 1); 1628 } 1629 1630 return ret; 1631 } 1632 1633 static RISCVException rmw_vsie(CPURISCVState *env, int csrno, 1634 target_ulong *ret_val, 1635 target_ulong new_val, target_ulong wr_mask) 1636 { 1637 uint64_t rval; 1638 RISCVException ret; 1639 1640 ret = rmw_vsie64(env, csrno, &rval, new_val, wr_mask); 1641 if (ret_val) { 1642 *ret_val = rval; 1643 } 1644 1645 return ret; 1646 } 1647 1648 static RISCVException rmw_vsieh(CPURISCVState *env, int csrno, 1649 target_ulong *ret_val, 1650 target_ulong new_val, target_ulong wr_mask) 1651 { 1652 uint64_t rval; 1653 RISCVException ret; 1654 1655 ret = rmw_vsie64(env, csrno, &rval, 1656 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1657 if (ret_val) { 1658 *ret_val = rval >> 32; 1659 } 1660 1661 return ret; 1662 } 1663 1664 static RISCVException rmw_sie64(CPURISCVState *env, int csrno, 1665 uint64_t *ret_val, 1666 uint64_t new_val, uint64_t wr_mask) 1667 { 1668 RISCVException ret; 1669 uint64_t mask = env->mideleg & S_MODE_INTERRUPTS; 1670 1671 if (riscv_cpu_virt_enabled(env)) { 1672 if (env->hvictl & HVICTL_VTI) { 1673 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1674 } 1675 ret = rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); 1676 } else { 1677 ret = rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); 1678 } 1679 1680 if (ret_val) { 1681 *ret_val &= mask; 1682 } 1683 1684 return ret; 1685 } 1686 1687 static RISCVException rmw_sie(CPURISCVState *env, int csrno, 1688 target_ulong *ret_val, 1689 target_ulong new_val, target_ulong wr_mask) 1690 { 1691 uint64_t rval; 1692 RISCVException ret; 1693 1694 ret = rmw_sie64(env, csrno, &rval, new_val, wr_mask); 1695 if (ret == RISCV_EXCP_NONE && ret_val) { 1696 *ret_val = rval; 1697 } 1698 1699 return ret; 1700 } 1701 1702 static RISCVException rmw_sieh(CPURISCVState *env, int csrno, 1703 target_ulong *ret_val, 1704 target_ulong new_val, target_ulong wr_mask) 1705 { 1706 uint64_t rval; 1707 RISCVException ret; 1708 1709 ret = rmw_sie64(env, csrno, &rval, 1710 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1711 if (ret_val) { 1712 *ret_val = rval >> 32; 1713 } 1714 1715 return ret; 1716 } 1717 1718 static RISCVException read_stvec(CPURISCVState *env, int csrno, 1719 target_ulong *val) 1720 { 1721 *val = env->stvec; 1722 return RISCV_EXCP_NONE; 1723 } 1724 1725 static RISCVException write_stvec(CPURISCVState *env, int csrno, 1726 target_ulong val) 1727 { 1728 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ 1729 if ((val & 3) < 2) { 1730 env->stvec = val; 1731 } else { 1732 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n"); 1733 } 1734 return RISCV_EXCP_NONE; 1735 } 1736 1737 static RISCVException read_scounteren(CPURISCVState *env, int csrno, 1738 target_ulong *val) 1739 { 1740 *val = env->scounteren; 1741 return RISCV_EXCP_NONE; 1742 } 1743 1744 static RISCVException write_scounteren(CPURISCVState *env, int csrno, 1745 target_ulong val) 1746 { 1747 env->scounteren = val; 1748 return RISCV_EXCP_NONE; 1749 } 1750 1751 /* Supervisor Trap Handling */ 1752 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno, 1753 Int128 *val) 1754 { 1755 *val = int128_make128(env->sscratch, env->sscratchh); 1756 return RISCV_EXCP_NONE; 1757 } 1758 1759 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno, 1760 Int128 val) 1761 { 1762 env->sscratch = int128_getlo(val); 1763 env->sscratchh = int128_gethi(val); 1764 return RISCV_EXCP_NONE; 1765 } 1766 1767 static RISCVException read_sscratch(CPURISCVState *env, int csrno, 1768 target_ulong *val) 1769 { 1770 *val = env->sscratch; 1771 return RISCV_EXCP_NONE; 1772 } 1773 1774 static RISCVException write_sscratch(CPURISCVState *env, int csrno, 1775 target_ulong val) 1776 { 1777 env->sscratch = val; 1778 return RISCV_EXCP_NONE; 1779 } 1780 1781 static RISCVException read_sepc(CPURISCVState *env, int csrno, 1782 target_ulong *val) 1783 { 1784 *val = env->sepc; 1785 return RISCV_EXCP_NONE; 1786 } 1787 1788 static RISCVException write_sepc(CPURISCVState *env, int csrno, 1789 target_ulong val) 1790 { 1791 env->sepc = val; 1792 return RISCV_EXCP_NONE; 1793 } 1794 1795 static RISCVException read_scause(CPURISCVState *env, int csrno, 1796 target_ulong *val) 1797 { 1798 *val = env->scause; 1799 return RISCV_EXCP_NONE; 1800 } 1801 1802 static RISCVException write_scause(CPURISCVState *env, int csrno, 1803 target_ulong val) 1804 { 1805 env->scause = val; 1806 return RISCV_EXCP_NONE; 1807 } 1808 1809 static RISCVException read_stval(CPURISCVState *env, int csrno, 1810 target_ulong *val) 1811 { 1812 *val = env->stval; 1813 return RISCV_EXCP_NONE; 1814 } 1815 1816 static RISCVException write_stval(CPURISCVState *env, int csrno, 1817 target_ulong val) 1818 { 1819 env->stval = val; 1820 return RISCV_EXCP_NONE; 1821 } 1822 1823 static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, 1824 uint64_t *ret_val, 1825 uint64_t new_val, uint64_t wr_mask) 1826 { 1827 RISCVException ret; 1828 uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; 1829 1830 /* Bring VS-level bits to correct position */ 1831 vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); 1832 new_val &= ~(VS_MODE_INTERRUPTS >> 1); 1833 new_val |= vsbits << 1; 1834 vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); 1835 wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); 1836 wr_mask |= vsbits << 1; 1837 1838 ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); 1839 if (ret_val) { 1840 rval &= mask; 1841 vsbits = rval & VS_MODE_INTERRUPTS; 1842 rval &= ~VS_MODE_INTERRUPTS; 1843 *ret_val = rval | (vsbits >> 1); 1844 } 1845 1846 return ret; 1847 } 1848 1849 static RISCVException rmw_vsip(CPURISCVState *env, int csrno, 1850 target_ulong *ret_val, 1851 target_ulong new_val, target_ulong wr_mask) 1852 { 1853 uint64_t rval; 1854 RISCVException ret; 1855 1856 ret = rmw_vsip64(env, csrno, &rval, new_val, wr_mask); 1857 if (ret_val) { 1858 *ret_val = rval; 1859 } 1860 1861 return ret; 1862 } 1863 1864 static RISCVException rmw_vsiph(CPURISCVState *env, int csrno, 1865 target_ulong *ret_val, 1866 target_ulong new_val, target_ulong wr_mask) 1867 { 1868 uint64_t rval; 1869 RISCVException ret; 1870 1871 ret = rmw_vsip64(env, csrno, &rval, 1872 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1873 if (ret_val) { 1874 *ret_val = rval >> 32; 1875 } 1876 1877 return ret; 1878 } 1879 1880 static RISCVException rmw_sip64(CPURISCVState *env, int csrno, 1881 uint64_t *ret_val, 1882 uint64_t new_val, uint64_t wr_mask) 1883 { 1884 RISCVException ret; 1885 uint64_t mask = env->mideleg & sip_writable_mask; 1886 1887 if (riscv_cpu_virt_enabled(env)) { 1888 if (env->hvictl & HVICTL_VTI) { 1889 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; 1890 } 1891 ret = rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); 1892 } else { 1893 ret = rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); 1894 } 1895 1896 if (ret_val) { 1897 *ret_val &= env->mideleg & S_MODE_INTERRUPTS; 1898 } 1899 1900 return ret; 1901 } 1902 1903 static RISCVException rmw_sip(CPURISCVState *env, int csrno, 1904 target_ulong *ret_val, 1905 target_ulong new_val, target_ulong wr_mask) 1906 { 1907 uint64_t rval; 1908 RISCVException ret; 1909 1910 ret = rmw_sip64(env, csrno, &rval, new_val, wr_mask); 1911 if (ret_val) { 1912 *ret_val = rval; 1913 } 1914 1915 return ret; 1916 } 1917 1918 static RISCVException rmw_siph(CPURISCVState *env, int csrno, 1919 target_ulong *ret_val, 1920 target_ulong new_val, target_ulong wr_mask) 1921 { 1922 uint64_t rval; 1923 RISCVException ret; 1924 1925 ret = rmw_sip64(env, csrno, &rval, 1926 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 1927 if (ret_val) { 1928 *ret_val = rval >> 32; 1929 } 1930 1931 return ret; 1932 } 1933 1934 /* Supervisor Protection and Translation */ 1935 static RISCVException read_satp(CPURISCVState *env, int csrno, 1936 target_ulong *val) 1937 { 1938 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1939 *val = 0; 1940 return RISCV_EXCP_NONE; 1941 } 1942 1943 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1944 return RISCV_EXCP_ILLEGAL_INST; 1945 } else { 1946 *val = env->satp; 1947 } 1948 1949 return RISCV_EXCP_NONE; 1950 } 1951 1952 static RISCVException write_satp(CPURISCVState *env, int csrno, 1953 target_ulong val) 1954 { 1955 target_ulong vm, mask; 1956 1957 if (!riscv_feature(env, RISCV_FEATURE_MMU)) { 1958 return RISCV_EXCP_NONE; 1959 } 1960 1961 if (riscv_cpu_mxl(env) == MXL_RV32) { 1962 vm = validate_vm(env, get_field(val, SATP32_MODE)); 1963 mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); 1964 } else { 1965 vm = validate_vm(env, get_field(val, SATP64_MODE)); 1966 mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); 1967 } 1968 1969 if (vm && mask) { 1970 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { 1971 return RISCV_EXCP_ILLEGAL_INST; 1972 } else { 1973 /* 1974 * The ISA defines SATP.MODE=Bare as "no translation", but we still 1975 * pass these through QEMU's TLB emulation as it improves 1976 * performance. Flushing the TLB on SATP writes with paging 1977 * enabled avoids leaking those invalid cached mappings. 1978 */ 1979 tlb_flush(env_cpu(env)); 1980 env->satp = val; 1981 } 1982 } 1983 return RISCV_EXCP_NONE; 1984 } 1985 1986 static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) 1987 { 1988 int irq, ret; 1989 target_ulong topei; 1990 uint64_t vseip, vsgein; 1991 uint32_t iid, iprio, hviid, hviprio, gein; 1992 uint32_t s, scount = 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_SRCS]; 1993 1994 gein = get_field(env->hstatus, HSTATUS_VGEIN); 1995 hviid = get_field(env->hvictl, HVICTL_IID); 1996 hviprio = get_field(env->hvictl, HVICTL_IPRIO); 1997 1998 if (gein) { 1999 vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; 2000 vseip = env->mie & (env->mip | vsgein) & MIP_VSEIP; 2001 if (gein <= env->geilen && vseip) { 2002 siid[scount] = IRQ_S_EXT; 2003 siprio[scount] = IPRIO_MMAXIPRIO + 1; 2004 if (env->aia_ireg_rmw_fn[PRV_S]) { 2005 /* 2006 * Call machine specific IMSIC register emulation for 2007 * reading TOPEI. 2008 */ 2009 ret = env->aia_ireg_rmw_fn[PRV_S]( 2010 env->aia_ireg_rmw_fn_arg[PRV_S], 2011 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, gein, 2012 riscv_cpu_mxl_bits(env)), 2013 &topei, 0, 0); 2014 if (!ret && topei) { 2015 siprio[scount] = topei & IMSIC_TOPEI_IPRIO_MASK; 2016 } 2017 } 2018 scount++; 2019 } 2020 } else { 2021 if (hviid == IRQ_S_EXT && hviprio) { 2022 siid[scount] = IRQ_S_EXT; 2023 siprio[scount] = hviprio; 2024 scount++; 2025 } 2026 } 2027 2028 if (env->hvictl & HVICTL_VTI) { 2029 if (hviid != IRQ_S_EXT) { 2030 siid[scount] = hviid; 2031 siprio[scount] = hviprio; 2032 scount++; 2033 } 2034 } else { 2035 irq = riscv_cpu_vsirq_pending(env); 2036 if (irq != IRQ_S_EXT && 0 < irq && irq <= 63) { 2037 siid[scount] = irq; 2038 siprio[scount] = env->hviprio[irq]; 2039 scount++; 2040 } 2041 } 2042 2043 iid = 0; 2044 iprio = UINT_MAX; 2045 for (s = 0; s < scount; s++) { 2046 if (siprio[s] < iprio) { 2047 iid = siid[s]; 2048 iprio = siprio[s]; 2049 } 2050 } 2051 2052 if (iid) { 2053 if (env->hvictl & HVICTL_IPRIOM) { 2054 if (iprio > IPRIO_MMAXIPRIO) { 2055 iprio = IPRIO_MMAXIPRIO; 2056 } 2057 if (!iprio) { 2058 if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { 2059 iprio = IPRIO_MMAXIPRIO; 2060 } 2061 } 2062 } else { 2063 iprio = 1; 2064 } 2065 } else { 2066 iprio = 0; 2067 } 2068 2069 *val = (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2070 *val |= iprio; 2071 return RISCV_EXCP_NONE; 2072 } 2073 2074 static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) 2075 { 2076 int irq; 2077 uint8_t iprio; 2078 2079 if (riscv_cpu_virt_enabled(env)) { 2080 return read_vstopi(env, CSR_VSTOPI, val); 2081 } 2082 2083 irq = riscv_cpu_sirq_pending(env); 2084 if (irq <= 0 || irq > 63) { 2085 *val = 0; 2086 } else { 2087 iprio = env->siprio[irq]; 2088 if (!iprio) { 2089 if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { 2090 iprio = IPRIO_MMAXIPRIO; 2091 } 2092 } 2093 *val = (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; 2094 *val |= iprio; 2095 } 2096 2097 return RISCV_EXCP_NONE; 2098 } 2099 2100 /* Hypervisor Extensions */ 2101 static RISCVException read_hstatus(CPURISCVState *env, int csrno, 2102 target_ulong *val) 2103 { 2104 *val = env->hstatus; 2105 if (riscv_cpu_mxl(env) != MXL_RV32) { 2106 /* We only support 64-bit VSXL */ 2107 *val = set_field(*val, HSTATUS_VSXL, 2); 2108 } 2109 /* We only support little endian */ 2110 *val = set_field(*val, HSTATUS_VSBE, 0); 2111 return RISCV_EXCP_NONE; 2112 } 2113 2114 static RISCVException write_hstatus(CPURISCVState *env, int csrno, 2115 target_ulong val) 2116 { 2117 env->hstatus = val; 2118 if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { 2119 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options."); 2120 } 2121 if (get_field(val, HSTATUS_VSBE) != 0) { 2122 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests."); 2123 } 2124 return RISCV_EXCP_NONE; 2125 } 2126 2127 static RISCVException read_hedeleg(CPURISCVState *env, int csrno, 2128 target_ulong *val) 2129 { 2130 *val = env->hedeleg; 2131 return RISCV_EXCP_NONE; 2132 } 2133 2134 static RISCVException write_hedeleg(CPURISCVState *env, int csrno, 2135 target_ulong val) 2136 { 2137 env->hedeleg = val & vs_delegable_excps; 2138 return RISCV_EXCP_NONE; 2139 } 2140 2141 static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, 2142 uint64_t *ret_val, 2143 uint64_t new_val, uint64_t wr_mask) 2144 { 2145 uint64_t mask = wr_mask & vs_delegable_ints; 2146 2147 if (ret_val) { 2148 *ret_val = env->hideleg & vs_delegable_ints; 2149 } 2150 2151 env->hideleg = (env->hideleg & ~mask) | (new_val & mask); 2152 return RISCV_EXCP_NONE; 2153 } 2154 2155 static RISCVException rmw_hideleg(CPURISCVState *env, int csrno, 2156 target_ulong *ret_val, 2157 target_ulong new_val, target_ulong wr_mask) 2158 { 2159 uint64_t rval; 2160 RISCVException ret; 2161 2162 ret = rmw_hideleg64(env, csrno, &rval, new_val, wr_mask); 2163 if (ret_val) { 2164 *ret_val = rval; 2165 } 2166 2167 return ret; 2168 } 2169 2170 static RISCVException rmw_hidelegh(CPURISCVState *env, int csrno, 2171 target_ulong *ret_val, 2172 target_ulong new_val, target_ulong wr_mask) 2173 { 2174 uint64_t rval; 2175 RISCVException ret; 2176 2177 ret = rmw_hideleg64(env, csrno, &rval, 2178 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2179 if (ret_val) { 2180 *ret_val = rval >> 32; 2181 } 2182 2183 return ret; 2184 } 2185 2186 static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, 2187 uint64_t *ret_val, 2188 uint64_t new_val, uint64_t wr_mask) 2189 { 2190 RISCVException ret; 2191 2192 ret = rmw_mip64(env, csrno, ret_val, new_val, 2193 wr_mask & hvip_writable_mask); 2194 if (ret_val) { 2195 *ret_val &= VS_MODE_INTERRUPTS; 2196 } 2197 2198 return ret; 2199 } 2200 2201 static RISCVException rmw_hvip(CPURISCVState *env, int csrno, 2202 target_ulong *ret_val, 2203 target_ulong new_val, target_ulong wr_mask) 2204 { 2205 uint64_t rval; 2206 RISCVException ret; 2207 2208 ret = rmw_hvip64(env, csrno, &rval, new_val, wr_mask); 2209 if (ret_val) { 2210 *ret_val = rval; 2211 } 2212 2213 return ret; 2214 } 2215 2216 static RISCVException rmw_hviph(CPURISCVState *env, int csrno, 2217 target_ulong *ret_val, 2218 target_ulong new_val, target_ulong wr_mask) 2219 { 2220 uint64_t rval; 2221 RISCVException ret; 2222 2223 ret = rmw_hvip64(env, csrno, &rval, 2224 ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); 2225 if (ret_val) { 2226 *ret_val = rval >> 32; 2227 } 2228 2229 return ret; 2230 } 2231 2232 static RISCVException rmw_hip(CPURISCVState *env, int csrno, 2233 target_ulong *ret_value, 2234 target_ulong new_value, target_ulong write_mask) 2235 { 2236 int ret = rmw_mip(env, csrno, ret_value, new_value, 2237 write_mask & hip_writable_mask); 2238 2239 if (ret_value) { 2240 *ret_value &= HS_MODE_INTERRUPTS; 2241 } 2242 return ret; 2243 } 2244 2245 static RISCVException rmw_hie(CPURISCVState *env, int csrno, 2246 target_ulong *ret_val, 2247 target_ulong new_val, target_ulong wr_mask) 2248 { 2249 uint64_t rval; 2250 RISCVException ret; 2251 2252 ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & HS_MODE_INTERRUPTS); 2253 if (ret_val) { 2254 *ret_val = rval & HS_MODE_INTERRUPTS; 2255 } 2256 2257 return ret; 2258 } 2259 2260 static RISCVException read_hcounteren(CPURISCVState *env, int csrno, 2261 target_ulong *val) 2262 { 2263 *val = env->hcounteren; 2264 return RISCV_EXCP_NONE; 2265 } 2266 2267 static RISCVException write_hcounteren(CPURISCVState *env, int csrno, 2268 target_ulong val) 2269 { 2270 env->hcounteren = val; 2271 return RISCV_EXCP_NONE; 2272 } 2273 2274 static RISCVException read_hgeie(CPURISCVState *env, int csrno, 2275 target_ulong *val) 2276 { 2277 if (val) { 2278 *val = env->hgeie; 2279 } 2280 return RISCV_EXCP_NONE; 2281 } 2282 2283 static RISCVException write_hgeie(CPURISCVState *env, int csrno, 2284 target_ulong val) 2285 { 2286 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ 2287 val &= ((((target_ulong)1) << env->geilen) - 1) << 1; 2288 env->hgeie = val; 2289 /* Update mip.SGEIP bit */ 2290 riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, 2291 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 2292 return RISCV_EXCP_NONE; 2293 } 2294 2295 static RISCVException read_htval(CPURISCVState *env, int csrno, 2296 target_ulong *val) 2297 { 2298 *val = env->htval; 2299 return RISCV_EXCP_NONE; 2300 } 2301 2302 static RISCVException write_htval(CPURISCVState *env, int csrno, 2303 target_ulong val) 2304 { 2305 env->htval = val; 2306 return RISCV_EXCP_NONE; 2307 } 2308 2309 static RISCVException read_htinst(CPURISCVState *env, int csrno, 2310 target_ulong *val) 2311 { 2312 *val = env->htinst; 2313 return RISCV_EXCP_NONE; 2314 } 2315 2316 static RISCVException write_htinst(CPURISCVState *env, int csrno, 2317 target_ulong val) 2318 { 2319 return RISCV_EXCP_NONE; 2320 } 2321 2322 static RISCVException read_hgeip(CPURISCVState *env, int csrno, 2323 target_ulong *val) 2324 { 2325 if (val) { 2326 *val = env->hgeip; 2327 } 2328 return RISCV_EXCP_NONE; 2329 } 2330 2331 static RISCVException read_hgatp(CPURISCVState *env, int csrno, 2332 target_ulong *val) 2333 { 2334 *val = env->hgatp; 2335 return RISCV_EXCP_NONE; 2336 } 2337 2338 static RISCVException write_hgatp(CPURISCVState *env, int csrno, 2339 target_ulong val) 2340 { 2341 env->hgatp = val; 2342 return RISCV_EXCP_NONE; 2343 } 2344 2345 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, 2346 target_ulong *val) 2347 { 2348 if (!env->rdtime_fn) { 2349 return RISCV_EXCP_ILLEGAL_INST; 2350 } 2351 2352 *val = env->htimedelta; 2353 return RISCV_EXCP_NONE; 2354 } 2355 2356 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, 2357 target_ulong val) 2358 { 2359 if (!env->rdtime_fn) { 2360 return RISCV_EXCP_ILLEGAL_INST; 2361 } 2362 2363 if (riscv_cpu_mxl(env) == MXL_RV32) { 2364 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val); 2365 } else { 2366 env->htimedelta = val; 2367 } 2368 return RISCV_EXCP_NONE; 2369 } 2370 2371 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, 2372 target_ulong *val) 2373 { 2374 if (!env->rdtime_fn) { 2375 return RISCV_EXCP_ILLEGAL_INST; 2376 } 2377 2378 *val = env->htimedelta >> 32; 2379 return RISCV_EXCP_NONE; 2380 } 2381 2382 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, 2383 target_ulong val) 2384 { 2385 if (!env->rdtime_fn) { 2386 return RISCV_EXCP_ILLEGAL_INST; 2387 } 2388 2389 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); 2390 return RISCV_EXCP_NONE; 2391 } 2392 2393 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) 2394 { 2395 *val = env->hvictl; 2396 return RISCV_EXCP_NONE; 2397 } 2398 2399 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) 2400 { 2401 env->hvictl = val & HVICTL_VALID_MASK; 2402 return RISCV_EXCP_NONE; 2403 } 2404 2405 static int read_hvipriox(CPURISCVState *env, int first_index, 2406 uint8_t *iprio, target_ulong *val) 2407 { 2408 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2409 2410 /* First index has to be a multiple of number of irqs per register */ 2411 if (first_index % num_irqs) { 2412 return (riscv_cpu_virt_enabled(env)) ? 2413 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2414 } 2415 2416 /* Fill-up return value */ 2417 *val = 0; 2418 for (i = 0; i < num_irqs; i++) { 2419 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2420 continue; 2421 } 2422 if (rdzero) { 2423 continue; 2424 } 2425 *val |= ((target_ulong)iprio[irq]) << (i * 8); 2426 } 2427 2428 return RISCV_EXCP_NONE; 2429 } 2430 2431 static int write_hvipriox(CPURISCVState *env, int first_index, 2432 uint8_t *iprio, target_ulong val) 2433 { 2434 int i, irq, rdzero, num_irqs = 4 * (riscv_cpu_mxl_bits(env) / 32); 2435 2436 /* First index has to be a multiple of number of irqs per register */ 2437 if (first_index % num_irqs) { 2438 return (riscv_cpu_virt_enabled(env)) ? 2439 RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; 2440 } 2441 2442 /* Fill-up priority arrary */ 2443 for (i = 0; i < num_irqs; i++) { 2444 if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) { 2445 continue; 2446 } 2447 if (rdzero) { 2448 iprio[irq] = 0; 2449 } else { 2450 iprio[irq] = (val >> (i * 8)) & 0xff; 2451 } 2452 } 2453 2454 return RISCV_EXCP_NONE; 2455 } 2456 2457 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) 2458 { 2459 return read_hvipriox(env, 0, env->hviprio, val); 2460 } 2461 2462 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) 2463 { 2464 return write_hvipriox(env, 0, env->hviprio, val); 2465 } 2466 2467 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) 2468 { 2469 return read_hvipriox(env, 4, env->hviprio, val); 2470 } 2471 2472 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) 2473 { 2474 return write_hvipriox(env, 4, env->hviprio, val); 2475 } 2476 2477 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) 2478 { 2479 return read_hvipriox(env, 8, env->hviprio, val); 2480 } 2481 2482 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) 2483 { 2484 return write_hvipriox(env, 8, env->hviprio, val); 2485 } 2486 2487 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) 2488 { 2489 return read_hvipriox(env, 12, env->hviprio, val); 2490 } 2491 2492 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) 2493 { 2494 return write_hvipriox(env, 12, env->hviprio, val); 2495 } 2496 2497 /* Virtual CSR Registers */ 2498 static RISCVException read_vsstatus(CPURISCVState *env, int csrno, 2499 target_ulong *val) 2500 { 2501 *val = env->vsstatus; 2502 return RISCV_EXCP_NONE; 2503 } 2504 2505 static RISCVException write_vsstatus(CPURISCVState *env, int csrno, 2506 target_ulong val) 2507 { 2508 uint64_t mask = (target_ulong)-1; 2509 if ((val & VSSTATUS64_UXL) == 0) { 2510 mask &= ~VSSTATUS64_UXL; 2511 } 2512 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; 2513 return RISCV_EXCP_NONE; 2514 } 2515 2516 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) 2517 { 2518 *val = env->vstvec; 2519 return RISCV_EXCP_NONE; 2520 } 2521 2522 static RISCVException write_vstvec(CPURISCVState *env, int csrno, 2523 target_ulong val) 2524 { 2525 env->vstvec = val; 2526 return RISCV_EXCP_NONE; 2527 } 2528 2529 static RISCVException read_vsscratch(CPURISCVState *env, int csrno, 2530 target_ulong *val) 2531 { 2532 *val = env->vsscratch; 2533 return RISCV_EXCP_NONE; 2534 } 2535 2536 static RISCVException write_vsscratch(CPURISCVState *env, int csrno, 2537 target_ulong val) 2538 { 2539 env->vsscratch = val; 2540 return RISCV_EXCP_NONE; 2541 } 2542 2543 static RISCVException read_vsepc(CPURISCVState *env, int csrno, 2544 target_ulong *val) 2545 { 2546 *val = env->vsepc; 2547 return RISCV_EXCP_NONE; 2548 } 2549 2550 static RISCVException write_vsepc(CPURISCVState *env, int csrno, 2551 target_ulong val) 2552 { 2553 env->vsepc = val; 2554 return RISCV_EXCP_NONE; 2555 } 2556 2557 static RISCVException read_vscause(CPURISCVState *env, int csrno, 2558 target_ulong *val) 2559 { 2560 *val = env->vscause; 2561 return RISCV_EXCP_NONE; 2562 } 2563 2564 static RISCVException write_vscause(CPURISCVState *env, int csrno, 2565 target_ulong val) 2566 { 2567 env->vscause = val; 2568 return RISCV_EXCP_NONE; 2569 } 2570 2571 static RISCVException read_vstval(CPURISCVState *env, int csrno, 2572 target_ulong *val) 2573 { 2574 *val = env->vstval; 2575 return RISCV_EXCP_NONE; 2576 } 2577 2578 static RISCVException write_vstval(CPURISCVState *env, int csrno, 2579 target_ulong val) 2580 { 2581 env->vstval = val; 2582 return RISCV_EXCP_NONE; 2583 } 2584 2585 static RISCVException read_vsatp(CPURISCVState *env, int csrno, 2586 target_ulong *val) 2587 { 2588 *val = env->vsatp; 2589 return RISCV_EXCP_NONE; 2590 } 2591 2592 static RISCVException write_vsatp(CPURISCVState *env, int csrno, 2593 target_ulong val) 2594 { 2595 env->vsatp = val; 2596 return RISCV_EXCP_NONE; 2597 } 2598 2599 static RISCVException read_mtval2(CPURISCVState *env, int csrno, 2600 target_ulong *val) 2601 { 2602 *val = env->mtval2; 2603 return RISCV_EXCP_NONE; 2604 } 2605 2606 static RISCVException write_mtval2(CPURISCVState *env, int csrno, 2607 target_ulong val) 2608 { 2609 env->mtval2 = val; 2610 return RISCV_EXCP_NONE; 2611 } 2612 2613 static RISCVException read_mtinst(CPURISCVState *env, int csrno, 2614 target_ulong *val) 2615 { 2616 *val = env->mtinst; 2617 return RISCV_EXCP_NONE; 2618 } 2619 2620 static RISCVException write_mtinst(CPURISCVState *env, int csrno, 2621 target_ulong val) 2622 { 2623 env->mtinst = val; 2624 return RISCV_EXCP_NONE; 2625 } 2626 2627 /* Physical Memory Protection */ 2628 static RISCVException read_mseccfg(CPURISCVState *env, int csrno, 2629 target_ulong *val) 2630 { 2631 *val = mseccfg_csr_read(env); 2632 return RISCV_EXCP_NONE; 2633 } 2634 2635 static RISCVException write_mseccfg(CPURISCVState *env, int csrno, 2636 target_ulong val) 2637 { 2638 mseccfg_csr_write(env, val); 2639 return RISCV_EXCP_NONE; 2640 } 2641 2642 static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index) 2643 { 2644 /* TODO: RV128 restriction check */ 2645 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { 2646 return false; 2647 } 2648 return true; 2649 } 2650 2651 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno, 2652 target_ulong *val) 2653 { 2654 uint32_t reg_index = csrno - CSR_PMPCFG0; 2655 2656 if (!check_pmp_reg_index(env, reg_index)) { 2657 return RISCV_EXCP_ILLEGAL_INST; 2658 } 2659 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); 2660 return RISCV_EXCP_NONE; 2661 } 2662 2663 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno, 2664 target_ulong val) 2665 { 2666 uint32_t reg_index = csrno - CSR_PMPCFG0; 2667 2668 if (!check_pmp_reg_index(env, reg_index)) { 2669 return RISCV_EXCP_ILLEGAL_INST; 2670 } 2671 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val); 2672 return RISCV_EXCP_NONE; 2673 } 2674 2675 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno, 2676 target_ulong *val) 2677 { 2678 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); 2679 return RISCV_EXCP_NONE; 2680 } 2681 2682 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno, 2683 target_ulong val) 2684 { 2685 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val); 2686 return RISCV_EXCP_NONE; 2687 } 2688 2689 static RISCVException read_tselect(CPURISCVState *env, int csrno, 2690 target_ulong *val) 2691 { 2692 *val = tselect_csr_read(env); 2693 return RISCV_EXCP_NONE; 2694 } 2695 2696 static RISCVException write_tselect(CPURISCVState *env, int csrno, 2697 target_ulong val) 2698 { 2699 tselect_csr_write(env, val); 2700 return RISCV_EXCP_NONE; 2701 } 2702 2703 static RISCVException read_tdata(CPURISCVState *env, int csrno, 2704 target_ulong *val) 2705 { 2706 /* return 0 in tdata1 to end the trigger enumeration */ 2707 if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) { 2708 *val = 0; 2709 return RISCV_EXCP_NONE; 2710 } 2711 2712 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2713 return RISCV_EXCP_ILLEGAL_INST; 2714 } 2715 2716 *val = tdata_csr_read(env, csrno - CSR_TDATA1); 2717 return RISCV_EXCP_NONE; 2718 } 2719 2720 static RISCVException write_tdata(CPURISCVState *env, int csrno, 2721 target_ulong val) 2722 { 2723 if (!tdata_available(env, csrno - CSR_TDATA1)) { 2724 return RISCV_EXCP_ILLEGAL_INST; 2725 } 2726 2727 tdata_csr_write(env, csrno - CSR_TDATA1, val); 2728 return RISCV_EXCP_NONE; 2729 } 2730 2731 /* 2732 * Functions to access Pointer Masking feature registers 2733 * We have to check if current priv lvl could modify 2734 * csr in given mode 2735 */ 2736 static bool check_pm_current_disabled(CPURISCVState *env, int csrno) 2737 { 2738 int csr_priv = get_field(csrno, 0x300); 2739 int pm_current; 2740 2741 if (env->debugger) { 2742 return false; 2743 } 2744 /* 2745 * If priv lvls differ that means we're accessing csr from higher priv lvl, 2746 * so allow the access 2747 */ 2748 if (env->priv != csr_priv) { 2749 return false; 2750 } 2751 switch (env->priv) { 2752 case PRV_M: 2753 pm_current = get_field(env->mmte, M_PM_CURRENT); 2754 break; 2755 case PRV_S: 2756 pm_current = get_field(env->mmte, S_PM_CURRENT); 2757 break; 2758 case PRV_U: 2759 pm_current = get_field(env->mmte, U_PM_CURRENT); 2760 break; 2761 default: 2762 g_assert_not_reached(); 2763 } 2764 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */ 2765 return !pm_current; 2766 } 2767 2768 static RISCVException read_mmte(CPURISCVState *env, int csrno, 2769 target_ulong *val) 2770 { 2771 *val = env->mmte & MMTE_MASK; 2772 return RISCV_EXCP_NONE; 2773 } 2774 2775 static RISCVException write_mmte(CPURISCVState *env, int csrno, 2776 target_ulong val) 2777 { 2778 uint64_t mstatus; 2779 target_ulong wpri_val = val & MMTE_MASK; 2780 2781 if (val != wpri_val) { 2782 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2783 "MMTE: WPRI violation written 0x", val, 2784 "vs expected 0x", wpri_val); 2785 } 2786 /* for machine mode pm.current is hardwired to 1 */ 2787 wpri_val |= MMTE_M_PM_CURRENT; 2788 2789 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ 2790 wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); 2791 env->mmte = wpri_val | PM_EXT_DIRTY; 2792 riscv_cpu_update_mask(env); 2793 2794 /* Set XS and SD bits, since PM CSRs are dirty */ 2795 mstatus = env->mstatus | MSTATUS_XS; 2796 write_mstatus(env, csrno, mstatus); 2797 return RISCV_EXCP_NONE; 2798 } 2799 2800 static RISCVException read_smte(CPURISCVState *env, int csrno, 2801 target_ulong *val) 2802 { 2803 *val = env->mmte & SMTE_MASK; 2804 return RISCV_EXCP_NONE; 2805 } 2806 2807 static RISCVException write_smte(CPURISCVState *env, int csrno, 2808 target_ulong val) 2809 { 2810 target_ulong wpri_val = val & SMTE_MASK; 2811 2812 if (val != wpri_val) { 2813 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2814 "SMTE: WPRI violation written 0x", val, 2815 "vs expected 0x", wpri_val); 2816 } 2817 2818 /* if pm.current==0 we can't modify current PM CSRs */ 2819 if (check_pm_current_disabled(env, csrno)) { 2820 return RISCV_EXCP_NONE; 2821 } 2822 2823 wpri_val |= (env->mmte & ~SMTE_MASK); 2824 write_mmte(env, csrno, wpri_val); 2825 return RISCV_EXCP_NONE; 2826 } 2827 2828 static RISCVException read_umte(CPURISCVState *env, int csrno, 2829 target_ulong *val) 2830 { 2831 *val = env->mmte & UMTE_MASK; 2832 return RISCV_EXCP_NONE; 2833 } 2834 2835 static RISCVException write_umte(CPURISCVState *env, int csrno, 2836 target_ulong val) 2837 { 2838 target_ulong wpri_val = val & UMTE_MASK; 2839 2840 if (val != wpri_val) { 2841 qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n", 2842 "UMTE: WPRI violation written 0x", val, 2843 "vs expected 0x", wpri_val); 2844 } 2845 2846 if (check_pm_current_disabled(env, csrno)) { 2847 return RISCV_EXCP_NONE; 2848 } 2849 2850 wpri_val |= (env->mmte & ~UMTE_MASK); 2851 write_mmte(env, csrno, wpri_val); 2852 return RISCV_EXCP_NONE; 2853 } 2854 2855 static RISCVException read_mpmmask(CPURISCVState *env, int csrno, 2856 target_ulong *val) 2857 { 2858 *val = env->mpmmask; 2859 return RISCV_EXCP_NONE; 2860 } 2861 2862 static RISCVException write_mpmmask(CPURISCVState *env, int csrno, 2863 target_ulong val) 2864 { 2865 uint64_t mstatus; 2866 2867 env->mpmmask = val; 2868 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 2869 env->cur_pmmask = val; 2870 } 2871 env->mmte |= PM_EXT_DIRTY; 2872 2873 /* Set XS and SD bits, since PM CSRs are dirty */ 2874 mstatus = env->mstatus | MSTATUS_XS; 2875 write_mstatus(env, csrno, mstatus); 2876 return RISCV_EXCP_NONE; 2877 } 2878 2879 static RISCVException read_spmmask(CPURISCVState *env, int csrno, 2880 target_ulong *val) 2881 { 2882 *val = env->spmmask; 2883 return RISCV_EXCP_NONE; 2884 } 2885 2886 static RISCVException write_spmmask(CPURISCVState *env, int csrno, 2887 target_ulong val) 2888 { 2889 uint64_t mstatus; 2890 2891 /* if pm.current==0 we can't modify current PM CSRs */ 2892 if (check_pm_current_disabled(env, csrno)) { 2893 return RISCV_EXCP_NONE; 2894 } 2895 env->spmmask = val; 2896 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 2897 env->cur_pmmask = val; 2898 } 2899 env->mmte |= PM_EXT_DIRTY; 2900 2901 /* Set XS and SD bits, since PM CSRs are dirty */ 2902 mstatus = env->mstatus | MSTATUS_XS; 2903 write_mstatus(env, csrno, mstatus); 2904 return RISCV_EXCP_NONE; 2905 } 2906 2907 static RISCVException read_upmmask(CPURISCVState *env, int csrno, 2908 target_ulong *val) 2909 { 2910 *val = env->upmmask; 2911 return RISCV_EXCP_NONE; 2912 } 2913 2914 static RISCVException write_upmmask(CPURISCVState *env, int csrno, 2915 target_ulong val) 2916 { 2917 uint64_t mstatus; 2918 2919 /* if pm.current==0 we can't modify current PM CSRs */ 2920 if (check_pm_current_disabled(env, csrno)) { 2921 return RISCV_EXCP_NONE; 2922 } 2923 env->upmmask = val; 2924 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 2925 env->cur_pmmask = val; 2926 } 2927 env->mmte |= PM_EXT_DIRTY; 2928 2929 /* Set XS and SD bits, since PM CSRs are dirty */ 2930 mstatus = env->mstatus | MSTATUS_XS; 2931 write_mstatus(env, csrno, mstatus); 2932 return RISCV_EXCP_NONE; 2933 } 2934 2935 static RISCVException read_mpmbase(CPURISCVState *env, int csrno, 2936 target_ulong *val) 2937 { 2938 *val = env->mpmbase; 2939 return RISCV_EXCP_NONE; 2940 } 2941 2942 static RISCVException write_mpmbase(CPURISCVState *env, int csrno, 2943 target_ulong val) 2944 { 2945 uint64_t mstatus; 2946 2947 env->mpmbase = val; 2948 if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { 2949 env->cur_pmbase = val; 2950 } 2951 env->mmte |= PM_EXT_DIRTY; 2952 2953 /* Set XS and SD bits, since PM CSRs are dirty */ 2954 mstatus = env->mstatus | MSTATUS_XS; 2955 write_mstatus(env, csrno, mstatus); 2956 return RISCV_EXCP_NONE; 2957 } 2958 2959 static RISCVException read_spmbase(CPURISCVState *env, int csrno, 2960 target_ulong *val) 2961 { 2962 *val = env->spmbase; 2963 return RISCV_EXCP_NONE; 2964 } 2965 2966 static RISCVException write_spmbase(CPURISCVState *env, int csrno, 2967 target_ulong val) 2968 { 2969 uint64_t mstatus; 2970 2971 /* if pm.current==0 we can't modify current PM CSRs */ 2972 if (check_pm_current_disabled(env, csrno)) { 2973 return RISCV_EXCP_NONE; 2974 } 2975 env->spmbase = val; 2976 if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { 2977 env->cur_pmbase = val; 2978 } 2979 env->mmte |= PM_EXT_DIRTY; 2980 2981 /* Set XS and SD bits, since PM CSRs are dirty */ 2982 mstatus = env->mstatus | MSTATUS_XS; 2983 write_mstatus(env, csrno, mstatus); 2984 return RISCV_EXCP_NONE; 2985 } 2986 2987 static RISCVException read_upmbase(CPURISCVState *env, int csrno, 2988 target_ulong *val) 2989 { 2990 *val = env->upmbase; 2991 return RISCV_EXCP_NONE; 2992 } 2993 2994 static RISCVException write_upmbase(CPURISCVState *env, int csrno, 2995 target_ulong val) 2996 { 2997 uint64_t mstatus; 2998 2999 /* if pm.current==0 we can't modify current PM CSRs */ 3000 if (check_pm_current_disabled(env, csrno)) { 3001 return RISCV_EXCP_NONE; 3002 } 3003 env->upmbase = val; 3004 if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { 3005 env->cur_pmbase = val; 3006 } 3007 env->mmte |= PM_EXT_DIRTY; 3008 3009 /* Set XS and SD bits, since PM CSRs are dirty */ 3010 mstatus = env->mstatus | MSTATUS_XS; 3011 write_mstatus(env, csrno, mstatus); 3012 return RISCV_EXCP_NONE; 3013 } 3014 3015 #endif 3016 3017 /* 3018 * riscv_csrrw - read and/or update control and status register 3019 * 3020 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0); 3021 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1); 3022 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value); 3023 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value); 3024 */ 3025 3026 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, 3027 int csrno, 3028 bool write_mask, 3029 RISCVCPU *cpu) 3030 { 3031 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ 3032 int read_only = get_field(csrno, 0xC00) == 3; 3033 int csr_min_priv = csr_ops[csrno].min_priv_ver; 3034 #if !defined(CONFIG_USER_ONLY) 3035 int effective_priv = env->priv; 3036 3037 if (riscv_has_ext(env, RVH) && 3038 env->priv == PRV_S && 3039 !riscv_cpu_virt_enabled(env)) { 3040 /* 3041 * We are in S mode without virtualisation, therefore we are in HS Mode. 3042 * Add 1 to the effective privledge level to allow us to access the 3043 * Hypervisor CSRs. 3044 */ 3045 effective_priv++; 3046 } 3047 3048 if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { 3049 return RISCV_EXCP_ILLEGAL_INST; 3050 } 3051 #endif 3052 if (write_mask && read_only) { 3053 return RISCV_EXCP_ILLEGAL_INST; 3054 } 3055 3056 /* ensure the CSR extension is enabled. */ 3057 if (!cpu->cfg.ext_icsr) { 3058 return RISCV_EXCP_ILLEGAL_INST; 3059 } 3060 3061 /* check predicate */ 3062 if (!csr_ops[csrno].predicate) { 3063 return RISCV_EXCP_ILLEGAL_INST; 3064 } 3065 3066 if (env->priv_ver < csr_min_priv) { 3067 return RISCV_EXCP_ILLEGAL_INST; 3068 } 3069 3070 return csr_ops[csrno].predicate(env, csrno); 3071 } 3072 3073 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, 3074 target_ulong *ret_value, 3075 target_ulong new_value, 3076 target_ulong write_mask) 3077 { 3078 RISCVException ret; 3079 target_ulong old_value; 3080 3081 /* execute combined read/write operation if it exists */ 3082 if (csr_ops[csrno].op) { 3083 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); 3084 } 3085 3086 /* if no accessor exists then return failure */ 3087 if (!csr_ops[csrno].read) { 3088 return RISCV_EXCP_ILLEGAL_INST; 3089 } 3090 /* read old value */ 3091 ret = csr_ops[csrno].read(env, csrno, &old_value); 3092 if (ret != RISCV_EXCP_NONE) { 3093 return ret; 3094 } 3095 3096 /* write value if writable and write mask set, otherwise drop writes */ 3097 if (write_mask) { 3098 new_value = (old_value & ~write_mask) | (new_value & write_mask); 3099 if (csr_ops[csrno].write) { 3100 ret = csr_ops[csrno].write(env, csrno, new_value); 3101 if (ret != RISCV_EXCP_NONE) { 3102 return ret; 3103 } 3104 } 3105 } 3106 3107 /* return old value */ 3108 if (ret_value) { 3109 *ret_value = old_value; 3110 } 3111 3112 return RISCV_EXCP_NONE; 3113 } 3114 3115 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 3116 target_ulong *ret_value, 3117 target_ulong new_value, target_ulong write_mask) 3118 { 3119 RISCVCPU *cpu = env_archcpu(env); 3120 3121 RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu); 3122 if (ret != RISCV_EXCP_NONE) { 3123 return ret; 3124 } 3125 3126 return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask); 3127 } 3128 3129 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, 3130 Int128 *ret_value, 3131 Int128 new_value, 3132 Int128 write_mask) 3133 { 3134 RISCVException ret; 3135 Int128 old_value; 3136 3137 /* read old value */ 3138 ret = csr_ops[csrno].read128(env, csrno, &old_value); 3139 if (ret != RISCV_EXCP_NONE) { 3140 return ret; 3141 } 3142 3143 /* write value if writable and write mask set, otherwise drop writes */ 3144 if (int128_nz(write_mask)) { 3145 new_value = int128_or(int128_and(old_value, int128_not(write_mask)), 3146 int128_and(new_value, write_mask)); 3147 if (csr_ops[csrno].write128) { 3148 ret = csr_ops[csrno].write128(env, csrno, new_value); 3149 if (ret != RISCV_EXCP_NONE) { 3150 return ret; 3151 } 3152 } else if (csr_ops[csrno].write) { 3153 /* avoids having to write wrappers for all registers */ 3154 ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value)); 3155 if (ret != RISCV_EXCP_NONE) { 3156 return ret; 3157 } 3158 } 3159 } 3160 3161 /* return old value */ 3162 if (ret_value) { 3163 *ret_value = old_value; 3164 } 3165 3166 return RISCV_EXCP_NONE; 3167 } 3168 3169 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 3170 Int128 *ret_value, 3171 Int128 new_value, Int128 write_mask) 3172 { 3173 RISCVException ret; 3174 RISCVCPU *cpu = env_archcpu(env); 3175 3176 ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); 3177 if (ret != RISCV_EXCP_NONE) { 3178 return ret; 3179 } 3180 3181 if (csr_ops[csrno].read128) { 3182 return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); 3183 } 3184 3185 /* 3186 * Fall back to 64-bit version for now, if the 128-bit alternative isn't 3187 * at all defined. 3188 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non 3189 * significant), for those, this fallback is correctly handling the accesses 3190 */ 3191 target_ulong old_value; 3192 ret = riscv_csrrw_do64(env, csrno, &old_value, 3193 int128_getlo(new_value), 3194 int128_getlo(write_mask)); 3195 if (ret == RISCV_EXCP_NONE && ret_value) { 3196 *ret_value = int128_make64(old_value); 3197 } 3198 return ret; 3199 } 3200 3201 /* 3202 * Debugger support. If not in user mode, set env->debugger before the 3203 * riscv_csrrw call and clear it after the call. 3204 */ 3205 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 3206 target_ulong *ret_value, 3207 target_ulong new_value, 3208 target_ulong write_mask) 3209 { 3210 RISCVException ret; 3211 #if !defined(CONFIG_USER_ONLY) 3212 env->debugger = true; 3213 #endif 3214 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask); 3215 #if !defined(CONFIG_USER_ONLY) 3216 env->debugger = false; 3217 #endif 3218 return ret; 3219 } 3220 3221 /* Control and Status Register function table */ 3222 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 3223 /* User Floating-Point CSRs */ 3224 [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, 3225 [CSR_FRM] = { "frm", fs, read_frm, write_frm }, 3226 [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr }, 3227 /* Vector CSRs */ 3228 [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart, 3229 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3230 [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat, 3231 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3232 [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm, 3233 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3234 [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr, 3235 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3236 [CSR_VL] = { "vl", vs, read_vl, 3237 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3238 [CSR_VTYPE] = { "vtype", vs, read_vtype, 3239 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3240 [CSR_VLENB] = { "vlenb", vs, read_vlenb, 3241 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3242 /* User Timers and Counters */ 3243 [CSR_CYCLE] = { "cycle", ctr, read_instret }, 3244 [CSR_INSTRET] = { "instret", ctr, read_instret }, 3245 [CSR_CYCLEH] = { "cycleh", ctr32, read_instreth }, 3246 [CSR_INSTRETH] = { "instreth", ctr32, read_instreth }, 3247 3248 /* 3249 * In privileged mode, the monitor will have to emulate TIME CSRs only if 3250 * rdtime callback is not provided by machine/platform emulation. 3251 */ 3252 [CSR_TIME] = { "time", ctr, read_time }, 3253 [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, 3254 3255 #if !defined(CONFIG_USER_ONLY) 3256 /* Machine Timers and Counters */ 3257 [CSR_MCYCLE] = { "mcycle", any, read_instret }, 3258 [CSR_MINSTRET] = { "minstret", any, read_instret }, 3259 [CSR_MCYCLEH] = { "mcycleh", any32, read_instreth }, 3260 [CSR_MINSTRETH] = { "minstreth", any32, read_instreth }, 3261 3262 /* Machine Information Registers */ 3263 [CSR_MVENDORID] = { "mvendorid", any, read_zero }, 3264 [CSR_MARCHID] = { "marchid", any, read_zero }, 3265 [CSR_MIMPID] = { "mimpid", any, read_zero }, 3266 [CSR_MHARTID] = { "mhartid", any, read_mhartid }, 3267 3268 [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, 3269 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3270 /* Machine Trap Setup */ 3271 [CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL, 3272 read_mstatus_i128 }, 3273 [CSR_MISA] = { "misa", any, read_misa, write_misa, NULL, 3274 read_misa_i128 }, 3275 [CSR_MIDELEG] = { "mideleg", any, NULL, NULL, rmw_mideleg }, 3276 [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, 3277 [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, 3278 [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, 3279 [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, write_mcounteren }, 3280 3281 [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, 3282 3283 /* Machine Trap Handling */ 3284 [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, NULL, 3285 read_mscratch_i128, write_mscratch_i128 }, 3286 [CSR_MEPC] = { "mepc", any, read_mepc, write_mepc }, 3287 [CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause }, 3288 [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, 3289 [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, 3290 3291 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 3292 [CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect }, 3293 [CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg }, 3294 3295 /* Machine-Level Interrupts (AIA) */ 3296 [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, 3297 3298 /* Machine-Level IMSIC Interface (AIA) */ 3299 [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3300 [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3301 [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3302 [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum }, 3303 [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, 3304 3305 /* Virtual Interrupts for Supervisor Level (AIA) */ 3306 [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore }, 3307 [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore }, 3308 3309 /* Machine-Level High-Half CSRs (AIA) */ 3310 [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, 3311 [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, 3312 [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore }, 3313 [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, 3314 [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, 3315 3316 /* Execution environment configuration */ 3317 [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, 3318 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3319 [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, 3320 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3321 [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, 3322 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3323 [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg, 3324 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3325 [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, 3326 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3327 3328 /* Supervisor Trap Setup */ 3329 [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, 3330 read_sstatus_i128 }, 3331 [CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie }, 3332 [CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec }, 3333 [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren }, 3334 3335 /* Supervisor Trap Handling */ 3336 [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL, 3337 read_sscratch_i128, write_sscratch_i128 }, 3338 [CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc }, 3339 [CSR_SCAUSE] = { "scause", smode, read_scause, write_scause }, 3340 [CSR_STVAL] = { "stval", smode, read_stval, write_stval }, 3341 [CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip }, 3342 3343 /* Supervisor Protection and Translation */ 3344 [CSR_SATP] = { "satp", smode, read_satp, write_satp }, 3345 3346 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 3347 [CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect }, 3348 [CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg }, 3349 3350 /* Supervisor-Level Interrupts (AIA) */ 3351 [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, 3352 3353 /* Supervisor-Level IMSIC Interface (AIA) */ 3354 [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3355 [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3356 [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3357 [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum }, 3358 [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, 3359 3360 /* Supervisor-Level High-Half CSRs (AIA) */ 3361 [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, 3362 [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph }, 3363 3364 [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus, 3365 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3366 [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg, 3367 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3368 [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg, 3369 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3370 [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip, 3371 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3372 [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip, 3373 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3374 [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie, 3375 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3376 [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren, 3377 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3378 [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie, 3379 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3380 [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval, 3381 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3382 [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst, 3383 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3384 [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, 3385 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3386 [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp, 3387 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3388 [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta, 3389 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3390 [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah, 3391 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3392 3393 [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus, 3394 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3395 [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip, 3396 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3397 [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie , 3398 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3399 [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec, 3400 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3401 [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch, 3402 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3403 [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc, 3404 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3405 [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause, 3406 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3407 [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval, 3408 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3409 [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp, 3410 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3411 3412 [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2, 3413 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3414 [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst, 3415 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3416 3417 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 3418 [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, 3419 [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, 3420 [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, 3421 [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, 3422 3423 /* 3424 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) 3425 */ 3426 [CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect }, 3427 [CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg }, 3428 3429 /* VS-Level Interrupts (H-extension with AIA) */ 3430 [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, 3431 3432 /* VS-Level IMSIC Interface (H-extension with AIA) */ 3433 [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3434 [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3435 [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3436 [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum }, 3437 [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, 3438 3439 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 3440 [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, 3441 [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, 3442 [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, 3443 [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, 3444 [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, 3445 [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL, rmw_vsieh }, 3446 [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph }, 3447 3448 /* Physical Memory Protection */ 3449 [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg, 3450 .min_priv_ver = PRIV_VERSION_1_12_0 }, 3451 [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, 3452 [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, 3453 [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, 3454 [CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, 3455 [CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, 3456 [CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, 3457 [CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, 3458 [CSR_PMPADDR3] = { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, 3459 [CSR_PMPADDR4] = { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, 3460 [CSR_PMPADDR5] = { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, 3461 [CSR_PMPADDR6] = { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, 3462 [CSR_PMPADDR7] = { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, 3463 [CSR_PMPADDR8] = { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, 3464 [CSR_PMPADDR9] = { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, 3465 [CSR_PMPADDR10] = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, 3466 [CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, 3467 [CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, 3468 [CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, 3469 [CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, 3470 [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, 3471 3472 /* Debug CSRs */ 3473 [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, 3474 [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, 3475 [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, 3476 [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, 3477 3478 /* User Pointer Masking */ 3479 [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, 3480 [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask }, 3481 [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase }, 3482 /* Machine Pointer Masking */ 3483 [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte }, 3484 [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask }, 3485 [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase }, 3486 /* Supervisor Pointer Masking */ 3487 [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte }, 3488 [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask }, 3489 [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase }, 3490 3491 /* Performance Counters */ 3492 [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero }, 3493 [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero }, 3494 [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero }, 3495 [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero }, 3496 [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero }, 3497 [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero }, 3498 [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero }, 3499 [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero }, 3500 [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero }, 3501 [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero }, 3502 [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero }, 3503 [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero }, 3504 [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero }, 3505 [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero }, 3506 [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero }, 3507 [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero }, 3508 [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero }, 3509 [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero }, 3510 [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero }, 3511 [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero }, 3512 [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero }, 3513 [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero }, 3514 [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero }, 3515 [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero }, 3516 [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero }, 3517 [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero }, 3518 [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero }, 3519 [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero }, 3520 [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero }, 3521 3522 [CSR_MHPMCOUNTER3] = { "mhpmcounter3", any, read_zero }, 3523 [CSR_MHPMCOUNTER4] = { "mhpmcounter4", any, read_zero }, 3524 [CSR_MHPMCOUNTER5] = { "mhpmcounter5", any, read_zero }, 3525 [CSR_MHPMCOUNTER6] = { "mhpmcounter6", any, read_zero }, 3526 [CSR_MHPMCOUNTER7] = { "mhpmcounter7", any, read_zero }, 3527 [CSR_MHPMCOUNTER8] = { "mhpmcounter8", any, read_zero }, 3528 [CSR_MHPMCOUNTER9] = { "mhpmcounter9", any, read_zero }, 3529 [CSR_MHPMCOUNTER10] = { "mhpmcounter10", any, read_zero }, 3530 [CSR_MHPMCOUNTER11] = { "mhpmcounter11", any, read_zero }, 3531 [CSR_MHPMCOUNTER12] = { "mhpmcounter12", any, read_zero }, 3532 [CSR_MHPMCOUNTER13] = { "mhpmcounter13", any, read_zero }, 3533 [CSR_MHPMCOUNTER14] = { "mhpmcounter14", any, read_zero }, 3534 [CSR_MHPMCOUNTER15] = { "mhpmcounter15", any, read_zero }, 3535 [CSR_MHPMCOUNTER16] = { "mhpmcounter16", any, read_zero }, 3536 [CSR_MHPMCOUNTER17] = { "mhpmcounter17", any, read_zero }, 3537 [CSR_MHPMCOUNTER18] = { "mhpmcounter18", any, read_zero }, 3538 [CSR_MHPMCOUNTER19] = { "mhpmcounter19", any, read_zero }, 3539 [CSR_MHPMCOUNTER20] = { "mhpmcounter20", any, read_zero }, 3540 [CSR_MHPMCOUNTER21] = { "mhpmcounter21", any, read_zero }, 3541 [CSR_MHPMCOUNTER22] = { "mhpmcounter22", any, read_zero }, 3542 [CSR_MHPMCOUNTER23] = { "mhpmcounter23", any, read_zero }, 3543 [CSR_MHPMCOUNTER24] = { "mhpmcounter24", any, read_zero }, 3544 [CSR_MHPMCOUNTER25] = { "mhpmcounter25", any, read_zero }, 3545 [CSR_MHPMCOUNTER26] = { "mhpmcounter26", any, read_zero }, 3546 [CSR_MHPMCOUNTER27] = { "mhpmcounter27", any, read_zero }, 3547 [CSR_MHPMCOUNTER28] = { "mhpmcounter28", any, read_zero }, 3548 [CSR_MHPMCOUNTER29] = { "mhpmcounter29", any, read_zero }, 3549 [CSR_MHPMCOUNTER30] = { "mhpmcounter30", any, read_zero }, 3550 [CSR_MHPMCOUNTER31] = { "mhpmcounter31", any, read_zero }, 3551 3552 [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, 3553 [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, 3554 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, 3555 [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero }, 3556 [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero }, 3557 [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero }, 3558 [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero }, 3559 [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero }, 3560 [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero }, 3561 [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero }, 3562 [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero }, 3563 [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero }, 3564 [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero }, 3565 [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero }, 3566 [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero }, 3567 [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero }, 3568 [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero }, 3569 [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero }, 3570 [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero }, 3571 [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero }, 3572 [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero }, 3573 [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero }, 3574 [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero }, 3575 [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero }, 3576 [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero }, 3577 [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero }, 3578 [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero }, 3579 [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero }, 3580 [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero }, 3581 3582 [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero }, 3583 [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero }, 3584 [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero }, 3585 [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero }, 3586 [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero }, 3587 [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero }, 3588 [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero }, 3589 [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero }, 3590 [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero }, 3591 [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero }, 3592 [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero }, 3593 [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero }, 3594 [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero }, 3595 [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero }, 3596 [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero }, 3597 [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero }, 3598 [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero }, 3599 [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero }, 3600 [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero }, 3601 [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero }, 3602 [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero }, 3603 [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero }, 3604 [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero }, 3605 [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero }, 3606 [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero }, 3607 [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero }, 3608 [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero }, 3609 [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero }, 3610 [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero }, 3611 3612 [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero }, 3613 [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero }, 3614 [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero }, 3615 [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero }, 3616 [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero }, 3617 [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero }, 3618 [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero }, 3619 [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero }, 3620 [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero }, 3621 [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero }, 3622 [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero }, 3623 [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero }, 3624 [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero }, 3625 [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero }, 3626 [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero }, 3627 [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero }, 3628 [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero }, 3629 [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero }, 3630 [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero }, 3631 [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero }, 3632 [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero }, 3633 [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero }, 3634 [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero }, 3635 [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero }, 3636 [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero }, 3637 [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero }, 3638 [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero }, 3639 [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero }, 3640 [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero }, 3641 #endif /* !CONFIG_USER_ONLY */ 3642 }; 3643