xref: /openbmc/qemu/target/riscv/csr.c (revision b4a99d40) 
1 /*
2  * RISC-V Control and Status Registers.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25 
26 /* CSR function table public API */
27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
28 {
29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
30 }
31 
32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
33 {
34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
35 }
36 
37 /* Predicates */
38 static RISCVException fs(CPURISCVState *env, int csrno)
39 {
40 #if !defined(CONFIG_USER_ONLY)
41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
42         return RISCV_EXCP_ILLEGAL_INST;
43     }
44 #endif
45     return RISCV_EXCP_NONE;
46 }
47 
48 static RISCVException vs(CPURISCVState *env, int csrno)
49 {
50     CPUState *cs = env_cpu(env);
51     RISCVCPU *cpu = RISCV_CPU(cs);
52 
53     if (env->misa_ext & RVV ||
54         cpu->cfg.ext_zve64f) {
55 #if !defined(CONFIG_USER_ONLY)
56         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
57             return RISCV_EXCP_ILLEGAL_INST;
58         }
59 #endif
60         return RISCV_EXCP_NONE;
61     }
62     return RISCV_EXCP_ILLEGAL_INST;
63 }
64 
65 static RISCVException ctr(CPURISCVState *env, int csrno)
66 {
67 #if !defined(CONFIG_USER_ONLY)
68     CPUState *cs = env_cpu(env);
69     RISCVCPU *cpu = RISCV_CPU(cs);
70 
71     if (!cpu->cfg.ext_counters) {
72         /* The Counters extensions is not enabled */
73         return RISCV_EXCP_ILLEGAL_INST;
74     }
75 
76     if (riscv_cpu_virt_enabled(env)) {
77         switch (csrno) {
78         case CSR_CYCLE:
79             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
80                 get_field(env->mcounteren, COUNTEREN_CY)) {
81                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
82             }
83             break;
84         case CSR_TIME:
85             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
86                 get_field(env->mcounteren, COUNTEREN_TM)) {
87                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
88             }
89             break;
90         case CSR_INSTRET:
91             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
92                 get_field(env->mcounteren, COUNTEREN_IR)) {
93                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
94             }
95             break;
96         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
97             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
98                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
99                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
100             }
101             break;
102         }
103         if (riscv_cpu_mxl(env) == MXL_RV32) {
104             switch (csrno) {
105             case CSR_CYCLEH:
106                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
107                     get_field(env->mcounteren, COUNTEREN_CY)) {
108                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
109                 }
110                 break;
111             case CSR_TIMEH:
112                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
113                     get_field(env->mcounteren, COUNTEREN_TM)) {
114                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
115                 }
116                 break;
117             case CSR_INSTRETH:
118                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
119                     get_field(env->mcounteren, COUNTEREN_IR)) {
120                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
121                 }
122                 break;
123             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
124                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
125                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
126                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
127                 }
128                 break;
129             }
130         }
131     }
132 #endif
133     return RISCV_EXCP_NONE;
134 }
135 
136 static RISCVException ctr32(CPURISCVState *env, int csrno)
137 {
138     if (riscv_cpu_mxl(env) != MXL_RV32) {
139         return RISCV_EXCP_ILLEGAL_INST;
140     }
141 
142     return ctr(env, csrno);
143 }
144 
145 #if !defined(CONFIG_USER_ONLY)
146 static RISCVException any(CPURISCVState *env, int csrno)
147 {
148     return RISCV_EXCP_NONE;
149 }
150 
151 static RISCVException any32(CPURISCVState *env, int csrno)
152 {
153     if (riscv_cpu_mxl(env) != MXL_RV32) {
154         return RISCV_EXCP_ILLEGAL_INST;
155     }
156 
157     return any(env, csrno);
158 
159 }
160 
161 static RISCVException smode(CPURISCVState *env, int csrno)
162 {
163     if (riscv_has_ext(env, RVS)) {
164         return RISCV_EXCP_NONE;
165     }
166 
167     return RISCV_EXCP_ILLEGAL_INST;
168 }
169 
170 static RISCVException hmode(CPURISCVState *env, int csrno)
171 {
172     if (riscv_has_ext(env, RVS) &&
173         riscv_has_ext(env, RVH)) {
174         /* Hypervisor extension is supported */
175         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
176             env->priv == PRV_M) {
177             return RISCV_EXCP_NONE;
178         } else {
179             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
180         }
181     }
182 
183     return RISCV_EXCP_ILLEGAL_INST;
184 }
185 
186 static RISCVException hmode32(CPURISCVState *env, int csrno)
187 {
188     if (riscv_cpu_mxl(env) != MXL_RV32) {
189         if (riscv_cpu_virt_enabled(env)) {
190             return RISCV_EXCP_ILLEGAL_INST;
191         } else {
192             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
193         }
194     }
195 
196     return hmode(env, csrno);
197 
198 }
199 
200 /* Checks if PointerMasking registers could be accessed */
201 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
202 {
203     /* Check if j-ext is present */
204     if (riscv_has_ext(env, RVJ)) {
205         return RISCV_EXCP_NONE;
206     }
207     return RISCV_EXCP_ILLEGAL_INST;
208 }
209 
210 static RISCVException pmp(CPURISCVState *env, int csrno)
211 {
212     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
213         return RISCV_EXCP_NONE;
214     }
215 
216     return RISCV_EXCP_ILLEGAL_INST;
217 }
218 
219 static RISCVException epmp(CPURISCVState *env, int csrno)
220 {
221     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
222         return RISCV_EXCP_NONE;
223     }
224 
225     return RISCV_EXCP_ILLEGAL_INST;
226 }
227 #endif
228 
229 /* User Floating-Point CSRs */
230 static RISCVException read_fflags(CPURISCVState *env, int csrno,
231                                   target_ulong *val)
232 {
233     *val = riscv_cpu_get_fflags(env);
234     return RISCV_EXCP_NONE;
235 }
236 
237 static RISCVException write_fflags(CPURISCVState *env, int csrno,
238                                    target_ulong val)
239 {
240 #if !defined(CONFIG_USER_ONLY)
241     env->mstatus |= MSTATUS_FS;
242 #endif
243     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
244     return RISCV_EXCP_NONE;
245 }
246 
247 static RISCVException read_frm(CPURISCVState *env, int csrno,
248                                target_ulong *val)
249 {
250     *val = env->frm;
251     return RISCV_EXCP_NONE;
252 }
253 
254 static RISCVException write_frm(CPURISCVState *env, int csrno,
255                                 target_ulong val)
256 {
257 #if !defined(CONFIG_USER_ONLY)
258     env->mstatus |= MSTATUS_FS;
259 #endif
260     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
261     return RISCV_EXCP_NONE;
262 }
263 
264 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
265                                 target_ulong *val)
266 {
267     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
268         | (env->frm << FSR_RD_SHIFT);
269     return RISCV_EXCP_NONE;
270 }
271 
272 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
273                                  target_ulong val)
274 {
275 #if !defined(CONFIG_USER_ONLY)
276     env->mstatus |= MSTATUS_FS;
277 #endif
278     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
279     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
280     return RISCV_EXCP_NONE;
281 }
282 
283 static RISCVException read_vtype(CPURISCVState *env, int csrno,
284                                  target_ulong *val)
285 {
286     *val = env->vtype;
287     return RISCV_EXCP_NONE;
288 }
289 
290 static RISCVException read_vl(CPURISCVState *env, int csrno,
291                               target_ulong *val)
292 {
293     *val = env->vl;
294     return RISCV_EXCP_NONE;
295 }
296 
297 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
298 {
299     *val = env_archcpu(env)->cfg.vlen >> 3;
300     return RISCV_EXCP_NONE;
301 }
302 
303 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
304                                 target_ulong *val)
305 {
306     *val = env->vxrm;
307     return RISCV_EXCP_NONE;
308 }
309 
310 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
311                                  target_ulong val)
312 {
313 #if !defined(CONFIG_USER_ONLY)
314     env->mstatus |= MSTATUS_VS;
315 #endif
316     env->vxrm = val;
317     return RISCV_EXCP_NONE;
318 }
319 
320 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
321                                  target_ulong *val)
322 {
323     *val = env->vxsat;
324     return RISCV_EXCP_NONE;
325 }
326 
327 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
328                                   target_ulong val)
329 {
330 #if !defined(CONFIG_USER_ONLY)
331     env->mstatus |= MSTATUS_VS;
332 #endif
333     env->vxsat = val;
334     return RISCV_EXCP_NONE;
335 }
336 
337 static RISCVException read_vstart(CPURISCVState *env, int csrno,
338                                   target_ulong *val)
339 {
340     *val = env->vstart;
341     return RISCV_EXCP_NONE;
342 }
343 
344 static RISCVException write_vstart(CPURISCVState *env, int csrno,
345                                    target_ulong val)
346 {
347 #if !defined(CONFIG_USER_ONLY)
348     env->mstatus |= MSTATUS_VS;
349 #endif
350     /*
351      * The vstart CSR is defined to have only enough writable bits
352      * to hold the largest element index, i.e. lg2(VLEN) bits.
353      */
354     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
355     return RISCV_EXCP_NONE;
356 }
357 
358 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
359 {
360     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
361     return RISCV_EXCP_NONE;
362 }
363 
364 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
365 {
366 #if !defined(CONFIG_USER_ONLY)
367     env->mstatus |= MSTATUS_VS;
368 #endif
369     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
370     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
371     return RISCV_EXCP_NONE;
372 }
373 
374 /* User Timers and Counters */
375 static RISCVException read_instret(CPURISCVState *env, int csrno,
376                                    target_ulong *val)
377 {
378 #if !defined(CONFIG_USER_ONLY)
379     if (icount_enabled()) {
380         *val = icount_get();
381     } else {
382         *val = cpu_get_host_ticks();
383     }
384 #else
385     *val = cpu_get_host_ticks();
386 #endif
387     return RISCV_EXCP_NONE;
388 }
389 
390 static RISCVException read_instreth(CPURISCVState *env, int csrno,
391                                     target_ulong *val)
392 {
393 #if !defined(CONFIG_USER_ONLY)
394     if (icount_enabled()) {
395         *val = icount_get() >> 32;
396     } else {
397         *val = cpu_get_host_ticks() >> 32;
398     }
399 #else
400     *val = cpu_get_host_ticks() >> 32;
401 #endif
402     return RISCV_EXCP_NONE;
403 }
404 
405 #if defined(CONFIG_USER_ONLY)
406 static RISCVException read_time(CPURISCVState *env, int csrno,
407                                 target_ulong *val)
408 {
409     *val = cpu_get_host_ticks();
410     return RISCV_EXCP_NONE;
411 }
412 
413 static RISCVException read_timeh(CPURISCVState *env, int csrno,
414                                  target_ulong *val)
415 {
416     *val = cpu_get_host_ticks() >> 32;
417     return RISCV_EXCP_NONE;
418 }
419 
420 #else /* CONFIG_USER_ONLY */
421 
422 static RISCVException read_time(CPURISCVState *env, int csrno,
423                                 target_ulong *val)
424 {
425     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
426 
427     if (!env->rdtime_fn) {
428         return RISCV_EXCP_ILLEGAL_INST;
429     }
430 
431     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
432     return RISCV_EXCP_NONE;
433 }
434 
435 static RISCVException read_timeh(CPURISCVState *env, int csrno,
436                                  target_ulong *val)
437 {
438     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
439 
440     if (!env->rdtime_fn) {
441         return RISCV_EXCP_ILLEGAL_INST;
442     }
443 
444     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
445     return RISCV_EXCP_NONE;
446 }
447 
448 /* Machine constants */
449 
450 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
451 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
452 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
453 
454 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
455                                            VS_MODE_INTERRUPTS;
456 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
457 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
458                                      VS_MODE_INTERRUPTS;
459 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
460                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
461                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
462                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
463                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
464                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
465                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
466                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
467                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
468                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
469                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
470                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
471                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
472                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
473                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
474                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
475                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
476                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
477                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
478 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
479     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
480       (1ULL << (RISCV_EXCP_VS_ECALL)) |
481       (1ULL << (RISCV_EXCP_M_ECALL)) |
482       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
483       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
484       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
485       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
486 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
487     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
488     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
489 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
490 static const target_ulong hip_writable_mask = MIP_VSSIP;
491 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
492 static const target_ulong vsip_writable_mask = MIP_VSSIP;
493 
494 static const char valid_vm_1_10_32[16] = {
495     [VM_1_10_MBARE] = 1,
496     [VM_1_10_SV32] = 1
497 };
498 
499 static const char valid_vm_1_10_64[16] = {
500     [VM_1_10_MBARE] = 1,
501     [VM_1_10_SV39] = 1,
502     [VM_1_10_SV48] = 1,
503     [VM_1_10_SV57] = 1
504 };
505 
506 /* Machine Information Registers */
507 static RISCVException read_zero(CPURISCVState *env, int csrno,
508                                 target_ulong *val)
509 {
510     *val = 0;
511     return RISCV_EXCP_NONE;
512 }
513 
514 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
515                                    target_ulong *val)
516 {
517     *val = env->mhartid;
518     return RISCV_EXCP_NONE;
519 }
520 
521 /* Machine Trap Setup */
522 
523 /* We do not store SD explicitly, only compute it on demand. */
524 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
525 {
526     if ((status & MSTATUS_FS) == MSTATUS_FS ||
527         (status & MSTATUS_VS) == MSTATUS_VS ||
528         (status & MSTATUS_XS) == MSTATUS_XS) {
529         switch (xl) {
530         case MXL_RV32:
531             return status | MSTATUS32_SD;
532         case MXL_RV64:
533             return status | MSTATUS64_SD;
534         case MXL_RV128:
535             return MSTATUSH128_SD;
536         default:
537             g_assert_not_reached();
538         }
539     }
540     return status;
541 }
542 
543 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
544                                    target_ulong *val)
545 {
546     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
547     return RISCV_EXCP_NONE;
548 }
549 
550 static int validate_vm(CPURISCVState *env, target_ulong vm)
551 {
552     if (riscv_cpu_mxl(env) == MXL_RV32) {
553         return valid_vm_1_10_32[vm & 0xf];
554     } else {
555         return valid_vm_1_10_64[vm & 0xf];
556     }
557 }
558 
559 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
560                                     target_ulong val)
561 {
562     uint64_t mstatus = env->mstatus;
563     uint64_t mask = 0;
564 
565     /* flush tlb on mstatus fields that affect VM */
566     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
567             MSTATUS_MPRV | MSTATUS_SUM)) {
568         tlb_flush(env_cpu(env));
569     }
570     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
571         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
572         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
573         MSTATUS_TW | MSTATUS_VS;
574 
575     if (riscv_cpu_mxl(env) != MXL_RV32) {
576         /*
577          * RV32: MPV and GVA are not in mstatus. The current plan is to
578          * add them to mstatush. For now, we just don't support it.
579          */
580         mask |= MSTATUS_MPV | MSTATUS_GVA;
581     }
582 
583     mstatus = (mstatus & ~mask) | (val & mask);
584 
585     RISCVMXL xl = riscv_cpu_mxl(env);
586     if (xl > MXL_RV32) {
587         /* SXL and UXL fields are for now read only */
588         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
589         mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
590     }
591     env->mstatus = mstatus;
592 
593     return RISCV_EXCP_NONE;
594 }
595 
596 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
597                                     target_ulong *val)
598 {
599     *val = env->mstatus >> 32;
600     return RISCV_EXCP_NONE;
601 }
602 
603 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
604                                      target_ulong val)
605 {
606     uint64_t valh = (uint64_t)val << 32;
607     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
608 
609     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
610         tlb_flush(env_cpu(env));
611     }
612 
613     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
614 
615     return RISCV_EXCP_NONE;
616 }
617 
618 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
619                                         Int128 *val)
620 {
621     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
622     return RISCV_EXCP_NONE;
623 }
624 
625 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
626                                      Int128 *val)
627 {
628     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
629     return RISCV_EXCP_NONE;
630 }
631 
632 static RISCVException read_misa(CPURISCVState *env, int csrno,
633                                 target_ulong *val)
634 {
635     target_ulong misa;
636 
637     switch (env->misa_mxl) {
638     case MXL_RV32:
639         misa = (target_ulong)MXL_RV32 << 30;
640         break;
641 #ifdef TARGET_RISCV64
642     case MXL_RV64:
643         misa = (target_ulong)MXL_RV64 << 62;
644         break;
645 #endif
646     default:
647         g_assert_not_reached();
648     }
649 
650     *val = misa | env->misa_ext;
651     return RISCV_EXCP_NONE;
652 }
653 
654 static RISCVException write_misa(CPURISCVState *env, int csrno,
655                                  target_ulong val)
656 {
657     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
658         /* drop write to misa */
659         return RISCV_EXCP_NONE;
660     }
661 
662     /* 'I' or 'E' must be present */
663     if (!(val & (RVI | RVE))) {
664         /* It is not, drop write to misa */
665         return RISCV_EXCP_NONE;
666     }
667 
668     /* 'E' excludes all other extensions */
669     if (val & RVE) {
670         /* when we support 'E' we can do "val = RVE;" however
671          * for now we just drop writes if 'E' is present.
672          */
673         return RISCV_EXCP_NONE;
674     }
675 
676     /*
677      * misa.MXL writes are not supported by QEMU.
678      * Drop writes to those bits.
679      */
680 
681     /* Mask extensions that are not supported by this hart */
682     val &= env->misa_ext_mask;
683 
684     /* Mask extensions that are not supported by QEMU */
685     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
686 
687     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
688     if ((val & RVD) && !(val & RVF)) {
689         val &= ~RVD;
690     }
691 
692     /* Suppress 'C' if next instruction is not aligned
693      * TODO: this should check next_pc
694      */
695     if ((val & RVC) && (GETPC() & ~3) != 0) {
696         val &= ~RVC;
697     }
698 
699     /* If nothing changed, do nothing. */
700     if (val == env->misa_ext) {
701         return RISCV_EXCP_NONE;
702     }
703 
704     /* flush translation cache */
705     tb_flush(env_cpu(env));
706     env->misa_ext = val;
707     return RISCV_EXCP_NONE;
708 }
709 
710 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
711                                    target_ulong *val)
712 {
713     *val = env->medeleg;
714     return RISCV_EXCP_NONE;
715 }
716 
717 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
718                                     target_ulong val)
719 {
720     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
721     return RISCV_EXCP_NONE;
722 }
723 
724 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
725                                    target_ulong *val)
726 {
727     *val = env->mideleg;
728     return RISCV_EXCP_NONE;
729 }
730 
731 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
732                                     target_ulong val)
733 {
734     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
735     if (riscv_has_ext(env, RVH)) {
736         env->mideleg |= VS_MODE_INTERRUPTS;
737     }
738     return RISCV_EXCP_NONE;
739 }
740 
741 static RISCVException read_mie(CPURISCVState *env, int csrno,
742                                target_ulong *val)
743 {
744     *val = env->mie;
745     return RISCV_EXCP_NONE;
746 }
747 
748 static RISCVException write_mie(CPURISCVState *env, int csrno,
749                                 target_ulong val)
750 {
751     env->mie = (env->mie & ~all_ints) | (val & all_ints);
752     return RISCV_EXCP_NONE;
753 }
754 
755 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
756                                  target_ulong *val)
757 {
758     *val = env->mtvec;
759     return RISCV_EXCP_NONE;
760 }
761 
762 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
763                                   target_ulong val)
764 {
765     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
766     if ((val & 3) < 2) {
767         env->mtvec = val;
768     } else {
769         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
770     }
771     return RISCV_EXCP_NONE;
772 }
773 
774 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
775                                       target_ulong *val)
776 {
777     *val = env->mcounteren;
778     return RISCV_EXCP_NONE;
779 }
780 
781 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
782                                        target_ulong val)
783 {
784     env->mcounteren = val;
785     return RISCV_EXCP_NONE;
786 }
787 
788 /* Machine Trap Handling */
789 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
790                                          Int128 *val)
791 {
792     *val = int128_make128(env->mscratch, env->mscratchh);
793     return RISCV_EXCP_NONE;
794 }
795 
796 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
797                                           Int128 val)
798 {
799     env->mscratch = int128_getlo(val);
800     env->mscratchh = int128_gethi(val);
801     return RISCV_EXCP_NONE;
802 }
803 
804 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
805                                     target_ulong *val)
806 {
807     *val = env->mscratch;
808     return RISCV_EXCP_NONE;
809 }
810 
811 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
812                                      target_ulong val)
813 {
814     env->mscratch = val;
815     return RISCV_EXCP_NONE;
816 }
817 
818 static RISCVException read_mepc(CPURISCVState *env, int csrno,
819                                      target_ulong *val)
820 {
821     *val = env->mepc;
822     return RISCV_EXCP_NONE;
823 }
824 
825 static RISCVException write_mepc(CPURISCVState *env, int csrno,
826                                      target_ulong val)
827 {
828     env->mepc = val;
829     return RISCV_EXCP_NONE;
830 }
831 
832 static RISCVException read_mcause(CPURISCVState *env, int csrno,
833                                      target_ulong *val)
834 {
835     *val = env->mcause;
836     return RISCV_EXCP_NONE;
837 }
838 
839 static RISCVException write_mcause(CPURISCVState *env, int csrno,
840                                      target_ulong val)
841 {
842     env->mcause = val;
843     return RISCV_EXCP_NONE;
844 }
845 
846 static RISCVException read_mtval(CPURISCVState *env, int csrno,
847                                  target_ulong *val)
848 {
849     *val = env->mtval;
850     return RISCV_EXCP_NONE;
851 }
852 
853 static RISCVException write_mtval(CPURISCVState *env, int csrno,
854                                   target_ulong val)
855 {
856     env->mtval = val;
857     return RISCV_EXCP_NONE;
858 }
859 
860 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
861                               target_ulong *ret_value,
862                               target_ulong new_value, target_ulong write_mask)
863 {
864     RISCVCPU *cpu = env_archcpu(env);
865     /* Allow software control of delegable interrupts not claimed by hardware */
866     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
867     uint32_t old_mip;
868 
869     if (mask) {
870         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
871     } else {
872         old_mip = env->mip;
873     }
874 
875     if (ret_value) {
876         *ret_value = old_mip;
877     }
878 
879     return RISCV_EXCP_NONE;
880 }
881 
882 /* Supervisor Trap Setup */
883 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
884                                         Int128 *val)
885 {
886     uint64_t mask = sstatus_v1_10_mask;
887     uint64_t sstatus = env->mstatus & mask;
888 
889     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
890     return RISCV_EXCP_NONE;
891 }
892 
893 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
894                                    target_ulong *val)
895 {
896     target_ulong mask = (sstatus_v1_10_mask);
897 
898     /* TODO: Use SXL not MXL. */
899     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
900     return RISCV_EXCP_NONE;
901 }
902 
903 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
904                                     target_ulong val)
905 {
906     target_ulong mask = (sstatus_v1_10_mask);
907     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
908     return write_mstatus(env, CSR_MSTATUS, newval);
909 }
910 
911 static RISCVException read_vsie(CPURISCVState *env, int csrno,
912                                 target_ulong *val)
913 {
914     /* Shift the VS bits to their S bit location in vsie */
915     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
916     return RISCV_EXCP_NONE;
917 }
918 
919 static RISCVException read_sie(CPURISCVState *env, int csrno,
920                                target_ulong *val)
921 {
922     if (riscv_cpu_virt_enabled(env)) {
923         read_vsie(env, CSR_VSIE, val);
924     } else {
925         *val = env->mie & env->mideleg;
926     }
927     return RISCV_EXCP_NONE;
928 }
929 
930 static RISCVException write_vsie(CPURISCVState *env, int csrno,
931                                  target_ulong val)
932 {
933     /* Shift the S bits to their VS bit location in mie */
934     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
935                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
936     return write_mie(env, CSR_MIE, newval);
937 }
938 
939 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
940 {
941     if (riscv_cpu_virt_enabled(env)) {
942         write_vsie(env, CSR_VSIE, val);
943     } else {
944         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
945                               (val & S_MODE_INTERRUPTS);
946         write_mie(env, CSR_MIE, newval);
947     }
948 
949     return RISCV_EXCP_NONE;
950 }
951 
952 static RISCVException read_stvec(CPURISCVState *env, int csrno,
953                                  target_ulong *val)
954 {
955     *val = env->stvec;
956     return RISCV_EXCP_NONE;
957 }
958 
959 static RISCVException write_stvec(CPURISCVState *env, int csrno,
960                                   target_ulong val)
961 {
962     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
963     if ((val & 3) < 2) {
964         env->stvec = val;
965     } else {
966         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
967     }
968     return RISCV_EXCP_NONE;
969 }
970 
971 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
972                                       target_ulong *val)
973 {
974     *val = env->scounteren;
975     return RISCV_EXCP_NONE;
976 }
977 
978 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
979                                        target_ulong val)
980 {
981     env->scounteren = val;
982     return RISCV_EXCP_NONE;
983 }
984 
985 /* Supervisor Trap Handling */
986 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
987                                          Int128 *val)
988 {
989     *val = int128_make128(env->sscratch, env->sscratchh);
990     return RISCV_EXCP_NONE;
991 }
992 
993 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
994                                           Int128 val)
995 {
996     env->sscratch = int128_getlo(val);
997     env->sscratchh = int128_gethi(val);
998     return RISCV_EXCP_NONE;
999 }
1000 
1001 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
1002                                     target_ulong *val)
1003 {
1004     *val = env->sscratch;
1005     return RISCV_EXCP_NONE;
1006 }
1007 
1008 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1009                                      target_ulong val)
1010 {
1011     env->sscratch = val;
1012     return RISCV_EXCP_NONE;
1013 }
1014 
1015 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1016                                 target_ulong *val)
1017 {
1018     *val = env->sepc;
1019     return RISCV_EXCP_NONE;
1020 }
1021 
1022 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1023                                  target_ulong val)
1024 {
1025     env->sepc = val;
1026     return RISCV_EXCP_NONE;
1027 }
1028 
1029 static RISCVException read_scause(CPURISCVState *env, int csrno,
1030                                   target_ulong *val)
1031 {
1032     *val = env->scause;
1033     return RISCV_EXCP_NONE;
1034 }
1035 
1036 static RISCVException write_scause(CPURISCVState *env, int csrno,
1037                                    target_ulong val)
1038 {
1039     env->scause = val;
1040     return RISCV_EXCP_NONE;
1041 }
1042 
1043 static RISCVException read_stval(CPURISCVState *env, int csrno,
1044                                  target_ulong *val)
1045 {
1046     *val = env->stval;
1047     return RISCV_EXCP_NONE;
1048 }
1049 
1050 static RISCVException write_stval(CPURISCVState *env, int csrno,
1051                                   target_ulong val)
1052 {
1053     env->stval = val;
1054     return RISCV_EXCP_NONE;
1055 }
1056 
1057 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1058                                target_ulong *ret_value,
1059                                target_ulong new_value, target_ulong write_mask)
1060 {
1061     /* Shift the S bits to their VS bit location in mip */
1062     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
1063                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
1064 
1065     if (ret_value) {
1066         *ret_value &= VS_MODE_INTERRUPTS;
1067         /* Shift the VS bits to their S bit location in vsip */
1068         *ret_value >>= 1;
1069     }
1070     return ret;
1071 }
1072 
1073 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1074                               target_ulong *ret_value,
1075                               target_ulong new_value, target_ulong write_mask)
1076 {
1077     int ret;
1078 
1079     if (riscv_cpu_virt_enabled(env)) {
1080         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
1081     } else {
1082         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
1083                       write_mask & env->mideleg & sip_writable_mask);
1084     }
1085 
1086     if (ret_value) {
1087         *ret_value &= env->mideleg;
1088     }
1089     return ret;
1090 }
1091 
1092 /* Supervisor Protection and Translation */
1093 static RISCVException read_satp(CPURISCVState *env, int csrno,
1094                                 target_ulong *val)
1095 {
1096     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1097         *val = 0;
1098         return RISCV_EXCP_NONE;
1099     }
1100 
1101     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1102         return RISCV_EXCP_ILLEGAL_INST;
1103     } else {
1104         *val = env->satp;
1105     }
1106 
1107     return RISCV_EXCP_NONE;
1108 }
1109 
1110 static RISCVException write_satp(CPURISCVState *env, int csrno,
1111                                  target_ulong val)
1112 {
1113     target_ulong vm, mask, asid;
1114 
1115     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1116         return RISCV_EXCP_NONE;
1117     }
1118 
1119     if (riscv_cpu_mxl(env) == MXL_RV32) {
1120         vm = validate_vm(env, get_field(val, SATP32_MODE));
1121         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1122         asid = (val ^ env->satp) & SATP32_ASID;
1123     } else {
1124         vm = validate_vm(env, get_field(val, SATP64_MODE));
1125         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1126         asid = (val ^ env->satp) & SATP64_ASID;
1127     }
1128 
1129     if (vm && mask) {
1130         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1131             return RISCV_EXCP_ILLEGAL_INST;
1132         } else {
1133             if (asid) {
1134                 tlb_flush(env_cpu(env));
1135             }
1136             env->satp = val;
1137         }
1138     }
1139     return RISCV_EXCP_NONE;
1140 }
1141 
1142 /* Hypervisor Extensions */
1143 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1144                                    target_ulong *val)
1145 {
1146     *val = env->hstatus;
1147     if (riscv_cpu_mxl(env) != MXL_RV32) {
1148         /* We only support 64-bit VSXL */
1149         *val = set_field(*val, HSTATUS_VSXL, 2);
1150     }
1151     /* We only support little endian */
1152     *val = set_field(*val, HSTATUS_VSBE, 0);
1153     return RISCV_EXCP_NONE;
1154 }
1155 
1156 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1157                                     target_ulong val)
1158 {
1159     env->hstatus = val;
1160     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1161         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1162     }
1163     if (get_field(val, HSTATUS_VSBE) != 0) {
1164         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1165     }
1166     return RISCV_EXCP_NONE;
1167 }
1168 
1169 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1170                                    target_ulong *val)
1171 {
1172     *val = env->hedeleg;
1173     return RISCV_EXCP_NONE;
1174 }
1175 
1176 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1177                                     target_ulong val)
1178 {
1179     env->hedeleg = val & vs_delegable_excps;
1180     return RISCV_EXCP_NONE;
1181 }
1182 
1183 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1184                                    target_ulong *val)
1185 {
1186     *val = env->hideleg;
1187     return RISCV_EXCP_NONE;
1188 }
1189 
1190 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1191                                     target_ulong val)
1192 {
1193     env->hideleg = val & vs_delegable_ints;
1194     return RISCV_EXCP_NONE;
1195 }
1196 
1197 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1198                                target_ulong *ret_value,
1199                                target_ulong new_value, target_ulong write_mask)
1200 {
1201     int ret = rmw_mip(env, 0, ret_value, new_value,
1202                       write_mask & hvip_writable_mask);
1203 
1204     if (ret_value) {
1205         *ret_value &= hvip_writable_mask;
1206     }
1207     return ret;
1208 }
1209 
1210 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1211                               target_ulong *ret_value,
1212                               target_ulong new_value, target_ulong write_mask)
1213 {
1214     int ret = rmw_mip(env, 0, ret_value, new_value,
1215                       write_mask & hip_writable_mask);
1216 
1217     if (ret_value) {
1218         *ret_value &= hip_writable_mask;
1219     }
1220     return ret;
1221 }
1222 
1223 static RISCVException read_hie(CPURISCVState *env, int csrno,
1224                                target_ulong *val)
1225 {
1226     *val = env->mie & VS_MODE_INTERRUPTS;
1227     return RISCV_EXCP_NONE;
1228 }
1229 
1230 static RISCVException write_hie(CPURISCVState *env, int csrno,
1231                                 target_ulong val)
1232 {
1233     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1234     return write_mie(env, CSR_MIE, newval);
1235 }
1236 
1237 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1238                                       target_ulong *val)
1239 {
1240     *val = env->hcounteren;
1241     return RISCV_EXCP_NONE;
1242 }
1243 
1244 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1245                                        target_ulong val)
1246 {
1247     env->hcounteren = val;
1248     return RISCV_EXCP_NONE;
1249 }
1250 
1251 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1252                                   target_ulong val)
1253 {
1254     if (val) {
1255         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1256     }
1257     return RISCV_EXCP_NONE;
1258 }
1259 
1260 static RISCVException read_htval(CPURISCVState *env, int csrno,
1261                                  target_ulong *val)
1262 {
1263     *val = env->htval;
1264     return RISCV_EXCP_NONE;
1265 }
1266 
1267 static RISCVException write_htval(CPURISCVState *env, int csrno,
1268                                   target_ulong val)
1269 {
1270     env->htval = val;
1271     return RISCV_EXCP_NONE;
1272 }
1273 
1274 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1275                                   target_ulong *val)
1276 {
1277     *val = env->htinst;
1278     return RISCV_EXCP_NONE;
1279 }
1280 
1281 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1282                                    target_ulong val)
1283 {
1284     return RISCV_EXCP_NONE;
1285 }
1286 
1287 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1288                                   target_ulong val)
1289 {
1290     if (val) {
1291         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1292     }
1293     return RISCV_EXCP_NONE;
1294 }
1295 
1296 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1297                                  target_ulong *val)
1298 {
1299     *val = env->hgatp;
1300     return RISCV_EXCP_NONE;
1301 }
1302 
1303 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1304                                   target_ulong val)
1305 {
1306     env->hgatp = val;
1307     return RISCV_EXCP_NONE;
1308 }
1309 
1310 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1311                                       target_ulong *val)
1312 {
1313     if (!env->rdtime_fn) {
1314         return RISCV_EXCP_ILLEGAL_INST;
1315     }
1316 
1317     *val = env->htimedelta;
1318     return RISCV_EXCP_NONE;
1319 }
1320 
1321 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1322                                        target_ulong val)
1323 {
1324     if (!env->rdtime_fn) {
1325         return RISCV_EXCP_ILLEGAL_INST;
1326     }
1327 
1328     if (riscv_cpu_mxl(env) == MXL_RV32) {
1329         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1330     } else {
1331         env->htimedelta = val;
1332     }
1333     return RISCV_EXCP_NONE;
1334 }
1335 
1336 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1337                                        target_ulong *val)
1338 {
1339     if (!env->rdtime_fn) {
1340         return RISCV_EXCP_ILLEGAL_INST;
1341     }
1342 
1343     *val = env->htimedelta >> 32;
1344     return RISCV_EXCP_NONE;
1345 }
1346 
1347 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1348                                         target_ulong val)
1349 {
1350     if (!env->rdtime_fn) {
1351         return RISCV_EXCP_ILLEGAL_INST;
1352     }
1353 
1354     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1355     return RISCV_EXCP_NONE;
1356 }
1357 
1358 /* Virtual CSR Registers */
1359 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1360                                     target_ulong *val)
1361 {
1362     *val = env->vsstatus;
1363     return RISCV_EXCP_NONE;
1364 }
1365 
1366 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1367                                      target_ulong val)
1368 {
1369     uint64_t mask = (target_ulong)-1;
1370     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1371     return RISCV_EXCP_NONE;
1372 }
1373 
1374 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1375 {
1376     *val = env->vstvec;
1377     return RISCV_EXCP_NONE;
1378 }
1379 
1380 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1381                                    target_ulong val)
1382 {
1383     env->vstvec = val;
1384     return RISCV_EXCP_NONE;
1385 }
1386 
1387 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1388                                      target_ulong *val)
1389 {
1390     *val = env->vsscratch;
1391     return RISCV_EXCP_NONE;
1392 }
1393 
1394 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1395                                       target_ulong val)
1396 {
1397     env->vsscratch = val;
1398     return RISCV_EXCP_NONE;
1399 }
1400 
1401 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1402                                  target_ulong *val)
1403 {
1404     *val = env->vsepc;
1405     return RISCV_EXCP_NONE;
1406 }
1407 
1408 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1409                                   target_ulong val)
1410 {
1411     env->vsepc = val;
1412     return RISCV_EXCP_NONE;
1413 }
1414 
1415 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1416                                    target_ulong *val)
1417 {
1418     *val = env->vscause;
1419     return RISCV_EXCP_NONE;
1420 }
1421 
1422 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1423                                     target_ulong val)
1424 {
1425     env->vscause = val;
1426     return RISCV_EXCP_NONE;
1427 }
1428 
1429 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1430                                   target_ulong *val)
1431 {
1432     *val = env->vstval;
1433     return RISCV_EXCP_NONE;
1434 }
1435 
1436 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1437                                    target_ulong val)
1438 {
1439     env->vstval = val;
1440     return RISCV_EXCP_NONE;
1441 }
1442 
1443 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1444                                  target_ulong *val)
1445 {
1446     *val = env->vsatp;
1447     return RISCV_EXCP_NONE;
1448 }
1449 
1450 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1451                                   target_ulong val)
1452 {
1453     env->vsatp = val;
1454     return RISCV_EXCP_NONE;
1455 }
1456 
1457 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1458                                   target_ulong *val)
1459 {
1460     *val = env->mtval2;
1461     return RISCV_EXCP_NONE;
1462 }
1463 
1464 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1465                                    target_ulong val)
1466 {
1467     env->mtval2 = val;
1468     return RISCV_EXCP_NONE;
1469 }
1470 
1471 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1472                                   target_ulong *val)
1473 {
1474     *val = env->mtinst;
1475     return RISCV_EXCP_NONE;
1476 }
1477 
1478 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1479                                    target_ulong val)
1480 {
1481     env->mtinst = val;
1482     return RISCV_EXCP_NONE;
1483 }
1484 
1485 /* Physical Memory Protection */
1486 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1487                                    target_ulong *val)
1488 {
1489     *val = mseccfg_csr_read(env);
1490     return RISCV_EXCP_NONE;
1491 }
1492 
1493 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1494                          target_ulong val)
1495 {
1496     mseccfg_csr_write(env, val);
1497     return RISCV_EXCP_NONE;
1498 }
1499 
1500 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1501                                   target_ulong *val)
1502 {
1503     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1504     return RISCV_EXCP_NONE;
1505 }
1506 
1507 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1508                                    target_ulong val)
1509 {
1510     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1511     return RISCV_EXCP_NONE;
1512 }
1513 
1514 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1515                                    target_ulong *val)
1516 {
1517     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1518     return RISCV_EXCP_NONE;
1519 }
1520 
1521 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1522                                     target_ulong val)
1523 {
1524     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1525     return RISCV_EXCP_NONE;
1526 }
1527 
1528 /*
1529  * Functions to access Pointer Masking feature registers
1530  * We have to check if current priv lvl could modify
1531  * csr in given mode
1532  */
1533 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1534 {
1535     int csr_priv = get_field(csrno, 0x300);
1536     int pm_current;
1537 
1538     /*
1539      * If priv lvls differ that means we're accessing csr from higher priv lvl,
1540      * so allow the access
1541      */
1542     if (env->priv != csr_priv) {
1543         return false;
1544     }
1545     switch (env->priv) {
1546     case PRV_M:
1547         pm_current = get_field(env->mmte, M_PM_CURRENT);
1548         break;
1549     case PRV_S:
1550         pm_current = get_field(env->mmte, S_PM_CURRENT);
1551         break;
1552     case PRV_U:
1553         pm_current = get_field(env->mmte, U_PM_CURRENT);
1554         break;
1555     default:
1556         g_assert_not_reached();
1557     }
1558     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
1559     return !pm_current;
1560 }
1561 
1562 static RISCVException read_mmte(CPURISCVState *env, int csrno,
1563                                 target_ulong *val)
1564 {
1565     *val = env->mmte & MMTE_MASK;
1566     return RISCV_EXCP_NONE;
1567 }
1568 
1569 static RISCVException write_mmte(CPURISCVState *env, int csrno,
1570                                  target_ulong val)
1571 {
1572     uint64_t mstatus;
1573     target_ulong wpri_val = val & MMTE_MASK;
1574 
1575     if (val != wpri_val) {
1576         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1577                       "MMTE: WPRI violation written 0x", val,
1578                       "vs expected 0x", wpri_val);
1579     }
1580     /* for machine mode pm.current is hardwired to 1 */
1581     wpri_val |= MMTE_M_PM_CURRENT;
1582 
1583     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
1584     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1585     env->mmte = wpri_val | PM_EXT_DIRTY;
1586 
1587     /* Set XS and SD bits, since PM CSRs are dirty */
1588     mstatus = env->mstatus | MSTATUS_XS;
1589     write_mstatus(env, csrno, mstatus);
1590     return RISCV_EXCP_NONE;
1591 }
1592 
1593 static RISCVException read_smte(CPURISCVState *env, int csrno,
1594                                 target_ulong *val)
1595 {
1596     *val = env->mmte & SMTE_MASK;
1597     return RISCV_EXCP_NONE;
1598 }
1599 
1600 static RISCVException write_smte(CPURISCVState *env, int csrno,
1601                                  target_ulong val)
1602 {
1603     target_ulong wpri_val = val & SMTE_MASK;
1604 
1605     if (val != wpri_val) {
1606         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1607                       "SMTE: WPRI violation written 0x", val,
1608                       "vs expected 0x", wpri_val);
1609     }
1610 
1611     /* if pm.current==0 we can't modify current PM CSRs */
1612     if (check_pm_current_disabled(env, csrno)) {
1613         return RISCV_EXCP_NONE;
1614     }
1615 
1616     wpri_val |= (env->mmte & ~SMTE_MASK);
1617     write_mmte(env, csrno, wpri_val);
1618     return RISCV_EXCP_NONE;
1619 }
1620 
1621 static RISCVException read_umte(CPURISCVState *env, int csrno,
1622                                 target_ulong *val)
1623 {
1624     *val = env->mmte & UMTE_MASK;
1625     return RISCV_EXCP_NONE;
1626 }
1627 
1628 static RISCVException write_umte(CPURISCVState *env, int csrno,
1629                                  target_ulong val)
1630 {
1631     target_ulong wpri_val = val & UMTE_MASK;
1632 
1633     if (val != wpri_val) {
1634         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1635                       "UMTE: WPRI violation written 0x", val,
1636                       "vs expected 0x", wpri_val);
1637     }
1638 
1639     if (check_pm_current_disabled(env, csrno)) {
1640         return RISCV_EXCP_NONE;
1641     }
1642 
1643     wpri_val |= (env->mmte & ~UMTE_MASK);
1644     write_mmte(env, csrno, wpri_val);
1645     return RISCV_EXCP_NONE;
1646 }
1647 
1648 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1649                                    target_ulong *val)
1650 {
1651     *val = env->mpmmask;
1652     return RISCV_EXCP_NONE;
1653 }
1654 
1655 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1656                                     target_ulong val)
1657 {
1658     uint64_t mstatus;
1659 
1660     env->mpmmask = val;
1661     env->mmte |= PM_EXT_DIRTY;
1662 
1663     /* Set XS and SD bits, since PM CSRs are dirty */
1664     mstatus = env->mstatus | MSTATUS_XS;
1665     write_mstatus(env, csrno, mstatus);
1666     return RISCV_EXCP_NONE;
1667 }
1668 
1669 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1670                                    target_ulong *val)
1671 {
1672     *val = env->spmmask;
1673     return RISCV_EXCP_NONE;
1674 }
1675 
1676 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1677                                     target_ulong val)
1678 {
1679     uint64_t mstatus;
1680 
1681     /* if pm.current==0 we can't modify current PM CSRs */
1682     if (check_pm_current_disabled(env, csrno)) {
1683         return RISCV_EXCP_NONE;
1684     }
1685     env->spmmask = val;
1686     env->mmte |= PM_EXT_DIRTY;
1687 
1688     /* Set XS and SD bits, since PM CSRs are dirty */
1689     mstatus = env->mstatus | MSTATUS_XS;
1690     write_mstatus(env, csrno, mstatus);
1691     return RISCV_EXCP_NONE;
1692 }
1693 
1694 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1695                                    target_ulong *val)
1696 {
1697     *val = env->upmmask;
1698     return RISCV_EXCP_NONE;
1699 }
1700 
1701 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1702                                     target_ulong val)
1703 {
1704     uint64_t mstatus;
1705 
1706     /* if pm.current==0 we can't modify current PM CSRs */
1707     if (check_pm_current_disabled(env, csrno)) {
1708         return RISCV_EXCP_NONE;
1709     }
1710     env->upmmask = val;
1711     env->mmte |= PM_EXT_DIRTY;
1712 
1713     /* Set XS and SD bits, since PM CSRs are dirty */
1714     mstatus = env->mstatus | MSTATUS_XS;
1715     write_mstatus(env, csrno, mstatus);
1716     return RISCV_EXCP_NONE;
1717 }
1718 
1719 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1720                                    target_ulong *val)
1721 {
1722     *val = env->mpmbase;
1723     return RISCV_EXCP_NONE;
1724 }
1725 
1726 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1727                                     target_ulong val)
1728 {
1729     uint64_t mstatus;
1730 
1731     env->mpmbase = val;
1732     env->mmte |= PM_EXT_DIRTY;
1733 
1734     /* Set XS and SD bits, since PM CSRs are dirty */
1735     mstatus = env->mstatus | MSTATUS_XS;
1736     write_mstatus(env, csrno, mstatus);
1737     return RISCV_EXCP_NONE;
1738 }
1739 
1740 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1741                                    target_ulong *val)
1742 {
1743     *val = env->spmbase;
1744     return RISCV_EXCP_NONE;
1745 }
1746 
1747 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1748                                     target_ulong val)
1749 {
1750     uint64_t mstatus;
1751 
1752     /* if pm.current==0 we can't modify current PM CSRs */
1753     if (check_pm_current_disabled(env, csrno)) {
1754         return RISCV_EXCP_NONE;
1755     }
1756     env->spmbase = val;
1757     env->mmte |= PM_EXT_DIRTY;
1758 
1759     /* Set XS and SD bits, since PM CSRs are dirty */
1760     mstatus = env->mstatus | MSTATUS_XS;
1761     write_mstatus(env, csrno, mstatus);
1762     return RISCV_EXCP_NONE;
1763 }
1764 
1765 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1766                                    target_ulong *val)
1767 {
1768     *val = env->upmbase;
1769     return RISCV_EXCP_NONE;
1770 }
1771 
1772 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1773                                     target_ulong val)
1774 {
1775     uint64_t mstatus;
1776 
1777     /* if pm.current==0 we can't modify current PM CSRs */
1778     if (check_pm_current_disabled(env, csrno)) {
1779         return RISCV_EXCP_NONE;
1780     }
1781     env->upmbase = val;
1782     env->mmte |= PM_EXT_DIRTY;
1783 
1784     /* Set XS and SD bits, since PM CSRs are dirty */
1785     mstatus = env->mstatus | MSTATUS_XS;
1786     write_mstatus(env, csrno, mstatus);
1787     return RISCV_EXCP_NONE;
1788 }
1789 
1790 #endif
1791 
1792 /*
1793  * riscv_csrrw - read and/or update control and status register
1794  *
1795  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1796  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1797  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1798  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1799  */
1800 
1801 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
1802                                                int csrno,
1803                                                bool write_mask,
1804                                                RISCVCPU *cpu)
1805 {
1806     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
1807     int read_only = get_field(csrno, 0xC00) == 3;
1808 #if !defined(CONFIG_USER_ONLY)
1809     int effective_priv = env->priv;
1810 
1811     if (riscv_has_ext(env, RVH) &&
1812         env->priv == PRV_S &&
1813         !riscv_cpu_virt_enabled(env)) {
1814         /*
1815          * We are in S mode without virtualisation, therefore we are in HS Mode.
1816          * Add 1 to the effective privledge level to allow us to access the
1817          * Hypervisor CSRs.
1818          */
1819         effective_priv++;
1820     }
1821 
1822     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1823         return RISCV_EXCP_ILLEGAL_INST;
1824     }
1825 #endif
1826     if (write_mask && read_only) {
1827         return RISCV_EXCP_ILLEGAL_INST;
1828     }
1829 
1830     /* ensure the CSR extension is enabled. */
1831     if (!cpu->cfg.ext_icsr) {
1832         return RISCV_EXCP_ILLEGAL_INST;
1833     }
1834 
1835     /* check predicate */
1836     if (!csr_ops[csrno].predicate) {
1837         return RISCV_EXCP_ILLEGAL_INST;
1838     }
1839 
1840     return csr_ops[csrno].predicate(env, csrno);
1841 }
1842 
1843 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
1844                                        target_ulong *ret_value,
1845                                        target_ulong new_value,
1846                                        target_ulong write_mask)
1847 {
1848     RISCVException ret;
1849     target_ulong old_value;
1850 
1851     /* execute combined read/write operation if it exists */
1852     if (csr_ops[csrno].op) {
1853         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1854     }
1855 
1856     /* if no accessor exists then return failure */
1857     if (!csr_ops[csrno].read) {
1858         return RISCV_EXCP_ILLEGAL_INST;
1859     }
1860     /* read old value */
1861     ret = csr_ops[csrno].read(env, csrno, &old_value);
1862     if (ret != RISCV_EXCP_NONE) {
1863         return ret;
1864     }
1865 
1866     /* write value if writable and write mask set, otherwise drop writes */
1867     if (write_mask) {
1868         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1869         if (csr_ops[csrno].write) {
1870             ret = csr_ops[csrno].write(env, csrno, new_value);
1871             if (ret != RISCV_EXCP_NONE) {
1872                 return ret;
1873             }
1874         }
1875     }
1876 
1877     /* return old value */
1878     if (ret_value) {
1879         *ret_value = old_value;
1880     }
1881 
1882     return RISCV_EXCP_NONE;
1883 }
1884 
1885 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1886                            target_ulong *ret_value,
1887                            target_ulong new_value, target_ulong write_mask)
1888 {
1889     RISCVCPU *cpu = env_archcpu(env);
1890 
1891     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
1892     if (ret != RISCV_EXCP_NONE) {
1893         return ret;
1894     }
1895 
1896     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
1897 }
1898 
1899 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
1900                                         Int128 *ret_value,
1901                                         Int128 new_value,
1902                                         Int128 write_mask)
1903 {
1904     RISCVException ret;
1905     Int128 old_value;
1906 
1907     /* read old value */
1908     ret = csr_ops[csrno].read128(env, csrno, &old_value);
1909     if (ret != RISCV_EXCP_NONE) {
1910         return ret;
1911     }
1912 
1913     /* write value if writable and write mask set, otherwise drop writes */
1914     if (int128_nz(write_mask)) {
1915         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
1916                               int128_and(new_value, write_mask));
1917         if (csr_ops[csrno].write128) {
1918             ret = csr_ops[csrno].write128(env, csrno, new_value);
1919             if (ret != RISCV_EXCP_NONE) {
1920                 return ret;
1921             }
1922         } else if (csr_ops[csrno].write) {
1923             /* avoids having to write wrappers for all registers */
1924             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
1925             if (ret != RISCV_EXCP_NONE) {
1926                 return ret;
1927             }
1928         }
1929     }
1930 
1931     /* return old value */
1932     if (ret_value) {
1933         *ret_value = old_value;
1934     }
1935 
1936     return RISCV_EXCP_NONE;
1937 }
1938 
1939 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
1940                                 Int128 *ret_value,
1941                                 Int128 new_value, Int128 write_mask)
1942 {
1943     RISCVException ret;
1944     RISCVCPU *cpu = env_archcpu(env);
1945 
1946     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
1947     if (ret != RISCV_EXCP_NONE) {
1948         return ret;
1949     }
1950 
1951     if (csr_ops[csrno].read128) {
1952         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
1953     }
1954 
1955     /*
1956      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
1957      * at all defined.
1958      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
1959      * significant), for those, this fallback is correctly handling the accesses
1960      */
1961     target_ulong old_value;
1962     ret = riscv_csrrw_do64(env, csrno, &old_value,
1963                            int128_getlo(new_value),
1964                            int128_getlo(write_mask));
1965     if (ret == RISCV_EXCP_NONE && ret_value) {
1966         *ret_value = int128_make64(old_value);
1967     }
1968     return ret;
1969 }
1970 
1971 /*
1972  * Debugger support.  If not in user mode, set env->debugger before the
1973  * riscv_csrrw call and clear it after the call.
1974  */
1975 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
1976                                  target_ulong *ret_value,
1977                                  target_ulong new_value,
1978                                  target_ulong write_mask)
1979 {
1980     RISCVException ret;
1981 #if !defined(CONFIG_USER_ONLY)
1982     env->debugger = true;
1983 #endif
1984     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1985 #if !defined(CONFIG_USER_ONLY)
1986     env->debugger = false;
1987 #endif
1988     return ret;
1989 }
1990 
1991 /* Control and Status Register function table */
1992 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1993     /* User Floating-Point CSRs */
1994     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
1995     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
1996     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
1997     /* Vector CSRs */
1998     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
1999     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
2000     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
2001     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
2002     [CSR_VL]       = { "vl",       vs,     read_vl                    },
2003     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2004     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2005     /* User Timers and Counters */
2006     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2007     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2008     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2009     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2010 
2011     /*
2012      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2013      * rdtime callback is not provided by machine/platform emulation.
2014      */
2015     [CSR_TIME]  = { "time",  ctr,   read_time  },
2016     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2017 
2018 #if !defined(CONFIG_USER_ONLY)
2019     /* Machine Timers and Counters */
2020     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2021     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2022     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2023     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2024 
2025     /* Machine Information Registers */
2026     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2027     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2028     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2029     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2030 
2031     /* Machine Trap Setup */
2032     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2033                                                read_mstatus_i128                   },
2034     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2035                                                read_misa_i128                      },
2036     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
2037     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2038     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
2039     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2040     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2041 
2042     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2043 
2044     /* Machine Trap Handling */
2045     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2046                                          read_mscratch_i128, write_mscratch_i128   },
2047     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2048     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2049     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2050     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2051 
2052     /* Supervisor Trap Setup */
2053     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2054                                               read_sstatus_i128                 },
2055     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
2056     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2057     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2058 
2059     /* Supervisor Trap Handling */
2060     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2061                                           read_sscratch_i128, write_sscratch_i128  },
2062     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2063     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2064     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2065     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2066 
2067     /* Supervisor Protection and Translation */
2068     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2069 
2070     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2071     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2072     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
2073     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2074     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2075     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
2076     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2077     [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
2078     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2079     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2080     [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
2081     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2082     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2083     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2084 
2085     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2086     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2087     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
2088     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2089     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2090     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2091     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2092     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2093     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2094 
2095     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2096     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2097 
2098     /* Physical Memory Protection */
2099     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2100     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2101     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2102     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2103     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2104     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2105     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2106     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2107     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2108     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2109     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2110     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2111     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2112     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2113     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2114     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2115     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2116     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2117     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2118     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2119     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2120 
2121     /* User Pointer Masking */
2122     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2123     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2124     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2125     /* Machine Pointer Masking */
2126     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2127     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2128     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2129     /* Supervisor Pointer Masking */
2130     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2131     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2132     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2133 
2134     /* Performance Counters */
2135     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2136     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2137     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2138     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2139     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2140     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2141     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2142     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2143     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2144     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2145     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2146     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2147     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2148     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2149     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2150     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2151     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2152     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2153     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2154     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2155     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2156     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2157     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2158     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2159     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2160     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2161     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2162     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2163     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2164 
2165     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2166     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2167     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2168     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2169     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2170     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2171     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2172     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2173     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2174     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2175     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2176     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2177     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2178     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2179     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2180     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2181     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2182     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2183     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2184     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2185     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2186     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2187     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2188     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2189     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2190     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2191     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2192     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2193     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2194 
2195     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2196     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2197     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2198     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2199     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2200     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2201     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2202     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2203     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2204     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2205     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2206     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2207     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2208     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2209     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2210     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2211     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2212     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2213     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2214     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2215     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2216     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2217     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2218     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2219     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2220     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2221     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2222     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2223     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2224 
2225     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2226     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2227     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2228     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2229     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2230     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2231     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2232     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2233     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2234     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2235     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2236     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2237     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2238     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2239     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2240     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2241     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2242     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2243     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2244     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2245     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2246     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2247     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2248     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2249     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2250     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2251     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2252     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2253     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2254 
2255     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2256     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2257     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2258     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2259     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2260     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2261     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2262     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2263     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2264     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2265     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2266     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2267     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2268     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2269     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2270     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2271     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2272     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2273     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2274     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2275     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2276     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2277     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2278     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2279     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2280     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2281     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2282     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2283     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2284 #endif /* !CONFIG_USER_ONLY */
2285 };
2286